/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tlb.c |
---|
39,8 → 39,8 |
#include <arch/sun4v/hypercall.h> |
#include <arch/mm/frame.h> |
#include <arch/mm/page.h> |
#include <arch/mm/sun4v/tte.h> |
#include <arch/mm/sun4v/tlb.h> |
#include <arch/mm/tte.h> |
#include <arch/mm/tlb.h> |
#include <arch/interrupt.h> |
#include <interrupt.h> |
#include <arch.h> |
51,7 → 51,7 |
#include <arch/trap/exception.h> |
#include <panic.h> |
#include <arch/asm.h> |
#include <arch/sun4v/cpu.h> |
#include <arch/cpu.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/as.c |
---|
33,14 → 33,16 |
/** @file |
*/ |
/* SUN4V-OK */ |
#include <arch/mm/as.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <genarch/mm/page_ht.h> |
#include <genarch/mm/asid_fifo.h> |
#include <debug.h> |
#include <config.h> |
#include <arch/sun4v/hypercall.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
63,12 → 65,8 |
int as_constructor_arch(as_t *as, int flags) |
{ |
#ifdef CONFIG_TSB |
/* |
* The order must be calculated with respect to the emulated |
* 16K page size. |
*/ |
int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
int order = fnzb32( |
(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
75,12 → 73,15 |
if (!tsb) |
return -1; |
as->arch.itsb = (tsb_entry_t *) tsb; |
as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
sizeof(tsb_entry_t)); |
as->arch.tsb_description.page_size = PAGESIZE_8K; |
as->arch.tsb_description.associativity = 1; |
as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT; |
as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K; |
as->arch.tsb_description.tsb_base = tsb; |
as->arch.tsb_description.reserved = 0; |
memsetb(as->arch.itsb, |
(ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
memsetb((void *) as->arch.tsb_description.tsb_base, |
TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0); |
#endif |
return 0; |
} |
88,13 → 89,8 |
int as_destructor_arch(as_t *as) |
{ |
#ifdef CONFIG_TSB |
/* |
* The count must be calculated with respect to the emualted 16K page |
* size. |
*/ |
count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.tsb_description.tsb_base)); |
return cnt; |
#else |
return 0; |
105,6 → 101,7 |
{ |
#ifdef CONFIG_TSB |
tsb_invalidate(as, 0, (count_t) -1); |
as->arch.tsb_description.context = as->asid; |
#endif |
return 0; |
} |
118,33 → 115,14 |
*/ |
void as_install_arch(as_t *as) |
{ |
#if 0 |
tlb_context_reg_t ctx; |
mmu_secondary_context_write(as->asid); |
/* |
* Note that we don't and may not lock the address space. That's ok |
* since we only read members that are currently read-only. |
* |
* Moreover, the as->asid is protected by asidlock, which is being held. |
*/ |
/* |
* Write ASID to secondary context register. The primary context |
* register has to be set from TL>0 so it will be filled from the |
* secondary context register from the TL=1 code just before switch to |
* userspace. |
*/ |
ctx.v = 0; |
ctx.context = as->asid; |
mmu_secondary_context_write(ctx.v); |
#ifdef CONFIG_TSB |
uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
ASSERT(as->arch.itsb && as->arch.dtsb); |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
uintptr_t tsb = (uintptr_t) as->arch.itsb; |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
* TSBs were allocated from memory not covered |
151,43 → 129,15 |
* by the locked 4M kernel DTLB entry. We need |
* to map both TSBs explicitly. |
*/ |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); |
mmu_map_perm_addr( |
tsb, KA2PA(tsb), true, true, false, true, |
PAGESIZE_64K, MMU_FLAG_DTLB); |
} |
/* |
* Setup TSB Base registers. |
*/ |
tsb_base_reg_t tsb_base; |
__hypercall_fast2(MMU_TSB_CTX0, 1, as->arch.tsb_description.tsb_base); |
tsb_base.value = 0; |
tsb_base.size = TSB_SIZE; |
tsb_base.split = 0; |
tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
itsb_base_write(tsb_base.value); |
tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
dtsb_base_write(tsb_base.value); |
#if defined (US3) |
/* |
* Clear the extension registers. |
* In HelenOS, primary and secondary context registers contain |
* equal values and kernel misses (context 0, ie. the nucleus context) |
* are excluded from the TSB miss handler, so it makes no sense |
* to have separate TSBs for primary, secondary and nucleus contexts. |
* Clearing the extension registers will ensure that the value of the |
* TSB Base register will be used as an address of TSB, making the code |
* compatible with the US port. |
*/ |
itsb_primary_extension_write(0); |
itsb_nucleus_extension_write(0); |
dtsb_primary_extension_write(0); |
dtsb_secondary_extension_write(0); |
dtsb_nucleus_extension_write(0); |
#endif |
#endif |
#endif |
} |
/** Perform sparc64-specific tasks when an address space is removed from the |
199,7 → 149,6 |
*/ |
void as_deinstall_arch(as_t *as) |
{ |
/* |
* Note that we don't and may not lock the address space. That's ok |
* since we only read members that are currently read-only. |
206,13 → 155,12 |
* |
* Moreover, the as->asid is protected by asidlock, which is being held. |
*/ |
#ifdef CONFIG_TSB |
uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
ASSERT(as->arch.itsb && as->arch.dtsb); |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = (uintptr_t) as->arch.itsb; |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
220,7 → 168,7 |
* by the locked 4M kernel DTLB entry. We need |
* to demap the entry installed by as_install_arch(). |
*/ |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); |
} |
#endif |
} |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tsb.c |
---|
0,0 → 1,181 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* Copyright (c) 2009 Pavel Rimsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/mm/tsb.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/page.h> |
#include <arch/barrier.h> |
#include <mm/as.h> |
#include <arch/types.h> |
#include <macros.h> |
#include <debug.h> |
#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1) |
/** Invalidate portion of TSB. |
* |
* We assume that the address space is already locked. Note that respective |
* portions of both TSBs are invalidated at a time. |
* |
* @param as Address space. |
* @param page First page to invalidate in TSB. |
* @param pages Number of pages to invalidate. Value of (count_t) -1 means the |
* whole TSB. |
*/ |
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
{ |
index_t i0, i; |
count_t cnt; |
ASSERT(as->arch.tsb_description.tsb_base); |
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(i0 < TSB_ENTRY_COUNT); |
if (pages == (count_t) - 1 || (pages) > TSB_ENTRY_COUNT) |
cnt = TSB_ENTRY_COUNT; |
else |
cnt = pages; |
for (i = 0; i < cnt; i++) { |
((tsb_entry_t *) as->arch.tsb_description.tsb_base)[ |
(i0 + i) & (TSB_ENTRY_COUNT - 1)].tag.invalid = true; |
} |
} |
/** Copy software PTE to ITSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K subpage. |
*/ |
void itsb_pte_copy(pte_t *t, index_t index) |
{ |
#if 0 |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < ITSB_ENTRY_COUNT); |
tsb = &as->arch.itsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ |
tsb->data.p = t->k; /* p as privileged, k as kernel */ |
tsb->data.v = t->p; /* v as valid, p as present */ |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
#endif |
} |
/** Copy software PTE to DTSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
* @param ro If true, the mapping is copied read-only. |
*/ |
void dtsb_pte_copy(pte_t *t, index_t index, bool ro) |
{ |
#if 0 |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < DTSB_ENTRY_COUNT); |
tsb = &as->arch.dtsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_DCACHE |
tsb->data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_DCACHE */ |
tsb->data.p = t->k; /* p as privileged */ |
tsb->data.w = ro ? false : t->w; |
tsb->data.v = t->p; |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
#endif |
} |
/** @} |
*/ |