/branches/sparc/kernel/arch/sparc64/include/sun4v/hypercall.h |
---|
71,6 → 71,28 |
#define CONS_GETCHAR 0x60 |
#define CONS_PUTCHAR 0x61 |
/* return codes */ |
#define EOK 0 /**< Successful return */ |
#define ENOCPU 1 /**< Invalid CPU id */ |
#define ENORADDR 2 /**< Invalid real address */ |
#define ENOINTR 3 /**< Invalid interrupt id */ |
#define EBADPGSZ 4 /**< Invalid pagesize encoding */ |
#define EBADTSB 5 /**< Invalid TSB description */ |
#define EINVAL 6 /**< Invalid argument */ |
#define EBADTRAP 7 /**< Invalid function number */ |
#define EBADALIGN 8 /**< Invalid address alignment */ |
#define EWOULDBLOCK 9 /**< Cannot complete operation without blocking */ |
#define ENOACCESS 10 /**< No access to specified resource */ |
#define EIO 11 /**< I/O Error */ |
#define ECPUERROR 12 /**< CPU is in error state */ |
#define ENOTSUPPORTED 13 /**< Function not supported */ |
#define ENOMAP 14 /**< No mapping found */ |
#define ETOOMANY 15 /**< Too many items specified / limit reached */ |
#define ECHANNEL 16 /**< Invalid LDC channel */ |
#define EBUSY 17 /**< Operation failed as resource is otherwise busy */ |
/** |
* Performs a hyperfast hypervisor API call from the assembly language code. |
* Expects the registers %o1-%o4 are properly filled with the arguments of the |
114,7 → 136,7 |
__hypercall_fast(p1, p2, p3, p4, p5, function_number) |
/** |
* Performs a fast hypervisor API call. |
* Performs a fast hypervisor API call which can returns a value. |
* |
* @param p1 the 1st argument of the hypervisor API call |
* @param p2 the 2nd argument of the hypervisor API call |
122,10 → 144,14 |
* @param p4 the 4th argument of the hypervisor API call |
* @param p5 the 5th argument of the hypervisor API call |
* @param function_number function number of the call |
* @param ret1 pointer to an address where the return value |
* of the hypercall should be saved, or NULL |
* @return error status |
*/ |
static inline uint64_t |
__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3, |
const uint64_t p4, const uint64_t p5, const uint64_t function_number) |
__hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3, |
const uint64_t p4, const uint64_t p5, const uint64_t function_number, |
uint64_t * const ret1) |
{ |
register uint64_t a6 asm("o5") = function_number; |
register uint64_t a1 asm("o0") = p1; |
142,10 → 168,32 |
: "memory" |
); |
if (ret1 != NULL) |
*ret1 = a2; |
return a1; |
} |
/** |
* Performs a fast hypervisor API call which return no value except for the |
* error status. |
* |
* @param p1 the 1st argument of the hypervisor API call |
* @param p2 the 2nd argument of the hypervisor API call |
* @param p3 the 3rd argument of the hypervisor API call |
* @param p4 the 4th argument of the hypervisor API call |
* @param p5 the 5th argument of the hypervisor API call |
* @param function_number function number of the call |
* @return error status |
*/ |
static inline uint64_t |
__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3, |
const uint64_t p4, const uint64_t p5, const uint64_t function_number) |
{ |
return __hypercall_fast_ret1(p1, p2, p3, p4, p5, function_number, |
NULL); |
} |
/** |
* Performs a hyperfast hypervisor API call. |
* |
* @param p1 the 1st argument of the hypervisor API call |
/branches/sparc/kernel/arch/sparc64/include/trap/sun4v/mmu.h |
---|
40,7 → 40,7 |
#include <arch/stack.h> |
#include <arch/sun4v/regdef.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/sun4v/tlb.h> |
#include <arch/mm/sun4v/mmu.h> |
#include <arch/mm/sun4v/tte.h> |
#include <arch/trap/regwin.h> |
/branches/sparc/kernel/arch/sparc64/include/trap/sun4u/mmu.h |
---|
39,8 → 39,8 |
#include <arch/stack.h> |
#include <arch/sun4u/regdef.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/mmu.h> |
#include <arch/mm/sun4u/tte.h> |
#include <arch/trap/regwin.h> |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h |
---|
46,6 → 46,9 |
#define DTLB_MAX_LOCKED_ENTRIES 16 |
#endif |
#define MEM_CONTEXT_KERNEL 0 |
#define MEM_CONTEXT_TEMP 1 |
/** Bit width of the TLB-locked portion of kernel address space. */ |
#define KERNEL_PAGE_WIDTH 22 /* 4M */ |
91,7 → 94,7 |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <arch/register.h> |
#include <arch/cpu.h> |
#include <arch/sun4u/cpu.h> |
union tlb_context_reg { |
uint64_t v; |
128,7 → 131,7 |
* In US3, I-MMU and D-MMU have different formats of the data |
* access register virtual address. In the corresponding |
* structures the member variable for the entry number is |
* called "local_tlb_entry" - it contrast with the "tlb_entry" |
* called "local_tlb_entry" - it contrasts with the "tlb_entry" |
* for the US data access register VA structure. The rationale |
* behind this is to prevent careless mistakes in the code |
* caused by setting only the entry number and not the TLB |
230,7 → 233,7 |
*/ |
/** |
* Determine the number od entries in the DMMU's small TLB. |
* Determine the number of entries in the DMMU's small TLB. |
*/ |
static inline uint16_t tlb_dsmall_size(void) |
{ |
238,7 → 241,7 |
} |
/** |
* Determine the number od entries in each DMMU's big TLB. |
* Determine the number of entries in each DMMU's big TLB. |
*/ |
static inline uint16_t tlb_dbig_size(void) |
{ |
246,7 → 249,7 |
} |
/** |
* Determine the number od entries in the IMMU's small TLB. |
* Determine the number of entries in the IMMU's small TLB. |
*/ |
static inline uint16_t tlb_ismall_size(void) |
{ |
254,7 → 257,7 |
} |
/** |
* Determine the number od entries in the IMMU's big TLB. |
* Determine the number of entries in the IMMU's big TLB. |
*/ |
static inline uint16_t tlb_ibig_size(void) |
{ |
310,7 → 313,8 |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Data Access Register. |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(index_t entry) |
{ |
340,7 → 344,8 |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Data Access Register. |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(index_t entry) |
{ |
404,7 → 409,8 |
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Data Access Register. |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
{ |
438,7 → 444,8 |
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Data Access Register. |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
{ |
613,9 → 620,8 |
/** Perform IMMU TLB Demap Operation. |
* |
* @param type |
* Selects between context and page demap |
* (and entire MMU demap on US3). |
* @param type Selects between context and page demap (and entire MMU |
* demap on US3). |
* @param context_encoding Specifies which Context register has Context ID for |
* demap. |
* @param page Address which is on the page to be demapped. |
632,17 → 638,16 |
da.context = context_encoding; |
da.vpn = pg.vpn; |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
* address within the |
* ASI */ |
/* da.value is the address within the ASI */ |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
flush_pipeline(); |
} |
/** Perform DMMU TLB Demap Operation. |
* |
* @param type |
* Selects between context and page demap |
* (and entire MMU demap on US3). |
* @param type Selects between context and page demap (and entire MMU |
* demap on US3). |
* @param context_encoding Specifies which Context register has Context ID for |
* demap. |
* @param page Address which is on the page to be demapped. |
659,19 → 664,19 |
da.context = context_encoding; |
da.vpn = pg.vpn; |
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
* address within the |
* ASI */ |
/* da.value is the address within the ASI */ |
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
membar(); |
} |
extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); |
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); |
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
extern void dump_sfsr_and_sfar(void); |
extern void describe_mmu_fault(void); |
#endif /* !def __ASM__ */ |
/branches/sparc/kernel/arch/sparc64/include/cpu.h |
---|
35,22 → 35,6 |
#ifndef KERN_sparc64_CPU_H_ |
#define KERN_sparc64_CPU_H_ |
#define MANUF_FUJITSU 0x04 |
#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ |
#define MANUF_SUN 0x3e |
#define IMPL_ULTRASPARCI 0x10 |
#define IMPL_ULTRASPARCII 0x11 |
#define IMPL_ULTRASPARCII_I 0x12 |
#define IMPL_ULTRASPARCII_E 0x13 |
#define IMPL_ULTRASPARCIII 0x14 |
#define IMPL_ULTRASPARCIII_PLUS 0x15 |
#define IMPL_ULTRASPARCIII_I 0x16 |
#define IMPL_ULTRASPARCIV 0x18 |
#define IMPL_ULTRASPARCIV_PLUS 0x19 |
#define IMPL_SPARC64V 0x5 |
#ifndef __ASM__ |
#include <arch/types.h> |
57,13 → 41,7 |
#include <typedefs.h> |
#include <arch/register.h> |
#include <arch/sun4u/regdef.h> |
#include <arch/asm.h> |
#include <arch/sun4u/arch.h> |
#ifdef CONFIG_SMP |
#include <arch/mm/cache.h> |
#endif |
typedef struct { |
uint32_t mid; /**< Processor ID as read from |
UPA_CONFIG/FIREPLANE_CONFIG. */ |
74,30 → 52,9 |
matches this value. */ |
} cpu_arch_t; |
/** |
* Reads the module ID (agent ID/CPUID) of the current CPU. |
*/ |
static inline uint32_t read_mid(void) |
{ |
uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); |
icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; |
#if defined (US) |
return icbus_config & 0x1f; |
#elif defined (US3) |
if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I) |
return icbus_config & 0x1f; |
else |
return icbus_config & 0x3ff; |
#else |
panic("Not implemented for this architecture."); |
return 0; |
#endif |
} |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/drivers/tick.h |
---|
35,11 → 35,23 |
#ifndef KERN_sparc64_TICK_H_ |
#define KERN_sparc64_TICK_H_ |
#include <arch/asm.h> |
#include <arch/interrupt.h> |
/* mask of the "counter" field of the Tick register */ |
#define TICK_COUNTER_MASK (~(1l << 63)) |
extern void tick_init(void); |
extern void tick_interrupt(int n, istate_t *istate); |
/** |
* Reads the Tick register counter. |
*/ |
static inline uint64_t tick_counter_read(void) |
{ |
return TICK_COUNTER_MASK & tick_read(); |
} |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/cpu_family.h |
---|
39,6 → 39,7 |
#include <cpu.h> |
#include <arch/register.h> |
#include <arch/asm.h> |
#include <arch/sun4u/cpu.h> |
/** |
* Find the processor (sub)family. |