/branches/sparc/kernel/arch/sparc64/include/regdef.h |
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59,8 → 59,8 |
* The following definitions concern the UPA_CONFIG register on US and the |
* FIREPLANE_CONFIG register on US3. |
*/ |
#define UPA_CONFIG_MID_SHIFT 17 |
#define UPA_CONFIG_MID_MASK 0x1f |
#define ICBUS_CONFIG_MID_SHIFT 17 |
#define ICBUS_CONFIG_MID_MASK 0x1f |
#endif |
/branches/sparc/kernel/arch/sparc64/include/arch.h |
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41,7 → 41,7 |
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ |
#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ |
#define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
#define NWINDOWS 8 /** Number of register window sets. */ |
/branches/sparc/kernel/arch/sparc64/include/asm.h |
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364,9 → 364,9 |
* Value of the UPA_CONFIG register in US, |
* value of the FIREPLANE_CONFIG on US3. |
*/ |
static inline uint64_t upa_config_read(void) |
static inline uint64_t icbus_config_read(void) |
{ |
return asi_u64_read(ASI_UPA_CONFIG, 0); |
return asi_u64_read(ASI_ICBUS_CONFIG, 0); |
} |
extern void cpu_halt(void); |
/branches/sparc/kernel/arch/sparc64/include/register.h |
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123,7 → 123,7 |
* processor version to version. The format defined here |
* is the common subset for all supported processor versions. |
*/ |
union upa_config { |
union icbus_config { |
uint64_t value; |
struct { |
uint64_t : 34; |
132,7 → 132,7 |
unsigned pcap : 17; /**< Processor capabilities. */ |
} __attribute__ ((packed)); |
}; |
typedef union upa_config upa_config_t; |
typedef union icbus_config icbus_config_t; |
#endif |
/branches/sparc/kernel/arch/sparc64/include/cpu.h |
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52,7 → 52,10 |
#define IMPL_ULTRASPARCII 0x11 |
#define IMPL_ULTRASPARCII_I 0x12 |
#define IMPL_ULTRASPARCII_E 0x13 |
#define IMPL_ULTRASPARCIII 0x15 |
#define IMPL_ULTRASPARCIII 0x14 |
#define IMPL_ULTRASPARCIII_PLUS 0x15 |
#define IMPL_ULTRASPARCIII_I 0x16 |
#define IMPL_ULTRASPARCIV 0x18 |
#define IMPL_ULTRASPARCIV_PLUS 0x19 |
#define IMPL_SPARC64V 0x5 |
/branches/sparc/kernel/arch/sparc64/src/cpu/cpu.c |
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47,10 → 47,10 |
ofw_tree_node_t *node; |
uint32_t mid; |
uint32_t clock_frequency = 0; |
upa_config_t upa_config; |
icbus_config_t icbus_config; |
upa_config.value = upa_config_read(); |
CPU->arch.mid = upa_config.mid; |
icbus_config.value = icbus_config_read(); |
CPU->arch.mid = icbus_config.mid; |
/* |
* Detect processor frequency. |
/branches/sparc/kernel/arch/sparc64/src/start.S |
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301,9 → 301,9 |
* Read MID from the processor. |
*/ |
1: |
ldxa [%g0] ASI_UPA_CONFIG, %g1 |
srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
and %g1, UPA_CONFIG_MID_MASK, %g1 |
ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
and %g1, ICBUS_CONFIG_MID_MASK, %g1 |
#ifdef CONFIG_SMP |
/* |