| 110,28 → 110,18 |
|---|
| /* |
| * US3 processors have a write-invalidate cache, so explicitly |
| * invalidating it is not required. Whether to invalidate I-cache |
| * or not is decided according to the value of the ver.impl bits |
| * in the Version register. |
| * or not is decided according to the value of the global |
| * "subarchitecture" variable (set in the bootstrap). |
| */ |
| ! the lowest/greatest value of ver.impl for US3 |
| #define FIRST_US3_CPU 0x14 |
| #define LAST_US3_CPU 0x19 |
| rdpr %ver, %g2 ! autodetect CPU using the Version register |
| sllx %g2, 16, %g2 ! extract ver.impl bits |
| srlx %g2, 48, %g2 |
| addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU |
| bl 0f |
| set subarchitecture, %g2 |
| ldub [%g2], %g2 |
| cmp %g2, 3 |
| be 1f |
| nop |
| addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU |
| bg 0f |
| nop |
| ba 1f |
| nop |
| 0: |
| call icache_flush |
| nop |
| 1: |
| |
| membar #StoreStore |
| |
| /* |