| 108,15 → 108,36 |
|---|
| */ |
| |
| /* |
| * US-III processors have a write-invalidate cache, so flushing it is |
| * not required. We only use the FLUSH instruction to flush the |
| * pipeline. |
| */ |
| #ifdef US |
| call icache_flush |
| #endif |
| * US3 processors have a write-invalidate cache, so explicitly |
| * invalidating it is not required. Whether to invalidate I-cache |
| * or not is decided according to the value of the ver.impl bits |
| * in the Version register. |
| */ |
| sethi 0x40000, %g0 |
| ! the lowest/greatest value of ver.impl for US3 |
| #define FIRST_US3_CPU 0x14 |
| #define LAST_US3_CPU 0x19 |
| rdpr %ver, %g2 ! autodetect CPU using the Version register |
| sllx %g2, 16, %g2 ! extract ver.impl bits |
| srlx %g2, 48, %g2 |
| addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU |
| bl 0f |
| nop |
| addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU |
| bg 0f |
| nop |
| ba 1f |
| nop |
| 0: |
| call icache_flush |
| nop |
| 1: |
| |
| membar #StoreStore |
| membar #StoreStore |
| |
| /* |
| * Flush the instruction pipeline. |
| */ |
| flush %i7 |
| |
| mov %o0, %l1 |
| 143,7 → 164,6 |
|---|
| retl |
| ! SF Erratum #51 |
| nop |
| |
| .global ofw |
| ofw: |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |