/branches/sparc/kernel/test/synch/rwlock2.c |
---|
28,6 → 28,7 |
#include <test.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
/branches/sparc/kernel/test/synch/rwlock3.c |
---|
28,6 → 28,7 |
#include <test.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
/branches/sparc/kernel/test/synch/semaphore1.c |
---|
28,6 → 28,7 |
#include <test.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
/branches/sparc/kernel/test/synch/rwlock4.c |
---|
31,6 → 31,7 |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <arch/context.h> |
#include <context.h> |
/branches/sparc/kernel/test/synch/semaphore2.c |
---|
31,6 → 31,7 |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <arch/context.h> |
/branches/sparc/kernel/test/synch/rwlock5.c |
---|
28,6 → 28,7 |
#include <test.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <atomic.h> |
#include <print.h> |
#include <proc/thread.h> |
/branches/sparc/kernel/test/thread/thread1.c |
---|
35,6 → 35,7 |
#include <proc/thread.h> |
#include <arch.h> |
#include <arch/asm.h> |
#define THREADS 5 |
/branches/sparc/kernel/test/mm/falloc2.c |
---|
32,6 → 32,7 |
#include <mm/frame.h> |
#include <mm/slab.h> |
#include <arch/mm/page.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <atomic.h> |
#include <debug.h> |
/branches/sparc/kernel/test/mm/slab1.c |
---|
31,6 → 31,7 |
#include <print.h> |
#include <proc/thread.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <memstr.h> |
#define VAL_COUNT 1024 |
/branches/sparc/kernel/test/mm/slab2.c |
---|
31,6 → 31,7 |
#include <print.h> |
#include <proc/thread.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <mm/frame.h> |
#include <memstr.h> |
#include <synch/condvar.h> |
/branches/sparc/kernel/generic/src/synch/spinlock.c |
---|
43,6 → 43,7 |
#include <print.h> |
#include <debug.h> |
#include <symtab.h> |
#include <arch/asm.h> |
#ifdef CONFIG_FB |
#include <genarch/fb/fb.h> |
/branches/sparc/kernel/generic/src/synch/futex.c |
---|
53,6 → 53,7 |
#include <panic.h> |
#include <errno.h> |
#include <print.h> |
#include <arch/asm.h> |
#define FUTEX_HT_SIZE 1024 /* keep it a power of 2 */ |
/branches/sparc/kernel/generic/src/main/kinit.c |
---|
157,7 → 157,6 |
interrupts_enable(); |
#if defined (SUN4U) |
/* |
* Create user tasks, load RAM disk images. |
*/ |
215,7 → 214,6 |
} |
} |
#endif /* CONFIG_KCONSOLE */ |
#endif |
} |
/** @} |
/branches/sparc/kernel/generic/src/main/uinit.c |
---|
41,6 → 41,7 |
*/ |
#include <main/uinit.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <proc/thread.h> |
#include <userspace.h> |
/branches/sparc/kernel/generic/src/cpu/cpu.c |
---|
37,6 → 37,7 |
#include <cpu.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <arch/cpu.h> |
#include <mm/slab.h> |
#include <mm/page.h> |
/branches/sparc/kernel/generic/src/interrupt/interrupt.c |
---|
47,6 → 47,7 |
#include <panic.h> |
#include <print.h> |
#include <symtab.h> |
#include <arch/asm.h> |
static struct { |
const char *name; |
/branches/sparc/kernel/generic/src/time/clock.c |
---|
52,6 → 52,7 |
#include <atomic.h> |
#include <proc/thread.h> |
#include <sysinfo/sysinfo.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <mm/frame.h> |
#include <ddi/ddi.h> |
/branches/sparc/kernel/generic/src/ddi/ddi.c |
---|
51,6 → 51,7 |
#include <arch.h> |
#include <align.h> |
#include <errno.h> |
#include <arch/asm.h> |
/** This lock protects the parea_btree. */ |
SPINLOCK_INITIALIZE(parea_lock); |
/branches/sparc/kernel/generic/src/ddi/irq.c |
---|
68,6 → 68,7 |
#include <ddi/irq.h> |
#include <adt/hash_table.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <synch/spinlock.h> |
#include <arch.h> |
/branches/sparc/kernel/generic/src/console/console.c |
---|
38,6 → 38,7 |
#include <sysinfo/sysinfo.h> |
#include <synch/waitq.h> |
#include <synch/spinlock.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <ddi/device.h> |
#include <ddi/irq.h> |
/branches/sparc/kernel/generic/src/console/cmd.c |
---|
45,6 → 45,7 |
#include <console/kconsole.h> |
#include <print.h> |
#include <panic.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <adt/list.h> |
#include <arch.h> |
/branches/sparc/kernel/generic/src/proc/task.c |
---|
53,6 → 53,7 |
#include <errno.h> |
#include <func.h> |
#include <syscall/copy.h> |
#include <arch/asm.h> |
/** Spinlock protecting the tasks_tree AVL tree. */ |
SPINLOCK_INITIALIZE(tasks_lock); |
/branches/sparc/kernel/generic/src/proc/program.c |
---|
52,6 → 52,7 |
#include <print.h> |
#include <syscall/copy.h> |
#include <proc/program.h> |
#include <arch/asm.h> |
#ifndef LOADED_PROG_STACK_PAGES_NO |
#define LOADED_PROG_STACK_PAGES_NO 1 |
/branches/sparc/kernel/generic/src/security/cap.c |
---|
43,6 → 43,7 |
#include <syscall/sysarg64.h> |
#include <syscall/copy.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <errno.h> |
/** Set capabilities. |
/branches/sparc/kernel/generic/src/mm/slab.c |
---|
112,6 → 112,7 |
#include <debug.h> |
#include <bitops.h> |
#include <macros.h> |
#include <arch/asm.h> |
SPINLOCK_INITIALIZE(slab_cache_lock); |
static LIST_INITIALIZE(slab_cache_list); |
/branches/sparc/kernel/generic/src/mm/tlb.c |
---|
44,6 → 44,7 |
#include <smp/ipi.h> |
#include <synch/spinlock.h> |
#include <atomic.h> |
#include <arch/asm.h> |
#include <arch/interrupt.h> |
#include <config.h> |
#include <arch.h> |
/branches/sparc/kernel/generic/src/mm/backend_anon.c |
---|
46,6 → 46,7 |
#include <adt/list.h> |
#include <adt/btree.h> |
#include <errno.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <align.h> |
#include <arch.h> |
/branches/sparc/kernel/generic/src/mm/backend_phys.c |
---|
37,6 → 37,7 |
*/ |
#include <debug.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <mm/as.h> |
#include <mm/frame.h> |
/branches/sparc/kernel/generic/src/mm/backend_elf.c |
---|
37,6 → 37,7 |
#include <lib/elf.h> |
#include <debug.h> |
#include <arch/asm.h> |
#include <arch/types.h> |
#include <mm/as.h> |
#include <mm/frame.h> |
/branches/sparc/kernel/generic/src/syscall/copy.c |
---|
43,6 → 43,7 |
#include <mm/as.h> |
#include <macros.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <errno.h> |
/** Copy data from userspace to kernel. |
/branches/sparc/kernel/generic/src/syscall/syscall.c |
---|
54,6 → 54,7 |
#include <sysinfo/sysinfo.h> |
#include <console/console.h> |
#include <udebug/udebug.h> |
#include <arch/asm.h> |
/** Print using kernel facility |
* |
/branches/sparc/kernel/generic/src/ipc/ipcrsc.c |
---|
128,6 → 128,7 |
#include <synch/spinlock.h> |
#include <ipc/ipc.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <proc/task.h> |
#include <ipc/ipcrsc.h> |
#include <debug.h> |
/branches/sparc/kernel/generic/src/ipc/sysipc.c |
---|
44,6 → 44,7 |
#include <ipc/ipcrsc.h> |
#include <ipc/kbox.h> |
#include <udebug/udebug_ipc.h> |
#include <arch/asm.h> |
#include <arch/interrupt.h> |
#include <syscall/copy.h> |
#include <security/cap.h> |
/branches/sparc/kernel/generic/src/ipc/ipc.c |
---|
47,6 → 47,7 |
#include <errno.h> |
#include <mm/slab.h> |
#include <arch.h> |
#include <arch/asm.h> |
#include <proc/task.h> |
#include <memstr.h> |
#include <debug.h> |
/branches/sparc/kernel/generic/src/ipc/irq.c |
---|
49,6 → 49,7 |
*/ |
#include <arch.h> |
#include <arch/asm.h> |
#include <mm/slab.h> |
#include <errno.h> |
#include <ddi/irq.h> |
/branches/sparc/kernel/arch/sparc64/include/sun4v/regdef.h |
---|
36,6 → 36,7 |
#ifndef KERN_sparc64_sun4v_REGDEF_H_ |
#define KERN_sparc64_sun4v_REGDEF_H_ |
#define PSTATE_IE_BIT (1 << 1) |
#define PSTATE_PRIV_BIT (1 << 2) |
#define PSTATE_PEF_BIT (1 << 4) |
/branches/sparc/kernel/arch/sparc64/include/sun4v/cpu.h |
---|
37,6 → 37,15 |
#ifndef __ASM__ |
typedef struct { |
uint64_t id; /**< virtual processor ID */ |
uint32_t mid; // TODO: left here only to keep the code compilable!!! |
uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
uint64_t next_tick_cmpr; /**< Next clock interrupt should be |
generated when the TICK register |
matches this value. */ |
} cpu_arch_t; |
/* Maximum number of virtual processors. */ |
#define MAX_NUM_STRANDS 64 |
/branches/sparc/kernel/arch/sparc64/include/interrupt.h |
---|
37,7 → 37,7 |
#define KERN_sparc64_INTERRUPT_H_ |
#include <arch/types.h> |
#include <arch/sun4u/regdef.h> |
#include <arch/regdef.h> |
#define IVT_ITEMS 15 |
#define IVT_FIRST 1 |
/branches/sparc/kernel/arch/sparc64/include/regdef.h |
---|
0,0 → 1,47 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_REGDEF_H_ |
#define KERN_sparc64_REGDEF_H_ |
#if defined (SUN4U) |
#include <arch/sun4u/regdef.h> |
#elif defined (SUN4V) |
#include <arch/sun4v/regdef.h> |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/arch.h |
---|
37,6 → 37,12 |
#ifndef KERN_sparc64_ARCH_H_ |
#define KERN_sparc64_ARCH_H_ |
#if defined (SUN4U) |
#include <arch/sun4u/arch.h> |
#elif defined (SUN4V) |
#include <arch/sun4v/arch.h> |
#endif |
#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ |
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
/branches/sparc/kernel/arch/sparc64/include/trap/sun4v/mmu.h |
---|
39,12 → 39,12 |
#define KERN_sparc64_sun4v_MMU_TRAP_H_ |
#include <arch/stack.h> |
#include <arch/sun4v/regdef.h> |
#include <arch/sun4v/arch.h> |
#include <arch/regdef.h> |
#include <arch/arch.h> |
#include <arch/sun4v/hypercall.h> |
#include <arch/mm/sun4v/tlb.h> |
#include <arch/mm/sun4v/mmu.h> |
#include <arch/mm/sun4v/tte.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/trap/regwin.h> |
#ifdef CONFIG_TSB |
/branches/sparc/kernel/arch/sparc64/include/trap/mmu.h |
---|
0,0 → 1,49 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64interrupt |
* @{ |
*/ |
/** |
* @file |
* @brief This file contains fast MMU trap handlers. |
*/ |
#ifndef KERN_sparc64_sun4u_MMU_TRAP_H_ |
#define KERN_sparc64_sun4u_MMU_TRAP_H_ |
#if defined (SUN4U) |
#include <arch/trap/sun4u/mmu.h> |
#elif defined (SUN4V) |
#include <arch/trap/sun4v/mmu.h> |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/trap/sun4u/mmu.h |
---|
38,13 → 38,12 |
#define KERN_sparc64_sun4u_MMU_TRAP_H_ |
#include <arch/stack.h> |
#include <arch/sun4u/regdef.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/mmu.h> |
#include <arch/mm/sun4u/tte.h> |
#include <arch/regdef.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/trap/regwin.h> |
#include <arch/sun4u/arch.h> |
#include <arch/arch.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/frame.h |
---|
0,0 → 1,75 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4v_FRAME_H_ |
#define KERN_sparc64_sun4v_FRAME_H_ |
#define MMU_FRAME_WIDTH 13 /* 8K */ |
#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) |
#define FRAME_WIDTH 13 /* 8K */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/types.h> |
union frame_address { |
uintptr_t address; |
struct { |
#if defined (US) |
unsigned : 23; |
uint64_t pfn : 28; /**< Physical Frame Number. */ |
#elif defined (US3) |
unsigned : 21; |
uint64_t pfn : 30; /**< Physical Frame Number. */ |
#endif |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
}; |
typedef union frame_address frame_address_t; |
extern uintptr_t last_frame; |
extern void frame_arch_init(void); |
#define physmem_print() |
#endif |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tte.h |
---|
47,6 → 47,38 |
#define MMU_FLAG_ITLB 2 /**< operation applies to ITLB */ |
#define MMU_FLAG_DTLB 1 /**< operation applies to DTLB */ |
#ifndef __ASM__ |
#include <arch/types.h> |
/** Translation Table Entry - Data. */ |
/** SUN4V-OK */ |
union tte_data { |
uint64_t value; |
struct { |
unsigned v : 1; /**< Valid. */ |
unsigned nfo : 1; /**< No-Fault-Only. */ |
unsigned soft : 6; /**< Software defined field. */ |
unsigned long ra : 43; /**< Real address. */ |
unsigned ie : 1; /**< Invert endianess. */ |
unsigned e : 1; /**< Side-effect. */ |
unsigned cp : 1; /**< Cacheable in physically indexed cache. */ |
unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ |
unsigned p : 1; /**< Privileged. */ |
unsigned x : 1; /**< Executable. */ |
unsigned w : 1; /**< Writable. */ |
unsigned soft2 : 2; /**< Software defined field. */ |
unsigned size : 4; /**< Page size. */ |
} __attribute__ ((packed)); |
}; |
typedef union tte_data tte_data_t; |
// TODO: probably remove once tsb.c exists for both sun4u and sun4v |
#define VA_TAG_PAGE_SHIFT 22 |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/page.h |
---|
0,0 → 1,84 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4v_PAGE_H_ |
#define KERN_sparc64_sun4v_PAGE_H_ |
#include <arch/mm/frame.h> |
/* |
* On the TLB and TSB level, we still use 8K pages, which are supported by the |
* MMU. |
*/ |
#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH |
#define MMU_PAGE_SIZE MMU_FRAME_SIZE |
/* |
* On the page table level, we use 16K pages. 16K pages are not supported by |
* the MMU but we emulate them with pairs of 8K pages. |
*/ |
#define PAGE_WIDTH FRAME_WIDTH |
#define PAGE_SIZE FRAME_SIZE |
#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/interrupt.h> |
extern uintptr_t physmem_base; |
#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) |
#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) |
typedef union { |
uintptr_t address; |
struct { |
uint64_t vpn : 51; /**< Virtual Page Number. */ |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
} page_address_t; |
extern void page_arch_init(void); |
#endif /* !def __ASM__ */ |
#endif /* KERNEL */ |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/mmu.h |
---|
36,11 → 36,14 |
#ifndef KERN_sparc64_sun4v_MMU_H_ |
#define KERN_sparc64_sun4v_MMU_H_ |
#define ASI_REAL 0x14 |
#define ASI_REAL 0x14 /**< MMU bypass ASI */ |
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context registeri VA. */ |
#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< DMMU primary context register ASI. */ |
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< primary context register VA. */ |
#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< primary context register ASI. */ |
#define VA_SECONDARY_CONTEXT_REG 0x10 /**< secondary context register VA. */ |
#define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h |
---|
41,8 → 41,8 |
#ifndef __ASM__ |
#include <arch/mm/sun4v/tte.h> |
#include <arch/mm/sun4v/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/page.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
49,11 → 49,12 |
#include <arch/types.h> |
#include <arch/register.h> |
#include <arch/cpu.h> |
#include <arch/sun4v/hypercall.h> |
/** |
* Structure filled by hypervisor (or directly CPU, if implemented so) when |
* a MMU fault occurs. The structure describes the exact condition which |
* has caused the fault; |
* has caused the fault. |
*/ |
typedef struct mmu_fault_status_area { |
uint64_t ift; /**< Instruction fault type (IFT) */ |
67,181 → 68,20 |
uint8_t reserved2[0x28]; |
} __attribute__ ((packed)) mmu_fault_status_area_t; |
#if 0 |
union tlb_context_reg { |
uint64_t v; |
struct { |
unsigned long : 51; |
unsigned context : 13; /**< Context/ASID. */ |
} __attribute__ ((packed)); |
}; |
typedef union tlb_context_reg tlb_context_reg_t; |
#define DTLB_MAX_LOCKED_ENTRIES 8 |
/** Bit width of the TLB-locked portion of kernel address space. */ |
#define KERNEL_PAGE_WIDTH 22 /* 4M */ |
/** I-/D-TLB Data In/Access Register type. */ |
typedef tte_data_t tlb_data_t; |
/** I-/D-TLB Data Access Address in Alternate Space. */ |
#if defined (US) |
union tlb_data_access_addr { |
uint64_t value; |
struct { |
uint64_t : 55; |
unsigned tlb_entry : 6; |
unsigned : 3; |
} __attribute__ ((packed)); |
}; |
typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
typedef union tlb_data_access_addr itlb_data_access_addr_t; |
typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
#elif defined (US3) |
/* |
* In US3, I-MMU and D-MMU have different formats of the data |
* access register virtual address. In the corresponding |
* structures the member variable for the entry number is |
* called "local_tlb_entry" - it contrasts with the "tlb_entry" |
* for the US data access register VA structure. The rationale |
* behind this is to prevent careless mistakes in the code |
* caused by setting only the entry number and not the TLB |
* number in the US3 code (when taking the code from US). |
* Reading and writing context registers. |
* |
* Note that UltraSPARC Architecture-compatible processors do not require |
* a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an |
* MMU register for proper operation. |
* |
*/ |
union dtlb_data_access_addr { |
uint64_t value; |
struct { |
uint64_t : 45; |
unsigned : 1; |
unsigned tlb_number : 2; |
unsigned : 4; |
unsigned local_tlb_entry : 9; |
unsigned : 3; |
} __attribute__ ((packed)); |
}; |
typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
union itlb_data_access_addr { |
uint64_t value; |
struct { |
uint64_t : 45; |
unsigned : 1; |
unsigned tlb_number : 2; |
unsigned : 6; |
unsigned local_tlb_entry : 7; |
unsigned : 3; |
} __attribute__ ((packed)); |
}; |
typedef union itlb_data_access_addr itlb_data_access_addr_t; |
typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
#endif |
/** I-/D-TLB Tag Read Register. */ |
union tlb_tag_read_reg { |
uint64_t value; |
struct { |
uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
unsigned context : 13; /**< Context identifier. */ |
} __attribute__ ((packed)); |
}; |
typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
/** TLB Demap Operation Address. */ |
union tlb_demap_addr { |
uint64_t value; |
struct { |
uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
#if defined (US) |
unsigned : 6; /**< Ignored. */ |
unsigned type : 1; /**< The type of demap operation. */ |
#elif defined (US3) |
unsigned : 5; /**< Ignored. */ |
unsigned type: 2; /**< The type of demap operation. */ |
#endif |
unsigned context : 2; /**< Context register selection. */ |
unsigned : 4; /**< Zero. */ |
} __attribute__ ((packed)); |
}; |
typedef union tlb_demap_addr tlb_demap_addr_t; |
/** TLB Synchronous Fault Status Register. */ |
union tlb_sfsr_reg { |
uint64_t value; |
struct { |
#if defined (US) |
unsigned long : 40; /**< Implementation dependent. */ |
unsigned asi : 8; /**< ASI. */ |
unsigned : 2; |
unsigned ft : 7; /**< Fault type. */ |
#elif defined (US3) |
unsigned long : 39; /**< Implementation dependent. */ |
unsigned nf : 1; /**< Non-faulting load. */ |
unsigned asi : 8; /**< ASI. */ |
unsigned tm : 1; /**< I-TLB miss. */ |
unsigned : 3; /**< Reserved. */ |
unsigned ft : 5; /**< Fault type. */ |
#endif |
unsigned e : 1; /**< Side-effect bit. */ |
unsigned ct : 2; /**< Context Register selection. */ |
unsigned pr : 1; /**< Privilege bit. */ |
unsigned w : 1; /**< Write bit. */ |
unsigned ow : 1; /**< Overwrite bit. */ |
unsigned fv : 1; /**< Fault Valid bit. */ |
} __attribute__ ((packed)); |
}; |
typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
#if defined (US3) |
/* |
* Functions for determining the number of entries in TLBs. They either return |
* a constant value or a value based on the CPU autodetection. |
*/ |
/** |
* Determine the number of entries in the DMMU's small TLB. |
*/ |
static inline uint16_t tlb_dsmall_size(void) |
{ |
return 16; |
} |
/** |
* Determine the number of entries in each DMMU's big TLB. |
*/ |
static inline uint16_t tlb_dbig_size(void) |
{ |
return 512; |
} |
/** |
* Determine the number of entries in the IMMU's small TLB. |
*/ |
static inline uint16_t tlb_ismall_size(void) |
{ |
return 16; |
} |
/** |
* Determine the number of entries in the IMMU's big TLB. |
*/ |
static inline uint16_t tlb_ibig_size(void) |
{ |
if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
return 512; |
else |
return 128; |
} |
#endif |
/** Read MMU Primary Context Register. |
* |
* @return Current value of Primary Context Register. |
248,7 → 88,7 |
*/ |
static inline uint64_t mmu_primary_context_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); |
} |
/** Write MMU Primary Context Register. |
257,8 → 97,7 |
*/ |
static inline void mmu_primary_context_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
flush_pipeline(); |
asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); |
} |
/** Read MMU Secondary Context Register. |
267,330 → 106,18 |
*/ |
static inline uint64_t mmu_secondary_context_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); |
} |
/** Write MMU Primary Context Register. |
/** Write MMU Secondary Context Register. |
* |
* @param v New value of Primary Context Register. |
* @param v New value of Secondary Context Register. |
*/ |
static inline void mmu_secondary_context_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
flush_pipeline(); |
asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); |
} |
#if defined (US) |
/** Read IMMU TLB Data Access Register. |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(index_t entry) |
{ |
itlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_entry = entry; |
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
} |
/** Write IMMU TLB Data Access Register. |
* |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void itlb_data_access_write(index_t entry, uint64_t value) |
{ |
itlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_entry = entry; |
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
flush_pipeline(); |
} |
/** Read DMMU TLB Data Access Register. |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(index_t entry) |
{ |
dtlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_entry = entry; |
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
} |
/** Write DMMU TLB Data Access Register. |
* |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
{ |
dtlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_entry = entry; |
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
membar(); |
} |
/** Read IMMU TLB Tag Read Register. |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Tag Read Register. |
*/ |
static inline uint64_t itlb_tag_read_read(index_t entry) |
{ |
itlb_tag_read_addr_t tag; |
tag.value = 0; |
tag.tlb_entry = entry; |
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
} |
/** Read DMMU TLB Tag Read Register. |
* |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Tag Read Register. |
*/ |
static inline uint64_t dtlb_tag_read_read(index_t entry) |
{ |
dtlb_tag_read_addr_t tag; |
tag.value = 0; |
tag.tlb_entry = entry; |
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
} |
#elif defined (US3) |
/** Read IMMU TLB Data Access Register. |
* |
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
{ |
itlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_number = tlb; |
reg.local_tlb_entry = entry; |
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
} |
/** Write IMMU TLB Data Access Register. |
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void itlb_data_access_write(int tlb, index_t entry, |
uint64_t value) |
{ |
itlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_number = tlb; |
reg.local_tlb_entry = entry; |
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
flush_pipeline(); |
} |
/** Read DMMU TLB Data Access Register. |
* |
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
{ |
dtlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_number = tlb; |
reg.local_tlb_entry = entry; |
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
} |
/** Write DMMU TLB Data Access Register. |
* |
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void dtlb_data_access_write(int tlb, index_t entry, |
uint64_t value) |
{ |
dtlb_data_access_addr_t reg; |
reg.value = 0; |
reg.tlb_number = tlb; |
reg.local_tlb_entry = entry; |
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
membar(); |
} |
/** Read IMMU TLB Tag Read Register. |
* |
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified IMMU TLB Tag Read Register. |
*/ |
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
{ |
itlb_tag_read_addr_t tag; |
tag.value = 0; |
tag.tlb_number = tlb; |
tag.local_tlb_entry = entry; |
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
} |
/** Read DMMU TLB Tag Read Register. |
* |
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
* @param entry TLB Entry index. |
* |
* @return Current value of specified DMMU TLB Tag Read Register. |
*/ |
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
{ |
dtlb_tag_read_addr_t tag; |
tag.value = 0; |
tag.tlb_number = tlb; |
tag.local_tlb_entry = entry; |
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
} |
#endif |
/** Write IMMU TLB Tag Access Register. |
* |
* @param v Value to be written. |
*/ |
static inline void itlb_tag_access_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
flush_pipeline(); |
} |
/** Read IMMU TLB Tag Access Register. |
* |
* @return Current value of IMMU TLB Tag Access Register. |
*/ |
static inline uint64_t itlb_tag_access_read(void) |
{ |
return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
} |
/** Write DMMU TLB Tag Access Register. |
* |
* @param v Value to be written. |
*/ |
static inline void dtlb_tag_access_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
membar(); |
} |
/** Read DMMU TLB Tag Access Register. |
* |
* @return Current value of DMMU TLB Tag Access Register. |
*/ |
static inline uint64_t dtlb_tag_access_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
} |
/** Write IMMU TLB Data in Register. |
* |
* @param v Value to be written. |
*/ |
static inline void itlb_data_in_write(uint64_t v) |
{ |
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
flush_pipeline(); |
} |
/** Write DMMU TLB Data in Register. |
* |
* @param v Value to be written. |
*/ |
static inline void dtlb_data_in_write(uint64_t v) |
{ |
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
membar(); |
} |
/** Read ITLB Synchronous Fault Status Register. |
* |
* @return Current content of I-SFSR register. |
*/ |
static inline uint64_t itlb_sfsr_read(void) |
{ |
return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
} |
/** Write ITLB Synchronous Fault Status Register. |
* |
* @param v New value of I-SFSR register. |
*/ |
static inline void itlb_sfsr_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
flush_pipeline(); |
} |
/** Read DTLB Synchronous Fault Status Register. |
* |
* @return Current content of D-SFSR register. |
*/ |
static inline uint64_t dtlb_sfsr_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
} |
/** Write DTLB Synchronous Fault Status Register. |
* |
* @param v New value of D-SFSR register. |
*/ |
static inline void dtlb_sfsr_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
membar(); |
} |
/** Read DTLB Synchronous Fault Address Register. |
* |
* @return Current content of D-SFAR register. |
*/ |
static inline uint64_t dtlb_sfar_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
} |
/** Perform IMMU TLB Demap Operation. |
* |
* @param type Selects between context and page demap (and entire MMU |
601,26 → 128,12 |
*/ |
static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
{ |
tlb_demap_addr_t da; |
page_address_t pg; |
da.value = 0; |
pg.address = page; |
da.type = type; |
da.context = context_encoding; |
da.vpn = pg.vpn; |
/* da.value is the address within the ASI */ |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
flush_pipeline(); |
} |
/** Perform DMMU TLB Demap Operation. |
* |
* @param type Selects between context and page demap (and entire MMU |
* demap on US3). |
* @param type One of TLB_DEMAP_PAGE and TLB_DEMAP_CONTEXT. Selects |
* between context and page demap. |
* @param context_encoding Specifies which Context register has Context ID for |
* demap. |
* @param page Address which is on the page to be demapped. |
627,26 → 140,53 |
*/ |
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
{ |
tlb_demap_addr_t da; |
page_address_t pg; |
#if 0 |
- this implementation is not correct!!! |
if (type == TLB_DEMAP_PAGE) { |
__hypercall_fast5( |
MMU_DEMAP_PAGE, 0, 0, |
page, context_encoding, MMU_FLAG_DTLB); |
} else if (type == TLB_DEMAP_CONTEXT) { |
__hypercall_fast4( |
MMU_DEMAP_CTX, 0, 0, |
context_encoding, MMU_FLAG_DTLB); |
} |
#endif |
} |
da.value = 0; |
pg.address = page; |
/** |
* Demaps all mappings in a context. |
* |
* @param context number of the context |
* @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both |
*/ |
static inline void mmu_demap_ctx(int context, int mmu_flag) { |
__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); |
} |
da.type = type; |
da.context = context_encoding; |
da.vpn = pg.vpn; |
static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { |
__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); |
} |
/* da.value is the address within the ASI */ |
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
static inline void mmu_map_perm_addr(uintptr_t vaddr, uintptr_t ra, |
bool cacheable, bool privileged, bool executable, |
bool writable, unsigned size, unsigned mmu_flags) { |
membar(); |
tte_data_t data; |
data.value = 0; |
data.v = true; |
data.ra = ra; |
data.cp = data.cv = cacheable; |
data.p = privileged; |
data.x = executable; |
data.w = writable; |
data.size = size; |
__hypercall_fast4(MMU_MAP_PERM_ADDR, vaddr, 0, data.value, mmu_flags); |
} |
#endif |
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
//extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); |
//extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); |
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/as.h |
---|
0,0 → 1,103 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* Copyright (c) 2009 Pavel Rimsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4v_AS_H_ |
#define KERN_sparc64_sun4v_AS_H_ |
#include <arch/mm/tte.h> |
#include <arch/mm/tsb.h> |
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) |
#ifdef CONFIG_TSB |
/** |
* TTE Tag. |
* |
* Even though for sun4v the format of the TSB Tag states that the context |
* field has 16 bits, the T1 CPU still only supports 13-bit contexts and the |
* three most significant bits are always zero. |
*/ |
typedef union tte_tag { |
uint64_t value; |
struct { |
unsigned invalid : 1; /**< Invalidated by software. */ |
unsigned : 2; |
unsigned context : 13; /**< Software ASID. */ |
unsigned : 6; |
uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
} __attribute__ ((packed)); |
} tte_tag_t; |
/** TSB entry. */ |
typedef struct tsb_entry { |
tte_tag_t tag; |
tte_data_t data; |
} __attribute__ ((packed)) tsb_entry_t; |
typedef struct { |
tsb_descr_t tsb_description; |
} as_arch_t; |
#else |
typedef struct { |
} as_arch_t; |
#endif /* CONFIG_TSB */ |
#include <genarch/mm/as_ht.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
#define as_invalidate_translation_cache(as, page, cnt) \ |
tsb_invalidate((as), (page), (cnt)) |
#else |
#define as_invalidate_translation_cache(as, page, cnt) |
#endif |
extern void as_arch_init(void); |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tsb.h |
---|
0,0 → 1,82 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* Copyright (c) 2009 Pavel Rimsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4v_TSB_H_ |
#define KERN_sparc64_sun4v_TSB_H_ |
/* |
* TSB will claim 64K of memory, which |
* is a nice number considered that it is one of |
* the page sizes supported by hardware, which, |
* again, is nice because TSBs need to be locked |
* in TLBs - only one TLB entry will do. |
*/ |
#define TSB_SIZE 3 /* when changing this, change |
* as.c as well */ |
#define TSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
#ifndef __ASM__ |
#include <typedefs.h> |
#include <arch/mm/tte.h> |
#include <arch/mm/mmu.h> |
#include <arch/types.h> |
/** TSB description, used in hypercalls */ |
typedef struct tsb_descr { |
uint16_t page_size; /**< Page size (0 = 8K, 1 = 64K,...). */ |
uint16_t associativity; /**< TSB associativity (will be 1). */ |
uint32_t num_ttes; /**< Number of TTEs. */ |
uint32_t context; /**< Context number. */ |
uint32_t pgsize_mask; /**< Equals "1 << page_size". */ |
uint64_t tsb_base; /**< Real address of TSB base. */ |
uint64_t reserved; |
} __attribute__ ((packed)) tsb_descr_t; |
/* Forward declarations. */ |
struct as; |
struct pte; |
extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
extern void itsb_pte_copy(struct pte *t, index_t index); |
extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/frame.h |
---|
35,51 → 35,13 |
#ifndef KERN_sparc64_FRAME_H_ |
#define KERN_sparc64_FRAME_H_ |
/* |
* Page size supported by the MMU. |
* For 8K there is the nasty illegal virtual aliasing problem. |
* Therefore, the kernel uses 8K only internally on the TLB and TSB levels. |
*/ |
#define MMU_FRAME_WIDTH 13 /* 8K */ |
#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) |
/* |
* Page size exported to the generic memory management subsystems. |
* This page size is not directly supported by the MMU, but we can emulate |
* each 16K page with a pair of adjacent 8K pages. |
*/ |
#define FRAME_WIDTH 14 /* 16K */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/types.h> |
union frame_address { |
uintptr_t address; |
struct { |
#if defined (US) |
unsigned : 23; |
uint64_t pfn : 28; /**< Physical Frame Number. */ |
#elif defined (US3) |
unsigned : 21; |
uint64_t pfn : 30; /**< Physical Frame Number. */ |
#if defined (SUN4U) |
#include <arch/mm/sun4u/frame.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/frame.h> |
#endif |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
}; |
typedef union frame_address frame_address_t; |
extern uintptr_t last_frame; |
extern void frame_arch_init(void); |
#define physmem_print() |
#endif |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/page.h |
---|
35,49 → 35,12 |
#ifndef KERN_sparc64_PAGE_H_ |
#define KERN_sparc64_PAGE_H_ |
#include <arch/mm/frame.h> |
#if defined(SUN4U) |
#include <arch/mm/sun4u/page.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/page.h> |
#endif |
/* |
* On the TLB and TSB level, we still use 8K pages, which are supported by the |
* MMU. |
*/ |
#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH |
#define MMU_PAGE_SIZE MMU_FRAME_SIZE |
/* |
* On the page table level, we use 16K pages. 16K pages are not supported by |
* the MMU but we emulate them with pairs of 8K pages. |
*/ |
#define PAGE_WIDTH FRAME_WIDTH |
#define PAGE_SIZE FRAME_SIZE |
#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/interrupt.h> |
extern uintptr_t physmem_base; |
#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) |
#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) |
typedef union { |
uintptr_t address; |
struct { |
uint64_t vpn : 51; /**< Virtual Page Number. */ |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
} page_address_t; |
extern void page_arch_init(void); |
#endif /* !def __ASM__ */ |
#endif /* KERNEL */ |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/mm/tte.h |
---|
0,0 → 1,47 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_TTE_H_ |
#define KERN_sparc64_TTE_H_ |
#if defined (SUN4U) |
#include <arch/mm/sun4u/tte.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/tte.h> |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/mmu.h |
---|
0,0 → 1,47 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_MMU_H_ |
#define KERN_sparc64_MMU_H_ |
#if defined (SUN4U) |
#include <arch/mm/sun4u/mmu.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/mmu.h> |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h |
---|
0,0 → 1,47 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_TLB_H_ |
#define KERN_sparc64_TLB_H_ |
#if defined (SUN4U) |
#include <arch/mm/sun4u/tlb.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/tlb.h> |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/as.h |
---|
35,61 → 35,12 |
#ifndef KERN_sparc64_AS_H_ |
#define KERN_sparc64_AS_H_ |
#include <arch/mm/sun4u/tte.h> |
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) |
#ifdef CONFIG_TSB |
/** TSB Tag Target register. */ |
typedef union tsb_tag_target { |
uint64_t value; |
struct { |
unsigned invalid : 1; /**< Invalidated by software. */ |
unsigned : 2; |
unsigned context : 13; /**< Software ASID. */ |
unsigned : 6; |
uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
} __attribute__ ((packed)); |
} tsb_tag_target_t; |
/** TSB entry. */ |
typedef struct tsb_entry { |
tsb_tag_target_t tag; |
tte_data_t data; |
} __attribute__ ((packed)) tsb_entry_t; |
typedef struct { |
tsb_entry_t *itsb; |
tsb_entry_t *dtsb; |
} as_arch_t; |
#else |
typedef struct { |
} as_arch_t; |
#endif /* CONFIG_TSB */ |
#include <genarch/mm/as_ht.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
#define as_invalidate_translation_cache(as, page, cnt) \ |
tsb_invalidate((as), (page), (cnt)) |
#else |
#define as_invalidate_translation_cache(as, page, cnt) |
#if defined (SUN4U) |
#include <arch/mm/sun4u/as.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/as.h> |
#endif |
extern void as_arch_init(void); |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/frame.h |
---|
0,0 → 1,85 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4u_FRAME_H_ |
#define KERN_sparc64_sun4u_FRAME_H_ |
/* |
* Page size supported by the MMU. |
* For 8K there is the nasty illegal virtual aliasing problem. |
* Therefore, the kernel uses 8K only internally on the TLB and TSB levels. |
*/ |
#define MMU_FRAME_WIDTH 13 /* 8K */ |
#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) |
/* |
* Page size exported to the generic memory management subsystems. |
* This page size is not directly supported by the MMU, but we can emulate |
* each 16K page with a pair of adjacent 8K pages. |
*/ |
#define FRAME_WIDTH 14 /* 16K */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/types.h> |
union frame_address { |
uintptr_t address; |
struct { |
#if defined (US) |
unsigned : 23; |
uint64_t pfn : 28; /**< Physical Frame Number. */ |
#elif defined (US3) |
unsigned : 21; |
uint64_t pfn : 30; /**< Physical Frame Number. */ |
#endif |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
}; |
typedef union frame_address frame_address_t; |
extern uintptr_t last_frame; |
extern void frame_arch_init(void); |
#define physmem_print() |
#endif |
#endif |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/page.h |
---|
0,0 → 1,84 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4u_PAGE_H_ |
#define KERN_sparc64_sun4u_PAGE_H_ |
#include <arch/mm/frame.h> |
/* |
* On the TLB and TSB level, we still use 8K pages, which are supported by the |
* MMU. |
*/ |
#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH |
#define MMU_PAGE_SIZE MMU_FRAME_SIZE |
/* |
* On the page table level, we use 16K pages. 16K pages are not supported by |
* the MMU but we emulate them with pairs of 8K pages. |
*/ |
#define PAGE_WIDTH FRAME_WIDTH |
#define PAGE_SIZE FRAME_SIZE |
#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/interrupt.h> |
extern uintptr_t physmem_base; |
#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) |
#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) |
typedef union { |
uintptr_t address; |
struct { |
uint64_t vpn : 51; /**< Virtual Page Number. */ |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
} page_address_t; |
extern void page_arch_init(void); |
#endif /* !def __ASM__ */ |
#endif /* KERNEL */ |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h |
---|
87,14 → 87,14 |
#ifndef __ASM__ |
#include <arch/mm/sun4u/tte.h> |
#include <arch/mm/sun4u/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/page.h> |
#include <arch/asm.h> |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <arch/register.h> |
#include <arch/sun4u/cpu.h> |
#include <arch/cpu.h> |
union tlb_context_reg { |
uint64_t v; |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/as.h |
---|
0,0 → 1,96 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4u_AS_H_ |
#define KERN_sparc64_sun4u_AS_H_ |
#include <arch/mm/tte.h> |
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
#define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) |
#ifdef CONFIG_TSB |
/** TSB Tag Target register. */ |
typedef union tsb_tag_target { |
uint64_t value; |
struct { |
unsigned invalid : 1; /**< Invalidated by software. */ |
unsigned : 2; |
unsigned context : 13; /**< Software ASID. */ |
unsigned : 6; |
uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
} __attribute__ ((packed)); |
} tsb_tag_target_t; |
/** TSB entry. */ |
typedef struct tsb_entry { |
tsb_tag_target_t tag; |
tte_data_t data; |
} __attribute__ ((packed)) tsb_entry_t; |
typedef struct { |
tsb_entry_t *itsb; |
tsb_entry_t *dtsb; |
} as_arch_t; |
#else |
typedef struct { |
} as_arch_t; |
#endif /* CONFIG_TSB */ |
#include <genarch/mm/as_ht.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
#define as_invalidate_translation_cache(as, page, cnt) \ |
tsb_invalidate((as), (page), (cnt)) |
#else |
#define as_invalidate_translation_cache(as, page, cnt) |
#endif |
extern void as_arch_init(void); |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tsb.h |
---|
0,0 → 1,172 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_sun4u_TSB_H_ |
#define KERN_sparc64_sun4u_TSB_H_ |
/* |
* ITSB abd DTSB will claim 64K of memory, which |
* is a nice number considered that it is one of |
* the page sizes supported by hardware, which, |
* again, is nice because TSBs need to be locked |
* in TLBs - only one TLB entry will do. |
*/ |
#define TSB_SIZE 2 /* when changing this, change |
* as.c as well */ |
#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 |
#ifndef __ASM__ |
#include <arch/mm/tte.h> |
#include <arch/mm/mmu.h> |
#include <arch/types.h> |
/** TSB Base register. */ |
typedef union tsb_base_reg { |
uint64_t value; |
struct { |
uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
unsigned split : 1; /**< Split vs. common TSB for 8K and 64K |
* pages. HelenOS uses only 8K pages |
* for user mappings, so we always set |
* this to 0. |
*/ |
unsigned : 9; |
unsigned size : 3; /**< TSB size. Number of entries is |
* 512 * 2^size. */ |
} __attribute__ ((packed)); |
} tsb_base_reg_t; |
/** Read ITSB Base register. |
* |
* @return Content of the ITSB Base register. |
*/ |
static inline uint64_t itsb_base_read(void) |
{ |
return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
} |
/** Read DTSB Base register. |
* |
* @return Content of the DTSB Base register. |
*/ |
static inline uint64_t dtsb_base_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
} |
/** Write ITSB Base register. |
* |
* @param v New content of the ITSB Base register. |
*/ |
static inline void itsb_base_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
} |
/** Write DTSB Base register. |
* |
* @param v New content of the DTSB Base register. |
*/ |
static inline void dtsb_base_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
} |
#if defined (US3) |
/** Write DTSB Primary Extension register. |
* |
* @param v New content of the DTSB Primary Extension register. |
*/ |
static inline void dtsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); |
} |
/** Write DTSB Secondary Extension register. |
* |
* @param v New content of the DTSB Secondary Extension register. |
*/ |
static inline void dtsb_secondary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); |
} |
/** Write DTSB Nucleus Extension register. |
* |
* @param v New content of the DTSB Nucleus Extension register. |
*/ |
static inline void dtsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); |
} |
/** Write ITSB Primary Extension register. |
* |
* @param v New content of the ITSB Primary Extension register. |
*/ |
static inline void itsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); |
} |
/** Write ITSB Nucleus Extension register. |
* |
* @param v New content of the ITSB Nucleus Extension register. |
*/ |
static inline void itsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); |
} |
#endif |
/* Forward declarations. */ |
struct as; |
struct pte; |
extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
extern void itsb_pte_copy(struct pte *t, index_t index); |
extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/include/mm/tsb.h |
---|
35,137 → 35,12 |
#ifndef KERN_sparc64_TSB_H_ |
#define KERN_sparc64_TSB_H_ |
/* |
* ITSB abd DTSB will claim 64K of memory, which |
* is a nice number considered that it is one of |
* the page sizes supported by hardware, which, |
* again, is nice because TSBs need to be locked |
* in TLBs - only one TLB entry will do. |
*/ |
#define TSB_SIZE 2 /* when changing this, change |
* as.c as well */ |
#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 |
#ifndef __ASM__ |
#include <arch/mm/sun4u/tte.h> |
#include <arch/mm/sun4u/mmu.h> |
#include <arch/types.h> |
/** TSB Base register. */ |
typedef union tsb_base_reg { |
uint64_t value; |
struct { |
uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
unsigned split : 1; /**< Split vs. common TSB for 8K and 64K |
* pages. HelenOS uses only 8K pages |
* for user mappings, so we always set |
* this to 0. |
*/ |
unsigned : 9; |
unsigned size : 3; /**< TSB size. Number of entries is |
* 512 * 2^size. */ |
} __attribute__ ((packed)); |
} tsb_base_reg_t; |
/** Read ITSB Base register. |
* |
* @return Content of the ITSB Base register. |
*/ |
static inline uint64_t itsb_base_read(void) |
{ |
return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
} |
/** Read DTSB Base register. |
* |
* @return Content of the DTSB Base register. |
*/ |
static inline uint64_t dtsb_base_read(void) |
{ |
return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
} |
/** Write ITSB Base register. |
* |
* @param v New content of the ITSB Base register. |
*/ |
static inline void itsb_base_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
} |
/** Write DTSB Base register. |
* |
* @param v New content of the DTSB Base register. |
*/ |
static inline void dtsb_base_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
} |
#if defined (US3) |
/** Write DTSB Primary Extension register. |
* |
* @param v New content of the DTSB Primary Extension register. |
*/ |
static inline void dtsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); |
} |
/** Write DTSB Secondary Extension register. |
* |
* @param v New content of the DTSB Secondary Extension register. |
*/ |
static inline void dtsb_secondary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); |
} |
/** Write DTSB Nucleus Extension register. |
* |
* @param v New content of the DTSB Nucleus Extension register. |
*/ |
static inline void dtsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); |
} |
/** Write ITSB Primary Extension register. |
* |
* @param v New content of the ITSB Primary Extension register. |
*/ |
static inline void itsb_primary_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); |
} |
/** Write ITSB Nucleus Extension register. |
* |
* @param v New content of the ITSB Nucleus Extension register. |
*/ |
static inline void itsb_nucleus_extension_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); |
} |
#if defined (SUN4U) |
#include <arch/mm/sun4u/tsb.h> |
#elif defined (SUN4V) |
#include <arch/mm/sun4v/tsb.h> |
#endif |
/* Forward declarations. */ |
struct as; |
struct pte; |
extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
extern void itsb_pte_copy(struct pte *t, index_t index); |
extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
#endif /* !def __ASM__ */ |
#endif |
/** @} |
/branches/sparc/kernel/arch/sparc64/include/register.h |
---|
35,7 → 35,7 |
#ifndef KERN_sparc64_REGISTER_H_ |
#define KERN_sparc64_REGISTER_H_ |
#include <arch/sun4u/regdef.h> |
#include <arch/regdef.h> |
#include <arch/types.h> |
/** Version Register. */ |
/branches/sparc/kernel/arch/sparc64/include/cpu.h |
---|
37,24 → 37,11 |
#ifndef __ASM__ |
#include <arch/types.h> |
#include <typedefs.h> |
#include <arch/register.h> |
typedef struct { |
#if defined (SUN4U) |
uint32_t mid; /**< Processor ID as read from |
UPA_CONFIG/FIREPLANE_CONFIG. */ |
ver_reg_t ver; |
#include <arch/sun4u/cpu.h> |
#elif defined (SUN4V) |
uint64_t id; /**< virtual processor ID */ |
uint32_t mid; // TODO: left here only to keep the code compilable!!! |
#include <arch/sun4v/cpu.h> |
#endif |
uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
uint64_t next_tick_cmpr; /**< Next clock interrupt should be |
generated when the TICK register |
matches this value. */ |
} cpu_arch_t; |
#endif |
/branches/sparc/kernel/arch/sparc64/include/cpu_family.h |
---|
39,7 → 39,7 |
#include <cpu.h> |
#include <arch/register.h> |
#include <arch/asm.h> |
#include <arch/sun4u/cpu.h> |
#include <arch/cpu.h> |
/** |
* Find the processor (sub)family. |
/branches/sparc/kernel/arch/sparc64/include/sun4u/cpu.h |
---|
56,14 → 56,24 |
#include <arch/types.h> |
#include <typedefs.h> |
#include <arch/register.h> |
#include <arch/sun4u/regdef.h> |
#include <arch/regdef.h> |
#include <arch/asm.h> |
#include <arch/sun4u/arch.h> |
#include <arch/arch.h> |
#ifdef CONFIG_SMP |
#include <arch/mm/cache.h> |
#endif |
typedef struct { |
uint32_t mid; /**< Processor ID as read from |
UPA_CONFIG/FIREPLANE_CONFIG. */ |
ver_reg_t ver; |
uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
uint64_t next_tick_cmpr; /**< Next clock interrupt should be |
generated when the TICK register |
matches this value. */ |
} cpu_arch_t; |
/** |
* Reads the module ID (agent ID/CPUID) of the current CPU. |
*/ |
/branches/sparc/kernel/arch/sparc64/Makefile.inc |
---|
113,6 → 113,11 |
arch/$(ARCH)/src/mm/$(USARCH)/as.c \ |
arch/$(ARCH)/src/cpu/$(USARCH)/cpu.c \ |
ifeq ($(CONFIG_TSB),y) |
ARCH_SOURCES += \ |
arch/$(ARCH)/src/mm/$(USARCH)/tsb.c |
endif |
# specific to machine type |
# sun4u-specific, not #ifdef'd yet in order to make the code compilable |
152,10 → 157,6 |
arch/$(ARCH)/src/smp/$(USARCH)/smp.c |
endif |
ifeq ($(CONFIG_TSB),y) |
ARCH_SOURCES += \ |
arch/$(ARCH)/src/mm/tsb.c |
endif |
ifdef CONFIG_Z8530 |
ARCH_SOURCES += \ |
/branches/sparc/kernel/arch/sparc64/src/smp/sun4v/smp.c |
---|
36,7 → 36,6 |
#include <smp/smp.h> |
#include <genarch/ofw/ofw_tree.h> |
#include <cpu.h> |
#include <arch/cpu_family.h> |
#include <arch/cpu.h> |
#include <arch.h> |
#include <config.h> |
/branches/sparc/kernel/arch/sparc64/src/console.c |
---|
56,7 → 56,7 |
#include <arch/asm.h> |
#include <arch/register.h> |
#include <proc/thread.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <genarch/ofw/ofw_tree.h> |
#include <arch.h> |
#include <panic.h> |
/branches/sparc/kernel/arch/sparc64/src/trap/exception.c |
---|
34,8 → 34,7 |
*/ |
#include <arch/trap/exception.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <arch/interrupt.h> |
#include <interrupt.h> |
#include <arch/asm.h> |
/branches/sparc/kernel/arch/sparc64/src/trap/trap.c |
---|
38,7 → 38,7 |
#include <arch/trap/regwin.h> |
#include <arch/trap/exception.h> |
#include <arch/trap/interrupt.h> |
#include <arch/trap/sun4u/mmu.h> |
#include <arch/trap/mmu.h> |
#include <arch/asm.h> |
#include <memstr.h> |
#include <debug.h> |
/branches/sparc/kernel/arch/sparc64/src/cpu/sun4v/cpu.c |
---|
33,7 → 33,6 |
/** @file |
*/ |
#include <arch/cpu_family.h> |
#include <cpu.h> |
#include <arch.h> |
#include <genarch/ofw/ofw_tree.h> |
/branches/sparc/kernel/arch/sparc64/src/cpu/sun4u/cpu.c |
---|
39,7 → 39,7 |
#include <arch/drivers/tick.h> |
#include <print.h> |
#include <arch/cpu_node.h> |
#include <arch/sun4u/cpu.h> |
#include <arch/cpu.h> |
/** |
* Finds out the clock frequency of the current CPU. |
/branches/sparc/kernel/arch/sparc64/src/mm/tsb.c |
---|
File deleted |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tlb.c |
---|
39,8 → 39,8 |
#include <arch/sun4v/hypercall.h> |
#include <arch/mm/frame.h> |
#include <arch/mm/page.h> |
#include <arch/mm/sun4v/tte.h> |
#include <arch/mm/sun4v/tlb.h> |
#include <arch/mm/tte.h> |
#include <arch/mm/tlb.h> |
#include <arch/interrupt.h> |
#include <interrupt.h> |
#include <arch.h> |
51,7 → 51,7 |
#include <arch/trap/exception.h> |
#include <panic.h> |
#include <arch/asm.h> |
#include <arch/sun4v/cpu.h> |
#include <arch/cpu.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/as.c |
---|
33,14 → 33,16 |
/** @file |
*/ |
/* SUN4V-OK */ |
#include <arch/mm/as.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <genarch/mm/page_ht.h> |
#include <genarch/mm/asid_fifo.h> |
#include <debug.h> |
#include <config.h> |
#include <arch/sun4v/hypercall.h> |
#ifdef CONFIG_TSB |
#include <arch/mm/tsb.h> |
63,12 → 65,8 |
int as_constructor_arch(as_t *as, int flags) |
{ |
#ifdef CONFIG_TSB |
/* |
* The order must be calculated with respect to the emulated |
* 16K page size. |
*/ |
int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
int order = fnzb32( |
(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
75,12 → 73,15 |
if (!tsb) |
return -1; |
as->arch.itsb = (tsb_entry_t *) tsb; |
as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
sizeof(tsb_entry_t)); |
as->arch.tsb_description.page_size = PAGESIZE_8K; |
as->arch.tsb_description.associativity = 1; |
as->arch.tsb_description.num_ttes = TSB_ENTRY_COUNT; |
as->arch.tsb_description.pgsize_mask = 1 << PAGESIZE_8K; |
as->arch.tsb_description.tsb_base = tsb; |
as->arch.tsb_description.reserved = 0; |
memsetb(as->arch.itsb, |
(ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
memsetb((void *) as->arch.tsb_description.tsb_base, |
TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0); |
#endif |
return 0; |
} |
88,13 → 89,8 |
int as_destructor_arch(as_t *as) |
{ |
#ifdef CONFIG_TSB |
/* |
* The count must be calculated with respect to the emualted 16K page |
* size. |
*/ |
count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.tsb_description.tsb_base)); |
return cnt; |
#else |
return 0; |
105,6 → 101,7 |
{ |
#ifdef CONFIG_TSB |
tsb_invalidate(as, 0, (count_t) -1); |
as->arch.tsb_description.context = as->asid; |
#endif |
return 0; |
} |
118,33 → 115,14 |
*/ |
void as_install_arch(as_t *as) |
{ |
#if 0 |
tlb_context_reg_t ctx; |
mmu_secondary_context_write(as->asid); |
/* |
* Note that we don't and may not lock the address space. That's ok |
* since we only read members that are currently read-only. |
* |
* Moreover, the as->asid is protected by asidlock, which is being held. |
*/ |
/* |
* Write ASID to secondary context register. The primary context |
* register has to be set from TL>0 so it will be filled from the |
* secondary context register from the TL=1 code just before switch to |
* userspace. |
*/ |
ctx.v = 0; |
ctx.context = as->asid; |
mmu_secondary_context_write(ctx.v); |
#ifdef CONFIG_TSB |
uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
ASSERT(as->arch.itsb && as->arch.dtsb); |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
uintptr_t tsb = (uintptr_t) as->arch.itsb; |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
* TSBs were allocated from memory not covered |
151,43 → 129,15 |
* by the locked 4M kernel DTLB entry. We need |
* to map both TSBs explicitly. |
*/ |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); |
mmu_map_perm_addr( |
tsb, KA2PA(tsb), true, true, false, true, |
PAGESIZE_64K, MMU_FLAG_DTLB); |
} |
/* |
* Setup TSB Base registers. |
*/ |
tsb_base_reg_t tsb_base; |
__hypercall_fast2(MMU_TSB_CTX0, 1, as->arch.tsb_description.tsb_base); |
tsb_base.value = 0; |
tsb_base.size = TSB_SIZE; |
tsb_base.split = 0; |
tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
itsb_base_write(tsb_base.value); |
tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
dtsb_base_write(tsb_base.value); |
#if defined (US3) |
/* |
* Clear the extension registers. |
* In HelenOS, primary and secondary context registers contain |
* equal values and kernel misses (context 0, ie. the nucleus context) |
* are excluded from the TSB miss handler, so it makes no sense |
* to have separate TSBs for primary, secondary and nucleus contexts. |
* Clearing the extension registers will ensure that the value of the |
* TSB Base register will be used as an address of TSB, making the code |
* compatible with the US port. |
*/ |
itsb_primary_extension_write(0); |
itsb_nucleus_extension_write(0); |
dtsb_primary_extension_write(0); |
dtsb_secondary_extension_write(0); |
dtsb_nucleus_extension_write(0); |
#endif |
#endif |
#endif |
} |
/** Perform sparc64-specific tasks when an address space is removed from the |
199,7 → 149,6 |
*/ |
void as_deinstall_arch(as_t *as) |
{ |
/* |
* Note that we don't and may not lock the address space. That's ok |
* since we only read members that are currently read-only. |
206,13 → 155,12 |
* |
* Moreover, the as->asid is protected by asidlock, which is being held. |
*/ |
#ifdef CONFIG_TSB |
uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
ASSERT(as->arch.itsb && as->arch.dtsb); |
ASSERT(as->arch.tsb_description.tsb_base); |
uintptr_t tsb = (uintptr_t) as->arch.itsb; |
uintptr_t tsb = as->arch.tsb_description.tsb_base; |
if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
/* |
220,7 → 168,7 |
* by the locked 4M kernel DTLB entry. We need |
* to demap the entry installed by as_install_arch(). |
*/ |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); |
} |
#endif |
} |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tsb.c |
---|
0,0 → 1,181 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* Copyright (c) 2009 Pavel Rimsky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/mm/tsb.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/page.h> |
#include <arch/barrier.h> |
#include <mm/as.h> |
#include <arch/types.h> |
#include <macros.h> |
#include <debug.h> |
#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1) |
/** Invalidate portion of TSB. |
* |
* We assume that the address space is already locked. Note that respective |
* portions of both TSBs are invalidated at a time. |
* |
* @param as Address space. |
* @param page First page to invalidate in TSB. |
* @param pages Number of pages to invalidate. Value of (count_t) -1 means the |
* whole TSB. |
*/ |
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
{ |
index_t i0, i; |
count_t cnt; |
ASSERT(as->arch.tsb_description.tsb_base); |
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(i0 < TSB_ENTRY_COUNT); |
if (pages == (count_t) - 1 || (pages) > TSB_ENTRY_COUNT) |
cnt = TSB_ENTRY_COUNT; |
else |
cnt = pages; |
for (i = 0; i < cnt; i++) { |
((tsb_entry_t *) as->arch.tsb_description.tsb_base)[ |
(i0 + i) & (TSB_ENTRY_COUNT - 1)].tag.invalid = true; |
} |
} |
/** Copy software PTE to ITSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K subpage. |
*/ |
void itsb_pte_copy(pte_t *t, index_t index) |
{ |
#if 0 |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < ITSB_ENTRY_COUNT); |
tsb = &as->arch.itsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ |
tsb->data.p = t->k; /* p as privileged, k as kernel */ |
tsb->data.v = t->p; /* v as valid, p as present */ |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
#endif |
} |
/** Copy software PTE to DTSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
* @param ro If true, the mapping is copied read-only. |
*/ |
void dtsb_pte_copy(pte_t *t, index_t index, bool ro) |
{ |
#if 0 |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < DTSB_ENTRY_COUNT); |
tsb = &as->arch.dtsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_DCACHE |
tsb->data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_DCACHE */ |
tsb->data.p = t->k; /* p as privileged */ |
tsb->data.w = ro ? false : t->w; |
tsb->data.v = t->p; |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
#endif |
} |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/src/mm/page.c |
---|
34,8 → 34,7 |
#include <arch/mm/page.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <genarch/mm/page_ht.h> |
#include <mm/frame.h> |
#include <arch/mm/frame.h> |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4u/tlb.c |
---|
32,8 → 32,7 |
/** @file |
*/ |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <mm/asid.h> |
40,7 → 39,7 |
#include <arch/mm/frame.h> |
#include <arch/mm/page.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/sun4u/mmu.h> |
#include <arch/mm/mmu.h> |
#include <arch/interrupt.h> |
#include <interrupt.h> |
#include <arch.h> |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4u/as.c |
---|
34,8 → 34,7 |
#include <arch/mm/as.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/sun4u/tlb.h> |
#include <arch/mm/tlb.h> |
#include <genarch/mm/page_ht.h> |
#include <genarch/mm/asid_fifo.h> |
#include <debug.h> |
/branches/sparc/kernel/arch/sparc64/src/mm/sun4u/tsb.c |
---|
0,0 → 1,177 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/mm/tsb.h> |
#include <arch/mm/pagesize.h> |
#include <arch/mm/tlb.h> |
#include <arch/mm/page.h> |
#include <arch/barrier.h> |
#include <mm/as.h> |
#include <arch/types.h> |
#include <macros.h> |
#include <debug.h> |
#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1) |
/** Invalidate portion of TSB. |
* |
* We assume that the address space is already locked. Note that respective |
* portions of both TSBs are invalidated at a time. |
* |
* @param as Address space. |
* @param page First page to invalidate in TSB. |
* @param pages Number of pages to invalidate. Value of (count_t) -1 means the |
* whole TSB. |
*/ |
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
{ |
index_t i0, i; |
count_t cnt; |
ASSERT(as->arch.itsb && as->arch.dtsb); |
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); |
if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) |
cnt = ITSB_ENTRY_COUNT; |
else |
cnt = pages * 2; |
for (i = 0; i < cnt; i++) { |
as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid = |
true; |
as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid = |
true; |
} |
} |
/** Copy software PTE to ITSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K subpage. |
*/ |
void itsb_pte_copy(pte_t *t, index_t index) |
{ |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < ITSB_ENTRY_COUNT); |
tsb = &as->arch.itsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ |
tsb->data.p = t->k; /* p as privileged, k as kernel */ |
tsb->data.v = t->p; /* v as valid, p as present */ |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
} |
/** Copy software PTE to DTSB. |
* |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
* @param ro If true, the mapping is copied read-only. |
*/ |
void dtsb_pte_copy(pte_t *t, index_t index, bool ro) |
{ |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < DTSB_ENTRY_COUNT); |
tsb = &as->arch.dtsb[entry]; |
/* |
* We use write barriers to make sure that the TSB load |
* won't use inconsistent data or that the fault will |
* be repeated. |
*/ |
tsb->tag.invalid = true; /* invalidate the entry |
* (tag target has this |
* set to 0) */ |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
tsb->data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_DCACHE |
tsb->data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_DCACHE */ |
tsb->data.p = t->k; /* p as privileged */ |
tsb->data.w = ro ? false : t->w; |
tsb->data.v = t->p; |
write_barrier(); |
tsb->tag.invalid = false; /* mark the entry as valid */ |
} |
/** @} |
*/ |
/branches/sparc/kernel/arch/sparc64/src/drivers/sgcn.c |
---|
34,6 → 34,7 |
* @brief SGCN driver. |
*/ |
#include <arch/asm.h> |
#include <arch/drivers/sgcn.h> |
#include <arch/drivers/kbd.h> |
#include <genarch/ofw/ofw_tree.h> |