/branches/sparc/kernel/arch/sparc64/include/regdef.h |
---|
59,8 → 59,8 |
* The following definitions concern the UPA_CONFIG register on US and the |
* FIREPLANE_CONFIG register on US3. |
*/ |
#define UPA_CONFIG_MID_SHIFT 17 |
#define UPA_CONFIG_MID_MASK 0x1f |
#define ICBUS_CONFIG_MID_SHIFT 17 |
#define ICBUS_CONFIG_MID_MASK 0x1f |
#endif |
/branches/sparc/kernel/arch/sparc64/include/arch.h |
---|
41,7 → 41,7 |
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ |
#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ |
#define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
#define NWINDOWS 8 /** Number of register window sets. */ |
/branches/sparc/kernel/arch/sparc64/include/asm.h |
---|
364,9 → 364,9 |
* Value of the UPA_CONFIG register in US, |
* value of the FIREPLANE_CONFIG on US3. |
*/ |
static inline uint64_t upa_config_read(void) |
static inline uint64_t icbus_config_read(void) |
{ |
return asi_u64_read(ASI_UPA_CONFIG, 0); |
return asi_u64_read(ASI_ICBUS_CONFIG, 0); |
} |
extern void cpu_halt(void); |
/branches/sparc/kernel/arch/sparc64/include/register.h |
---|
123,7 → 123,7 |
* processor version to version. The format defined here |
* is the common subset for all supported processor versions. |
*/ |
union upa_config { |
union icbus_config { |
uint64_t value; |
struct { |
uint64_t : 34; |
132,7 → 132,7 |
unsigned pcap : 17; /**< Processor capabilities. */ |
} __attribute__ ((packed)); |
}; |
typedef union upa_config upa_config_t; |
typedef union icbus_config icbus_config_t; |
#endif |
/branches/sparc/kernel/arch/sparc64/include/cpu.h |
---|
52,7 → 52,10 |
#define IMPL_ULTRASPARCII 0x11 |
#define IMPL_ULTRASPARCII_I 0x12 |
#define IMPL_ULTRASPARCII_E 0x13 |
#define IMPL_ULTRASPARCIII 0x15 |
#define IMPL_ULTRASPARCIII 0x14 |
#define IMPL_ULTRASPARCIII_PLUS 0x15 |
#define IMPL_ULTRASPARCIII_I 0x16 |
#define IMPL_ULTRASPARCIV 0x18 |
#define IMPL_ULTRASPARCIV_PLUS 0x19 |
#define IMPL_SPARC64V 0x5 |
/branches/sparc/kernel/arch/sparc64/src/cpu/cpu.c |
---|
47,10 → 47,10 |
ofw_tree_node_t *node; |
uint32_t mid; |
uint32_t clock_frequency = 0; |
upa_config_t upa_config; |
icbus_config_t icbus_config; |
upa_config.value = upa_config_read(); |
CPU->arch.mid = upa_config.mid; |
icbus_config.value = icbus_config_read(); |
CPU->arch.mid = icbus_config.mid; |
/* |
* Detect processor frequency. |
/branches/sparc/kernel/arch/sparc64/src/start.S |
---|
301,9 → 301,9 |
* Read MID from the processor. |
*/ |
1: |
ldxa [%g0] ASI_UPA_CONFIG, %g1 |
srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
and %g1, UPA_CONFIG_MID_MASK, %g1 |
ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
and %g1, ICBUS_CONFIG_MID_MASK, %g1 |
#ifdef CONFIG_SMP |
/* |
/branches/sparc/boot/boot.config |
---|
83,7 → 83,5 |
@ "fat" FAT16 image |
! RDFMT (choice) |
# OpenFirmware implementation |
@ "open_boot" OpenBoot (Sun Microsystems) |
@ "smart_firmware" SmartFirmware (CodeGen) |
! [ARCH=sparc64] OFW_IMPLEMENTATION (choice) |
# Preserve A.OUT header in isofs.b |
! [ARCH=sparc64] CONFIG_AOUT_ISOFS_B (y/n) |
/branches/sparc/boot/genarch/balloc.h |
---|
40,11 → 40,7 |
* machines so that it can fit into 128 kB. This is a workaround how |
* to get rid of the memory claiming failure. |
*/ |
#if defined (SMART_FIRMWARE) |
#define BALLOC_MAX_SIZE (128 * 1024) |
#else |
#define BALLOC_MAX_SIZE (1024 * 1024) |
#endif |
typedef struct { |
uintptr_t base; |
/branches/sparc/boot/genarch/ofw_tree.c |
---|
219,21 → 219,20 |
ofw_tree_node_t *ofw_tree_build(void) |
{ |
ofw_tree_node_t *root; |
#if defined (SMART_FIRMWARE) |
phandle ssm_node; |
ofw_tree_node_t *ssm; |
#endif |
root = ofw_tree_node_alloc(); |
if (root) |
ofw_tree_node_process(root, NULL, ofw_root); |
#if defined (SMART_FIRMWARE) |
/* |
* The firmware client interface does not automatically include the |
* "ssm" node in the list of children of "/". A nasty yet working |
* solution is to explicitly stick "ssm" to the OFW tree. |
*/ |
ssm_node = ofw_find_device("/ssm@0,0"); |
if (ssm_node != -1) { |
ssm = ofw_tree_node_alloc(); |
if (ssm) { |
ofw_tree_node_process(ssm, root, ofw_find_device("/ssm@0,0")); |
240,7 → 239,7 |
ssm->peer = root->child; |
root->child = ssm; |
} |
#endif |
} |
return root; |
} |
/branches/sparc/boot/arch/sparc64/Makefile.inc |
---|
28,13 → 28,11 |
TMP=distroot |
ifeq ($(OFW_IMPLEMENTATION),smart_firmware) |
DEFS += -DSMART_FIRMWARE |
ifeq ($(CONFIG_AOUT_ISOFS_B),n) |
SILO_PACKAGE=silo.patched.tar.gz |
endif |
ifeq ($(OFW_IMPLEMENTATION),open_boot) |
DEFS += -DOPEN_BOOT |
ifeq ($(CONFIG_AOUT_ISOFS_B),y) |
SILO_PACKAGE=silo.tar.gz |
endif |
/branches/sparc/boot/arch/sparc64/loader/asm.S |
---|
108,15 → 108,36 |
*/ |
/* |
* US-III processors have a write-invalidate cache, so flushing it is |
* not required. We only use the FLUSH instruction to flush the |
* pipeline. |
* US3 processors have a write-invalidate cache, so explicitly |
* invalidating it is not required. Whether to invalidate I-cache |
* or not is decided according to the value of the ver.impl bits |
* in the Version register. |
*/ |
#ifdef US |
sethi 0x40000, %g0 |
! the lowest/greatest value of ver.impl for US3 |
#define FIRST_US3_CPU 0x14 |
#define LAST_US3_CPU 0x19 |
rdpr %ver, %g2 ! autodetect CPU using the Version register |
sllx %g2, 16, %g2 ! extract ver.impl bits |
srlx %g2, 48, %g2 |
addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU |
bl 0f |
nop |
addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU |
bg 0f |
nop |
ba 1f |
nop |
0: |
call icache_flush |
#endif |
nop |
1: |
membar #StoreStore |
/* |
* Flush the instruction pipeline. |
*/ |
flush %i7 |
mov %o0, %l1 |
143,7 → 164,6 |
retl |
! SF Erratum #51 |
nop |
.global ofw |
ofw: |
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
/branches/sparc/boot/arch/sparc64/loader/ofwarch.c |
---|
56,23 → 56,19 |
return flag != -1; |
} |
/* |
* Node among whose children the CPU nodes are located. |
*/ |
#if defined (OPEN_BOOT) |
#define CPUS_PARENT_NODE ofw_root |
#elif defined (SMART_FIRMWARE) |
#define CPUS_PARENT_NODE ofw_find_device("/ssm@0,0") |
#endif |
int ofw_cpu(void) |
{ |
char type_name[BUF_SIZE]; |
phandle node; |
node = ofw_get_child_node(CPUS_PARENT_NODE); |
phandle ssm; |
ssm = ofw_find_device("/ssm@0,0"); |
if (ssm == -1) { |
node = ofw_get_child_node(ofw_root); |
} else { |
node = ofw_get_child_node(ssm); |
} |
if (node == 0 || node == -1) { |
printf("Could not find any child nodes of the root node.\n"); |
return 0; |
82,9 → 78,9 |
asm volatile ("ldxa [%1] %2, %0\n" |
: "=r" (current_mid) |
: "r" (0), "i" (ASI_UPA_CONFIG)); |
current_mid >>= UPA_CONFIG_MID_SHIFT; |
current_mid &= UPA_CONFIG_MID_MASK; |
: "r" (0), "i" (ASI_ICBUS_CONFIG)); |
current_mid >>= ICBUS_CONFIG_MID_SHIFT; |
current_mid &= ICBUS_CONFIG_MID_MASK; |
int cpus; |
/branches/sparc/boot/arch/sparc64/loader/register.h |
---|
33,8 → 33,8 |
#define PSTATE_PRIV_BIT 4 |
#define PSTATE_AM_BIT 8 |
#define ASI_UPA_CONFIG 0x4a |
#define UPA_CONFIG_MID_SHIFT 17 |
#define UPA_CONFIG_MID_MASK 0x1f |
#define ASI_ICBUS_CONFIG 0x4a |
#define ICBUS_CONFIG_MID_SHIFT 17 |
#define ICBUS_CONFIG_MID_MASK 0x1f |
#endif |
/branches/sparc/boot/arch/ppc32/Makefile.inc |
---|
26,8 → 26,6 |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
DEFS += -DSMART_FIRMWARE |
build: $(BASE)/image.boot |
$(BASE)/image.boot: depend arch/$(ARCH)/loader/image.boot |