/branches/rcu/kernel/arch/sparc64/src/mm/cache.S |
---|
45,10 → 45,8 |
subcc %g1, DCACHE_LINE_SIZE, %g1 |
bnz,pt %xcc, 0b |
stxa %g0, [%g1] ASI_DCACHE_TAG |
membar #Sync |
retl |
! beware SF Erratum #51, do not put the MEMBAR here |
nop |
membar #Sync |
/** Flush only D-cache lines of one virtual color. |
* |
/branches/rcu/kernel/arch/sparc64/src/mm/tlb.c |
---|
198,7 → 198,7 |
} |
/** ITLB miss handler. */ |
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
{ |
uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
234,18 → 234,15 |
* |
* Note that some faults (e.g. kernel faults) were already resolved by the |
* low-level, assembly language part of the fast_data_access_mmu_miss handler. |
* |
* @param tag Content of the TLB Tag Access register as it existed when the |
* trap happened. This is to prevent confusion created by clobbered |
* Tag Access register during a nested DTLB miss. |
* @param istate Interrupted state saved on the stack. |
*/ |
void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
void fast_data_access_mmu_miss(int n, istate_t *istate) |
{ |
tlb_tag_access_reg_t tag; |
uintptr_t va; |
index_t index; |
pte_t *t; |
tag.value = dtlb_tag_access_read(); |
va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
index = tag.vpn % MMU_PAGES_PER_PAGE; |
285,19 → 282,15 |
} |
} |
/** DTLB protection fault handler. |
* |
* @param tag Content of the TLB Tag Access register as it existed when the |
* trap happened. This is to prevent confusion created by clobbered |
* Tag Access register during a nested DTLB miss. |
* @param istate Interrupted state saved on the stack. |
*/ |
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
/** DTLB protection fault handler. */ |
void fast_data_access_protection(int n, istate_t *istate) |
{ |
tlb_tag_access_reg_t tag; |
uintptr_t va; |
index_t index; |
pte_t *t; |
tag.value = dtlb_tag_access_read(); |
va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
378,10 → 371,9 |
uintptr_t va; |
va = tag.vpn << MMU_PAGE_WIDTH; |
if (tag.context) { |
fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
tag.context); |
} |
fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
tag.context); |
dump_istate(istate); |
printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
panic("%s\n", str); |
394,10 → 386,8 |
va = tag.vpn << MMU_PAGE_WIDTH; |
if (tag.context) { |
fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
tag.context); |
} |
fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
tag.context); |
printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
dump_istate(istate); |
panic("%s\n", str); |
/branches/rcu/kernel/arch/sparc64/src/mm/as.c |
---|
66,7 → 66,6 |
*/ |
int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
if (!tsb) |
75,7 → 74,6 |
as->arch.itsb = (tsb_entry_t *) tsb; |
as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
sizeof(tsb_entry_t)); |
memsetb((uintptr_t) as->arch.itsb, |
(ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
#endif |
/branches/rcu/kernel/arch/sparc64/src/mm/tsb.c |
---|
61,8 → 61,6 |
ASSERT(as->arch.itsb && as->arch.dtsb); |
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); |
if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) |
cnt = ITSB_ENTRY_COUNT; |
else |
86,12 → 84,9 |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < ITSB_ENTRY_COUNT); |
tsb = &as->arch.itsb[entry]; |
/* |
107,8 → 102,8 |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >> |
VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
133,11 → 128,8 |
tsb_entry_t *tsb; |
index_t entry; |
ASSERT(index <= 1); |
as = t->as; |
entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
ASSERT(entry < DTSB_ENTRY_COUNT); |
tsb = &as->arch.dtsb[entry]; |
/* |
153,8 → 145,8 |
write_barrier(); |
tsb->tag.context = as->asid; |
/* the shift is bigger than PAGE_WIDTH, do not bother with index */ |
tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >> |
VA_TAG_PAGE_SHIFT; |
tsb->data.value = 0; |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
/branches/rcu/kernel/arch/sparc64/src/mm/frame.c |
---|
65,10 → 65,10 |
if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0)))) |
confdata = ADDR2PFN(KA2PA(PFN2ADDR(2))); |
zone_create(ADDR2PFN(start), |
SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), |
confdata, 0); |
SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), |
confdata, 0); |
last_frame = max(last_frame, start + ALIGN_UP(size, |
FRAME_SIZE)); |
FRAME_SIZE)); |
} |
/* |