/branches/rcu/kernel/test/tasklet/tasklet1.c |
---|
30,7 → 30,7 |
#include <print.h> |
#include <test.h> |
#include <ddi/tasklet.h> |
#include <proc/tasklet.h> |
#include <synch/waitq.h> |
#include <arch/types.h> |
/branches/rcu/kernel/generic/include/synch/rcu.h |
---|
36,7 → 36,7 |
#define KERN_RCU_H_ |
#include <arch/types.h> |
#include <ddi/tasklet.h> |
#include <proc/tasklet.h> |
#include <arch/barrier.h> |
#include <preemption.h> |
/branches/rcu/kernel/generic/include/ddi/tasklet.h |
---|
File deleted |
/branches/rcu/kernel/generic/include/ddi/irq.h |
---|
1,154 → 1,162 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup genericddi |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_IRQ_H_ |
#define KERN_IRQ_H_ |
typedef enum { |
CMD_MEM_READ_1 = 0, |
CMD_MEM_READ_2, |
CMD_MEM_READ_4, |
CMD_MEM_READ_8, |
CMD_MEM_WRITE_1, |
CMD_MEM_WRITE_2, |
CMD_MEM_WRITE_4, |
CMD_MEM_WRITE_8, |
CMD_PORT_READ_1, |
CMD_PORT_WRITE_1, |
CMD_IA64_GETCHAR, |
CMD_PPC32_GETCHAR, |
CMD_LAST |
} irq_cmd_type; |
typedef struct { |
irq_cmd_type cmd; |
void *addr; |
unsigned long long value; |
int dstarg; |
} irq_cmd_t; |
typedef struct { |
unsigned int cmdcount; |
irq_cmd_t *cmds; |
} irq_code_t; |
#ifdef KERNEL |
#include <arch/types.h> |
#include <adt/list.h> |
#include <synch/spinlock.h> |
#include <proc/task.h> |
typedef enum { |
IRQ_DECLINE, /**< Decline to service. */ |
IRQ_ACCEPT /**< Accept to service. */ |
} irq_ownership_t; |
typedef enum { |
IRQ_TRIGGER_LEVEL = 1, |
IRQ_TRIGGER_EDGE |
} irq_trigger_t; |
struct irq; |
typedef void (* irq_handler_t)(struct irq *irq, void *arg, ...); |
/** IPC notification config structure. |
* |
* Primarily, this structure is encapsulated in the irq_t structure. |
* It is protected by irq_t::lock. |
*/ |
typedef struct { |
/** When false, notifications are not sent. */ |
bool notify; |
/** Answerbox for notifications. */ |
answerbox_t *answerbox; |
/** Method to be used for the notification. */ |
unative_t method; |
/** Top-half pseudocode. */ |
irq_code_t *code; |
/** Counter. */ |
count_t counter; |
/** |
* Link between IRQs that are notifying the same answerbox. The list is |
* protected by the answerbox irq_lock. |
*/ |
link_t link; |
} ipc_notif_cfg_t; |
/** Structure representing one device IRQ. |
* |
* If one device has multiple interrupts, there will be multiple irq_t |
* instantions with the same devno. |
*/ |
typedef struct irq { |
/** Hash table link. */ |
link_t link; |
/** Lock protecting everything in this structure |
* except the link member. When both the IRQ |
* hash table lock and this lock are to be acquired, |
* this lock must not be taken first. |
*/ |
SPINLOCK_DECLARE(lock); |
/** Unique device number. -1 if not yet assigned. */ |
devno_t devno; |
/** Actual IRQ number. -1 if not yet assigned. */ |
inr_t inr; |
/** Trigger level of the IRQ.*/ |
irq_trigger_t trigger; |
/** Claim ownership of the IRQ. */ |
irq_ownership_t (* claim)(void); |
/** Handler for this IRQ and device. */ |
irq_handler_t handler; |
/** Argument for the handler. */ |
void *arg; |
/** Notification configuration structure. */ |
ipc_notif_cfg_t notif_cfg; |
} irq_t; |
extern void irq_init(count_t inrs, count_t chains); |
extern void irq_initialize(irq_t *irq); |
extern void irq_register(irq_t *irq); |
extern irq_t *irq_dispatch_and_lock(inr_t inr); |
extern irq_t *irq_find_and_lock(inr_t inr, devno_t devno); |
#endif |
#endif |
/** @} |
*/ |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup genericddi |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_IRQ_H_ |
#define KERN_IRQ_H_ |
typedef enum { |
CMD_MEM_READ_1 = 0, |
CMD_MEM_READ_2, |
CMD_MEM_READ_4, |
CMD_MEM_READ_8, |
CMD_MEM_WRITE_1, |
CMD_MEM_WRITE_2, |
CMD_MEM_WRITE_4, |
CMD_MEM_WRITE_8, |
CMD_PORT_READ_1, |
CMD_PORT_WRITE_1, |
CMD_IA64_GETCHAR, |
CMD_PPC32_GETCHAR, |
CMD_LAST |
} irq_cmd_type; |
typedef struct { |
irq_cmd_type cmd; |
void *addr; |
unsigned long long value; |
int dstarg; |
} irq_cmd_t; |
typedef struct { |
unsigned int cmdcount; |
irq_cmd_t *cmds; |
} irq_code_t; |
#ifdef KERNEL |
#include <arch/types.h> |
#include <adt/list.h> |
#include <synch/spinlock.h> |
#include <proc/task.h> |
typedef enum { |
IRQ_DECLINE, /**< Decline to service. */ |
IRQ_ACCEPT /**< Accept to service. */ |
} irq_ownership_t; |
typedef enum { |
IRQ_TRIGGER_LEVEL = 1, |
IRQ_TRIGGER_EDGE |
} irq_trigger_t; |
struct irq; |
typedef void (* irq_handler_t)(struct irq *irq, void *arg, ...); |
/** IPC notification config structure. |
* |
* Primarily, this structure is encapsulated in the irq_t structure. |
* It is protected by irq_t::lock. |
*/ |
typedef struct { |
/** When false, notifications are not sent. */ |
bool notify; |
/** Answerbox for notifications. */ |
answerbox_t *answerbox; |
/** Method to be used for the notification. */ |
unative_t method; |
/** Top-half pseudocode. */ |
irq_code_t *code; |
/** Counter. */ |
count_t counter; |
/** |
* Link between IRQs that are notifying the same answerbox. The list is |
* protected by the answerbox irq_lock. |
*/ |
link_t link; |
} ipc_notif_cfg_t; |
/** Structure representing one device IRQ. |
* |
* If one device has multiple interrupts, there will be multiple irq_t |
* instantions with the same devno. |
*/ |
typedef struct irq { |
/** Hash table link. */ |
link_t link; |
/** Lock protecting everything in this structure |
* except the link member. When both the IRQ |
* hash table lock and this lock are to be acquired, |
* this lock must not be taken first. |
*/ |
SPINLOCK_DECLARE(lock); |
/** Send EOI before processing the interrupt. |
* This is essential for timer interrupt which |
* has to be acknowledged before doing preemption |
* to make sure another timer interrupt will |
* be eventually generated. |
*/ |
bool preack; |
/** Unique device number. -1 if not yet assigned. */ |
devno_t devno; |
/** Actual IRQ number. -1 if not yet assigned. */ |
inr_t inr; |
/** Trigger level of the IRQ. */ |
irq_trigger_t trigger; |
/** Claim ownership of the IRQ. */ |
irq_ownership_t (* claim)(void); |
/** Handler for this IRQ and device. */ |
irq_handler_t handler; |
/** Argument for the handler. */ |
void *arg; |
/** Notification configuration structure. */ |
ipc_notif_cfg_t notif_cfg; |
} irq_t; |
extern void irq_init(count_t inrs, count_t chains); |
extern void irq_initialize(irq_t *irq); |
extern void irq_register(irq_t *irq); |
extern irq_t *irq_dispatch_and_lock(inr_t inr); |
extern irq_t *irq_find_and_lock(inr_t inr, devno_t devno); |
#endif |
#endif |
/** @} |
*/ |
/branches/rcu/kernel/generic/src/synch/rcu.c |
---|
37,47 → 37,42 |
#include <arch.h> |
#include <config.h> |
#include <arch/types.h> |
#include <ddi/tasklet.h> |
#include <proc/tasklet.h> |
#include <synch/spinlock.h> |
#include <time/delay.h> |
#include <panic.h> |
#include <print.h> |
typedef struct rcu_global |
{ |
typedef struct { |
uint32_t current_batch; |
uint32_t completed_batch; |
bool next_batch_waiting; |
} rcu_global_t; |
typedef struct rcu_callback_list |
{ |
struct rcu_callback_list* next; |
void (*func)(void*); |
void* data; |
bool* cpu_mask; |
typedef struct rcu_callback_list { |
struct rcu_callback_list* next; |
void (*func)(void*); |
void* data; |
bool* cpu_mask; |
} rcu_callback_list_t; |
typedef struct rcu_percpu |
{ |
typedef struct { |
uint32_t current_batch_number; |
uint32_t QS_passed; |
bool QS_pending; |
rcu_callback_list_t* next_batch, *current_batch, *done_batch; |
rcu_callback_list_t* next_batch, *current_batch, *done_batch; |
} rcu_percpu_t; |
rcu_global_t _rcu_global; |
rcu_percpu_t* _rcu_cpu_lists; |
void rcu_init(void) |
void rcu_init(void) |
{ |
_rcu_cpu_lists = malloc(sizeof(rcu_percpu_t)*config.cpu_count,0); |
_rcu_global.completed_batch = -1; |
_rcu_global.current_batch = -1; |
_rcu_global.next_batch_waiting = -1; |
} |
void rcu_synchronize(void) |
97,7 → 92,7 |
{ |
int i; |
rcu_callback_list_t *rd; |
rd = malloc(sizeof(rcu_desc), 0); |
rd = malloc(sizeof(rcu_callback_list_t), 0); |
rd->func = func; |
rd->data = data; |
rd->next = NULL; |
110,11 → 105,9 |
_rcu_global.next_batch_waiting = true; |
rd->next = _rcu_cpu_lists[0].next_batch; |
for (i=0;i<config.cpu_count;i++) |
{ |
for (i=0;i<config.cpu_count;i++) { |
_rcu_cpu_lists[i].next_batch = rd; |
_rcu_cpu_lists[i].QS_pending = true; |
} |
//TODO:tasklet, after_thread_ran, polishing |
/branches/rcu/kernel/generic/src/main/main.c |
---|
81,7 → 81,7 |
#include <console/klog.h> |
#include <smp/smp.h> |
#include <ddi/ddi.h> |
#include <ddi/tasklet.h> |
#include <proc/tasklet.h> |
/** Global configuration structure. */ |
config_t config; |
220,7 → 220,6 |
tlb_init(); |
ddi_init(); |
tasklet_init(); |
// tasklet_do(); |
arch_post_mm_init(); |
version_print(); |
242,7 → 241,6 |
calibrate_delay_loop(); |
clock_counter_init(); |
// tasklet_do(); |
timeout_init(); |
scheduler_init(); |
task_init(); |
259,9 → 257,7 |
init.tasks[i].size); |
} else |
printf("No init binaries found\n"); |
ipc_init(); |
//tasklet_do(); |
/* |
* Create kernel task. |
278,7 → 274,8 |
panic("can't create kinit thread\n"); |
thread_ready(t); |
tasklet_run_tasklet_thread(k); |
//tasklets disabled for debugging purposes |
//tasklet_run_tasklet_thread(k); |
/* |
* This call to scheduler() will return to kinit, |
/branches/rcu/kernel/generic/src/ddi/tasklet.c |
---|
File deleted |
/branches/rcu/kernel/generic/src/ddi/irq.c |
---|
1,379 → 1,380 |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup genericddi |
* @{ |
*/ |
/** |
* @file |
* @brief IRQ dispatcher. |
* |
* This file provides means of connecting IRQs with particular |
* devices and logic for dispatching interrupts to IRQ handlers |
* defined by those devices. |
* |
* This code is designed to support: |
* - multiple devices sharing single IRQ |
* - multiple IRQs per signle device |
* |
* |
* Note about architectures. |
* |
* Some architectures has the term IRQ well defined. Examples |
* of such architectures include amd64, ia32 and mips32. Some |
* other architectures, such as sparc64, don't use the term |
* at all. In those cases, we boldly step forward and define what |
* an IRQ is. |
* |
* The implementation is generic enough and still allows the |
* architectures to use the hardware layout effectively. |
* For instance, on amd64 and ia32, where there is only 16 |
* IRQs, the irq_hash_table can be optimized to a one-dimensional |
* array. Next, when it is known that the IRQ numbers (aka INR's) |
* are unique, the claim functions can always return IRQ_ACCEPT. |
* |
* |
* Note about the irq_hash_table. |
* |
* The hash table is configured to use two keys: inr and devno. |
* However, the hash index is computed only from inr. Moreover, |
* if devno is -1, the match is based on the return value of |
* the claim() function instead of on devno. |
*/ |
#include <ddi/irq.h> |
#include <adt/hash_table.h> |
#include <arch/types.h> |
#include <synch/spinlock.h> |
#include <arch.h> |
#define KEY_INR 0 |
#define KEY_DEVNO 1 |
/** |
* Spinlock protecting the hash table. |
* This lock must be taken only when interrupts are disabled. |
*/ |
SPINLOCK_INITIALIZE(irq_hash_table_lock); |
static hash_table_t irq_hash_table; |
/** |
* Hash table operations for cases when we know that |
* there will be collisions between different keys. |
*/ |
static index_t irq_ht_hash(unative_t *key); |
static bool irq_ht_compare(unative_t *key, count_t keys, link_t *item); |
static hash_table_operations_t irq_ht_ops = { |
.hash = irq_ht_hash, |
.compare = irq_ht_compare, |
.remove_callback = NULL /* not used */ |
}; |
/** |
* Hash table operations for cases when we know that |
* there will be no collisions between different keys. |
* However, there might be still collisions among |
* elements with single key (sharing of one IRQ). |
*/ |
static index_t irq_lin_hash(unative_t *key); |
static bool irq_lin_compare(unative_t *key, count_t keys, link_t *item); |
static hash_table_operations_t irq_lin_ops = { |
.hash = irq_lin_hash, |
.compare = irq_lin_compare, |
.remove_callback = NULL /* not used */ |
}; |
/** Initialize IRQ subsystem. |
* |
* @param inrs Numbers of unique IRQ numbers or INRs. |
* @param chains Number of chains in the hash table. |
*/ |
void irq_init(count_t inrs, count_t chains) |
{ |
/* |
* Be smart about the choice of the hash table operations. |
* In cases in which inrs equals the requested number of |
* chains (i.e. where there is no collision between |
* different keys), we can use optimized set of operations. |
*/ |
if (inrs == chains) |
hash_table_create(&irq_hash_table, chains, 2, &irq_lin_ops); |
else |
hash_table_create(&irq_hash_table, chains, 2, &irq_ht_ops); |
} |
/** Initialize one IRQ structure. |
* |
* @param irq Pointer to the IRQ structure to be initialized. |
* |
*/ |
void irq_initialize(irq_t *irq) |
{ |
link_initialize(&irq->link); |
spinlock_initialize(&irq->lock, "irq.lock"); |
irq->inr = -1; |
irq->devno = -1; |
irq->trigger = (irq_trigger_t) 0; |
irq->claim = NULL; |
irq->handler = NULL; |
irq->arg = NULL; |
irq->notif_cfg.notify = false; |
irq->notif_cfg.answerbox = NULL; |
irq->notif_cfg.code = NULL; |
irq->notif_cfg.method = 0; |
irq->notif_cfg.counter = 0; |
link_initialize(&irq->notif_cfg.link); |
} |
/** Register IRQ for device. |
* |
* The irq structure must be filled with information |
* about the interrupt source and with the claim() |
* function pointer and irq_handler() function pointer. |
* |
* @param irq IRQ structure belonging to a device. |
*/ |
void irq_register(irq_t *irq) |
{ |
ipl_t ipl; |
unative_t key[] = { |
(unative_t) irq->inr, |
(unative_t) irq->devno |
}; |
ipl = interrupts_disable(); |
spinlock_lock(&irq_hash_table_lock); |
hash_table_insert(&irq_hash_table, key, &irq->link); |
spinlock_unlock(&irq_hash_table_lock); |
interrupts_restore(ipl); |
} |
/** Dispatch the IRQ. |
* |
* We assume this function is only called from interrupt |
* context (i.e. that interrupts are disabled prior to |
* this call). |
* |
* This function attempts to lookup a fitting IRQ |
* structure. In case of success, return with interrupts |
* disabled and holding the respective structure. |
* |
* @param inr Interrupt number (aka inr or irq). |
* |
* @return IRQ structure of the respective device or NULL. |
*/ |
irq_t *irq_dispatch_and_lock(inr_t inr) |
{ |
link_t *lnk; |
unative_t key[] = { |
(unative_t) inr, |
(unative_t) -1 /* search will use claim() instead of devno */ |
}; |
spinlock_lock(&irq_hash_table_lock); |
lnk = hash_table_find(&irq_hash_table, key); |
if (lnk) { |
irq_t *irq; |
irq = hash_table_get_instance(lnk, irq_t, link); |
spinlock_unlock(&irq_hash_table_lock); |
return irq; |
} |
spinlock_unlock(&irq_hash_table_lock); |
return NULL; |
} |
/** Find the IRQ structure corresponding to inr and devno. |
* |
* This functions attempts to lookup the IRQ structure |
* corresponding to its arguments. On success, this |
* function returns with interrups disabled, holding |
* the lock of the respective IRQ structure. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param inr INR being looked up. |
* @param devno Devno being looked up. |
* |
* @return Locked IRQ structure on success or NULL on failure. |
*/ |
irq_t *irq_find_and_lock(inr_t inr, devno_t devno) |
{ |
link_t *lnk; |
unative_t keys[] = { |
(unative_t) inr, |
(unative_t) devno |
}; |
spinlock_lock(&irq_hash_table_lock); |
lnk = hash_table_find(&irq_hash_table, keys); |
if (lnk) { |
irq_t *irq; |
irq = hash_table_get_instance(lnk, irq_t, link); |
spinlock_unlock(&irq_hash_table_lock); |
return irq; |
} |
spinlock_unlock(&irq_hash_table_lock); |
return NULL; |
} |
/** Compute hash index for the key. |
* |
* This function computes hash index into |
* the IRQ hash table for which there |
* can be collisions between different |
* INRs. |
* |
* The devno is not used to compute the hash. |
* |
* @param key The first of the keys is inr and the second is devno or -1. |
* |
* @return Index into the hash table. |
*/ |
index_t irq_ht_hash(unative_t key[]) |
{ |
inr_t inr = (inr_t) key[KEY_INR]; |
return inr % irq_hash_table.entries; |
} |
/** Compare hash table element with a key. |
* |
* There are two things to note about this function. |
* First, it is used for the more complex architecture setup |
* in which there are way too many interrupt numbers (i.e. inr's) |
* to arrange the hash table so that collisions occur only |
* among same inrs of different devnos. So the explicit check |
* for inr match must be done. |
* Second, if devno is -1, the second key (i.e. devno) is not |
* used for the match and the result of the claim() function |
* is used instead. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param key Keys (i.e. inr and devno). |
* @param keys This is 2. |
* @param item The item to compare the key with. |
* |
* @return True on match or false otherwise. |
*/ |
bool irq_ht_compare(unative_t key[], count_t keys, link_t *item) |
{ |
irq_t *irq = hash_table_get_instance(item, irq_t, link); |
inr_t inr = (inr_t) key[KEY_INR]; |
devno_t devno = (devno_t) key[KEY_DEVNO]; |
bool rv; |
spinlock_lock(&irq->lock); |
if (devno == -1) { |
/* Invoked by irq_dispatch_and_lock(). */ |
rv = ((irq->inr == inr) && (irq->claim() == IRQ_ACCEPT)); |
} else { |
/* Invoked by irq_find_and_lock(). */ |
rv = ((irq->inr == inr) && (irq->devno == devno)); |
} |
/* unlock only on non-match */ |
if (!rv) |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** Compute hash index for the key. |
* |
* This function computes hash index into |
* the IRQ hash table for which there |
* are no collisions between different |
* INRs. |
* |
* @param key The first of the keys is inr and the second is devno or -1. |
* |
* @return Index into the hash table. |
*/ |
index_t irq_lin_hash(unative_t key[]) |
{ |
inr_t inr = (inr_t) key[KEY_INR]; |
return inr; |
} |
/** Compare hash table element with a key. |
* |
* There are two things to note about this function. |
* First, it is used for the less complex architecture setup |
* in which there are not too many interrupt numbers (i.e. inr's) |
* to arrange the hash table so that collisions occur only |
* among same inrs of different devnos. So the explicit check |
* for inr match is not done. |
* Second, if devno is -1, the second key (i.e. devno) is not |
* used for the match and the result of the claim() function |
* is used instead. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param key Keys (i.e. inr and devno). |
* @param keys This is 2. |
* @param item The item to compare the key with. |
* |
* @return True on match or false otherwise. |
*/ |
bool irq_lin_compare(unative_t key[], count_t keys, link_t *item) |
{ |
irq_t *irq = list_get_instance(item, irq_t, link); |
devno_t devno = (devno_t) key[KEY_DEVNO]; |
bool rv; |
spinlock_lock(&irq->lock); |
if (devno == -1) { |
/* Invoked by irq_dispatch_and_lock() */ |
rv = (irq->claim() == IRQ_ACCEPT); |
} else { |
/* Invoked by irq_find_and_lock() */ |
rv = (irq->devno == devno); |
} |
/* unlock only on non-match */ |
if (!rv) |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2006 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup genericddi |
* @{ |
*/ |
/** |
* @file |
* @brief IRQ dispatcher. |
* |
* This file provides means of connecting IRQs with particular |
* devices and logic for dispatching interrupts to IRQ handlers |
* defined by those devices. |
* |
* This code is designed to support: |
* - multiple devices sharing single IRQ |
* - multiple IRQs per signle device |
* |
* |
* Note about architectures. |
* |
* Some architectures has the term IRQ well defined. Examples |
* of such architectures include amd64, ia32 and mips32. Some |
* other architectures, such as sparc64, don't use the term |
* at all. In those cases, we boldly step forward and define what |
* an IRQ is. |
* |
* The implementation is generic enough and still allows the |
* architectures to use the hardware layout effectively. |
* For instance, on amd64 and ia32, where there is only 16 |
* IRQs, the irq_hash_table can be optimized to a one-dimensional |
* array. Next, when it is known that the IRQ numbers (aka INR's) |
* are unique, the claim functions can always return IRQ_ACCEPT. |
* |
* |
* Note about the irq_hash_table. |
* |
* The hash table is configured to use two keys: inr and devno. |
* However, the hash index is computed only from inr. Moreover, |
* if devno is -1, the match is based on the return value of |
* the claim() function instead of on devno. |
*/ |
#include <ddi/irq.h> |
#include <adt/hash_table.h> |
#include <arch/types.h> |
#include <synch/spinlock.h> |
#include <arch.h> |
#define KEY_INR 0 |
#define KEY_DEVNO 1 |
/** |
* Spinlock protecting the hash table. |
* This lock must be taken only when interrupts are disabled. |
*/ |
SPINLOCK_INITIALIZE(irq_hash_table_lock); |
static hash_table_t irq_hash_table; |
/** |
* Hash table operations for cases when we know that |
* there will be collisions between different keys. |
*/ |
static index_t irq_ht_hash(unative_t *key); |
static bool irq_ht_compare(unative_t *key, count_t keys, link_t *item); |
static hash_table_operations_t irq_ht_ops = { |
.hash = irq_ht_hash, |
.compare = irq_ht_compare, |
.remove_callback = NULL /* not used */ |
}; |
/** |
* Hash table operations for cases when we know that |
* there will be no collisions between different keys. |
* However, there might be still collisions among |
* elements with single key (sharing of one IRQ). |
*/ |
static index_t irq_lin_hash(unative_t *key); |
static bool irq_lin_compare(unative_t *key, count_t keys, link_t *item); |
static hash_table_operations_t irq_lin_ops = { |
.hash = irq_lin_hash, |
.compare = irq_lin_compare, |
.remove_callback = NULL /* not used */ |
}; |
/** Initialize IRQ subsystem. |
* |
* @param inrs Numbers of unique IRQ numbers or INRs. |
* @param chains Number of chains in the hash table. |
*/ |
void irq_init(count_t inrs, count_t chains) |
{ |
/* |
* Be smart about the choice of the hash table operations. |
* In cases in which inrs equals the requested number of |
* chains (i.e. where there is no collision between |
* different keys), we can use optimized set of operations. |
*/ |
if (inrs == chains) |
hash_table_create(&irq_hash_table, chains, 2, &irq_lin_ops); |
else |
hash_table_create(&irq_hash_table, chains, 2, &irq_ht_ops); |
} |
/** Initialize one IRQ structure. |
* |
* @param irq Pointer to the IRQ structure to be initialized. |
* |
*/ |
void irq_initialize(irq_t *irq) |
{ |
link_initialize(&irq->link); |
spinlock_initialize(&irq->lock, "irq.lock"); |
irq->preack = false; |
irq->inr = -1; |
irq->devno = -1; |
irq->trigger = (irq_trigger_t) 0; |
irq->claim = NULL; |
irq->handler = NULL; |
irq->arg = NULL; |
irq->notif_cfg.notify = false; |
irq->notif_cfg.answerbox = NULL; |
irq->notif_cfg.code = NULL; |
irq->notif_cfg.method = 0; |
irq->notif_cfg.counter = 0; |
link_initialize(&irq->notif_cfg.link); |
} |
/** Register IRQ for device. |
* |
* The irq structure must be filled with information |
* about the interrupt source and with the claim() |
* function pointer and irq_handler() function pointer. |
* |
* @param irq IRQ structure belonging to a device. |
*/ |
void irq_register(irq_t *irq) |
{ |
ipl_t ipl; |
unative_t key[] = { |
(unative_t) irq->inr, |
(unative_t) irq->devno |
}; |
ipl = interrupts_disable(); |
spinlock_lock(&irq_hash_table_lock); |
hash_table_insert(&irq_hash_table, key, &irq->link); |
spinlock_unlock(&irq_hash_table_lock); |
interrupts_restore(ipl); |
} |
/** Dispatch the IRQ. |
* |
* We assume this function is only called from interrupt |
* context (i.e. that interrupts are disabled prior to |
* this call). |
* |
* This function attempts to lookup a fitting IRQ |
* structure. In case of success, return with interrupts |
* disabled and holding the respective structure. |
* |
* @param inr Interrupt number (aka inr or irq). |
* |
* @return IRQ structure of the respective device or NULL. |
*/ |
irq_t *irq_dispatch_and_lock(inr_t inr) |
{ |
link_t *lnk; |
unative_t key[] = { |
(unative_t) inr, |
(unative_t) -1 /* search will use claim() instead of devno */ |
}; |
spinlock_lock(&irq_hash_table_lock); |
lnk = hash_table_find(&irq_hash_table, key); |
if (lnk) { |
irq_t *irq; |
irq = hash_table_get_instance(lnk, irq_t, link); |
spinlock_unlock(&irq_hash_table_lock); |
return irq; |
} |
spinlock_unlock(&irq_hash_table_lock); |
return NULL; |
} |
/** Find the IRQ structure corresponding to inr and devno. |
* |
* This functions attempts to lookup the IRQ structure |
* corresponding to its arguments. On success, this |
* function returns with interrups disabled, holding |
* the lock of the respective IRQ structure. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param inr INR being looked up. |
* @param devno Devno being looked up. |
* |
* @return Locked IRQ structure on success or NULL on failure. |
*/ |
irq_t *irq_find_and_lock(inr_t inr, devno_t devno) |
{ |
link_t *lnk; |
unative_t keys[] = { |
(unative_t) inr, |
(unative_t) devno |
}; |
spinlock_lock(&irq_hash_table_lock); |
lnk = hash_table_find(&irq_hash_table, keys); |
if (lnk) { |
irq_t *irq; |
irq = hash_table_get_instance(lnk, irq_t, link); |
spinlock_unlock(&irq_hash_table_lock); |
return irq; |
} |
spinlock_unlock(&irq_hash_table_lock); |
return NULL; |
} |
/** Compute hash index for the key. |
* |
* This function computes hash index into |
* the IRQ hash table for which there |
* can be collisions between different |
* INRs. |
* |
* The devno is not used to compute the hash. |
* |
* @param key The first of the keys is inr and the second is devno or -1. |
* |
* @return Index into the hash table. |
*/ |
index_t irq_ht_hash(unative_t key[]) |
{ |
inr_t inr = (inr_t) key[KEY_INR]; |
return inr % irq_hash_table.entries; |
} |
/** Compare hash table element with a key. |
* |
* There are two things to note about this function. |
* First, it is used for the more complex architecture setup |
* in which there are way too many interrupt numbers (i.e. inr's) |
* to arrange the hash table so that collisions occur only |
* among same inrs of different devnos. So the explicit check |
* for inr match must be done. |
* Second, if devno is -1, the second key (i.e. devno) is not |
* used for the match and the result of the claim() function |
* is used instead. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param key Keys (i.e. inr and devno). |
* @param keys This is 2. |
* @param item The item to compare the key with. |
* |
* @return True on match or false otherwise. |
*/ |
bool irq_ht_compare(unative_t key[], count_t keys, link_t *item) |
{ |
irq_t *irq = hash_table_get_instance(item, irq_t, link); |
inr_t inr = (inr_t) key[KEY_INR]; |
devno_t devno = (devno_t) key[KEY_DEVNO]; |
bool rv; |
spinlock_lock(&irq->lock); |
if (devno == -1) { |
/* Invoked by irq_dispatch_and_lock(). */ |
rv = ((irq->inr == inr) && (irq->claim() == IRQ_ACCEPT)); |
} else { |
/* Invoked by irq_find_and_lock(). */ |
rv = ((irq->inr == inr) && (irq->devno == devno)); |
} |
/* unlock only on non-match */ |
if (!rv) |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** Compute hash index for the key. |
* |
* This function computes hash index into |
* the IRQ hash table for which there |
* are no collisions between different |
* INRs. |
* |
* @param key The first of the keys is inr and the second is devno or -1. |
* |
* @return Index into the hash table. |
*/ |
index_t irq_lin_hash(unative_t key[]) |
{ |
inr_t inr = (inr_t) key[KEY_INR]; |
return inr; |
} |
/** Compare hash table element with a key. |
* |
* There are two things to note about this function. |
* First, it is used for the less complex architecture setup |
* in which there are not too many interrupt numbers (i.e. inr's) |
* to arrange the hash table so that collisions occur only |
* among same inrs of different devnos. So the explicit check |
* for inr match is not done. |
* Second, if devno is -1, the second key (i.e. devno) is not |
* used for the match and the result of the claim() function |
* is used instead. |
* |
* This function assumes interrupts are already disabled. |
* |
* @param key Keys (i.e. inr and devno). |
* @param keys This is 2. |
* @param item The item to compare the key with. |
* |
* @return True on match or false otherwise. |
*/ |
bool irq_lin_compare(unative_t key[], count_t keys, link_t *item) |
{ |
irq_t *irq = list_get_instance(item, irq_t, link); |
devno_t devno = (devno_t) key[KEY_DEVNO]; |
bool rv; |
spinlock_lock(&irq->lock); |
if (devno == -1) { |
/* Invoked by irq_dispatch_and_lock() */ |
rv = (irq->claim() == IRQ_ACCEPT); |
} else { |
/* Invoked by irq_find_and_lock() */ |
rv = (irq->devno == devno); |
} |
/* unlock only on non-match */ |
if (!rv) |
spinlock_unlock(&irq->lock); |
return rv; |
} |
/** @} |
*/ |
/branches/rcu/kernel/Makefile |
---|
155,7 → 155,6 |
generic/src/ddi/ddi.c \ |
generic/src/ddi/irq.c \ |
generic/src/ddi/device.c \ |
generic/src/ddi/tasklet.c \ |
generic/src/interrupt/interrupt.c \ |
generic/src/main/main.c \ |
generic/src/main/kinit.c \ |
164,6 → 163,7 |
generic/src/proc/scheduler.c \ |
generic/src/proc/thread.c \ |
generic/src/proc/task.c \ |
generic/src/proc/tasklet.c \ |
generic/src/proc/the.c \ |
generic/src/syscall/syscall.c \ |
generic/src/syscall/copy.c \ |
/branches/rcu/kernel/arch/ppc32/src/interrupt.c |
---|
1,100 → 1,110 |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ppc32interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <ddi/irq.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <time/clock.h> |
#include <ipc/sysipc.h> |
#include <arch/drivers/pic.h> |
#include <arch/mm/tlb.h> |
#include <print.h> |
void start_decrementer(void) |
{ |
asm volatile ( |
"mtdec %0\n" |
: |
: "r" (1000) |
); |
} |
/** Handler of external interrupts */ |
static void exception_external(int n, istate_t *istate) |
{ |
int inum; |
while ((inum = pic_get_pending()) != -1) { |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
pic_ack_interrupt(inum); |
} |
} |
static void exception_decrementer(int n, istate_t *istate) |
{ |
clock(); |
start_decrementer(); |
} |
/* Initialize basic tables for exception dispatching */ |
void interrupt_init(void) |
{ |
exc_register(VECTOR_DATA_STORAGE, "data_storage", pht_refill); |
exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", pht_refill); |
exc_register(VECTOR_EXTERNAL, "external", exception_external); |
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ppc32interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <ddi/irq.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <time/clock.h> |
#include <ipc/sysipc.h> |
#include <arch/drivers/pic.h> |
#include <arch/mm/tlb.h> |
#include <print.h> |
void start_decrementer(void) |
{ |
asm volatile ( |
"mtdec %0\n" |
: |
: "r" (1000) |
); |
} |
/** Handler of external interrupts */ |
static void exception_external(int n, istate_t *istate) |
{ |
int inum; |
while ((inum = pic_get_pending()) != -1) { |
bool ack = false; |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
if (irq->preack) { |
/* Acknowledge the interrupt before processing */ |
pic_ack_interrupt(inum); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
if (!ack) |
pic_ack_interrupt(inum); |
} |
} |
static void exception_decrementer(int n, istate_t *istate) |
{ |
clock(); |
start_decrementer(); |
} |
/* Initialize basic tables for exception dispatching */ |
void interrupt_init(void) |
{ |
exc_register(VECTOR_DATA_STORAGE, "data_storage", pht_refill); |
exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", pht_refill); |
exc_register(VECTOR_EXTERNAL, "external", exception_external); |
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer); |
} |
/** @} |
*/ |
/branches/rcu/kernel/arch/ia32xen/src/interrupt.c |
---|
1,239 → 1,249 |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32xen_interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <syscall/syscall.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <ipc/sysipc.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(istate_t *istate) |
{ |
char *symbol = get_symtab_entry(istate->eip); |
if (!symbol) |
symbol = ""; |
if (CPU) |
printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id); |
else |
printf("----------------EXCEPTION OCCURED----------------\n"); |
printf("%%eip: %#x (%s)\n",istate->eip,symbol); |
printf("ERROR_WORD=%#x\n", istate->error_word); |
printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags); |
printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx); |
#endif |
printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); |
printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(istate); |
panic("unserviced interrupt: %d\n", n); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(istate); |
panic("stack fault\n"); |
} |
static void simd_fp_exception(int n, istate_t *istate) |
{ |
uint32_t mxcsr; |
asm |
( |
"stmxcsr %0;\n" |
:"=m"(mxcsr) |
); |
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
(unative_t)mxcsr); |
decode_istate(istate); |
printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
panic("SIMD FP exception(19)\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
#ifdef CONFIG_SMP |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
#endif |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32xen_interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <syscall/syscall.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <ipc/sysipc.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(istate_t *istate) |
{ |
char *symbol = get_symtab_entry(istate->eip); |
if (!symbol) |
symbol = ""; |
if (CPU) |
printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id); |
else |
printf("----------------EXCEPTION OCCURED----------------\n"); |
printf("%%eip: %#x (%s)\n",istate->eip,symbol); |
printf("ERROR_WORD=%#x\n", istate->error_word); |
printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags); |
printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx); |
#endif |
printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); |
printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(istate); |
panic("unserviced interrupt: %d\n", n); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(istate); |
panic("stack fault\n"); |
} |
static void simd_fp_exception(int n, istate_t *istate) |
{ |
uint32_t mxcsr; |
asm |
( |
"stmxcsr %0;\n" |
:"=m"(mxcsr) |
); |
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
(unative_t)mxcsr); |
decode_istate(istate); |
printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
panic("SIMD FP exception(19)\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
#ifdef CONFIG_SMP |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
#endif |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
bool ack = false; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
if (irq->preack) { |
/* Send EOI before processing the interrupt */ |
trap_virtual_eoi(); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
if (!ack) |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/branches/rcu/kernel/arch/amd64/src/interrupt.c |
---|
1,219 → 1,228 |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup amd64interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <arch/drivers/i8259.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <arch/asm.h> |
#include <proc/scheduler.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(int n, istate_t *istate) |
{ |
char *symbol; |
/* uint64_t *x = &istate->stack[0]; */ |
if (!(symbol=get_symtab_entry(istate->rip))) |
symbol = ""; |
printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n",n, __FUNCTION__); |
printf("%%rip: %#llx (%s)\n",istate->rip, symbol); |
printf("ERROR_WORD=%#llx\n", istate->error_word); |
printf("%%rcs=%#llx, flags=%#llx, %%cr0=%#llx\n", istate->cs, istate->rflags, read_cr0()); |
printf("%%rax=%#llx, %%rcx=%#llx, %%rdx=%#llx\n", istate->rax, istate->rcx, istate->rdx); |
printf("%%rsi=%#llx, %%rdi=%#llx, %%r8 =%#llx\n", istate->rsi, istate->rdi, istate->r8); |
printf("%%r9 =%#llx, %%r10 =%#llx, %%r11=%#llx\n", istate->r9, istate->r10, istate->r11); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%r12=%#llx, %%r13=%#llx, %%r14=%#llx\n", istate->r12, istate->r13, istate->r14); |
printf("%%r15=%#llx, %%rbx=%#llx, %%rbp=%#llx\n", istate->r15, istate->rbx, &istate->rbp); |
#endif |
printf("%%rsp=%#llx\n", &istate->stack[0]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(n, istate); |
panic("unserviced interrupt\n"); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(n, istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(n, istate); |
panic("stack fault\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(14, "ident_mapper", (iroutine) ident_page_fault); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup amd64interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <arch/drivers/i8259.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <arch/asm.h> |
#include <proc/scheduler.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(int n, istate_t *istate) |
{ |
char *symbol; |
/* uint64_t *x = &istate->stack[0]; */ |
if (!(symbol=get_symtab_entry(istate->rip))) |
symbol = ""; |
printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n",n, __FUNCTION__); |
printf("%%rip: %#llx (%s)\n",istate->rip, symbol); |
printf("ERROR_WORD=%#llx\n", istate->error_word); |
printf("%%rcs=%#llx, flags=%#llx, %%cr0=%#llx\n", istate->cs, istate->rflags, read_cr0()); |
printf("%%rax=%#llx, %%rcx=%#llx, %%rdx=%#llx\n", istate->rax, istate->rcx, istate->rdx); |
printf("%%rsi=%#llx, %%rdi=%#llx, %%r8 =%#llx\n", istate->rsi, istate->rdi, istate->r8); |
printf("%%r9 =%#llx, %%r10 =%#llx, %%r11=%#llx\n", istate->r9, istate->r10, istate->r11); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%r12=%#llx, %%r13=%#llx, %%r14=%#llx\n", istate->r12, istate->r13, istate->r14); |
printf("%%r15=%#llx, %%rbx=%#llx, %%rbp=%#llx\n", istate->r15, istate->rbx, &istate->rbp); |
#endif |
printf("%%rsp=%#llx\n", &istate->stack[0]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(n, istate); |
panic("unserviced interrupt\n"); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(n, istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(n, istate); |
panic("stack fault\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
bool ack = false; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
if (irq->preack) { |
/* Send EOI before processing the interrupt */ |
trap_virtual_eoi(); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
if (!ack) |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(14, "ident_mapper", (iroutine) ident_page_fault); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/branches/rcu/kernel/arch/ppc64/src/interrupt.c |
---|
1,98 → 1,108 |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ppc64interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <ddi/irq.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <time/clock.h> |
#include <ipc/sysipc.h> |
#include <arch/drivers/pic.h> |
#include <arch/mm/tlb.h> |
#include <print.h> |
void start_decrementer(void) |
{ |
asm volatile ( |
"mtdec %0\n" |
: |
: "r" (1000) |
); |
} |
/** Handler of external interrupts */ |
static void exception_external(int n, istate_t *istate) |
{ |
int inum; |
while ((inum = pic_get_pending()) != -1) { |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
pic_ack_interrupt(inum); |
} |
} |
static void exception_decrementer(int n, istate_t *istate) |
{ |
clock(); |
start_decrementer(); |
} |
/* Initialize basic tables for exception dispatching */ |
void interrupt_init(void) |
{ |
exc_register(VECTOR_EXTERNAL, "external", exception_external); |
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ppc64interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <ddi/irq.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <arch/types.h> |
#include <arch.h> |
#include <time/clock.h> |
#include <ipc/sysipc.h> |
#include <arch/drivers/pic.h> |
#include <arch/mm/tlb.h> |
#include <print.h> |
void start_decrementer(void) |
{ |
asm volatile ( |
"mtdec %0\n" |
: |
: "r" (1000) |
); |
} |
/** Handler of external interrupts */ |
static void exception_external(int n, istate_t *istate) |
{ |
int inum; |
while ((inum = pic_get_pending()) != -1) { |
bool ack = false; |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
if (irq->preack) { |
/* Acknowledge the interrupt before processing */ |
pic_ack_interrupt(inum); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
if (!ack) |
pic_ack_interrupt(inum); |
} |
} |
static void exception_decrementer(int n, istate_t *istate) |
{ |
clock(); |
start_decrementer(); |
} |
/* Initialize basic tables for exception dispatching */ |
void interrupt_init(void) |
{ |
exc_register(VECTOR_EXTERNAL, "external", exception_external); |
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer); |
} |
/** @} |
*/ |
/branches/rcu/kernel/arch/ia32/src/smp/apic.c |
---|
1,587 → 1,595 |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32 |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/types.h> |
#include <arch/smp/apic.h> |
#include <arch/smp/ap.h> |
#include <arch/smp/mps.h> |
#include <arch/boot/boot.h> |
#include <mm/page.h> |
#include <time/delay.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <print.h> |
#include <arch/asm.h> |
#include <arch.h> |
#include <ddi/irq.h> |
#include <ddi/device.h> |
#ifdef CONFIG_SMP |
/* |
* Advanced Programmable Interrupt Controller for SMP systems. |
* Tested on: |
* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
* VMware Workstation 5.5 with 2 CPUs |
* QEMU 0.8.0 with 2-15 CPUs |
* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
*/ |
/* |
* These variables either stay configured as initilalized, or are changed by |
* the MP configuration code. |
* |
* Pay special attention to the volatile keyword. Without it, gcc -O2 would |
* optimize the code too much and accesses to l_apic and io_apic, that must |
* always be 32-bit, would use byte oriented instructions. |
*/ |
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
uint32_t apic_id_mask = 0; |
static irq_t l_apic_timer_irq; |
static int apic_poll_errors(void); |
#ifdef LAPIC_VERBOSE |
static char *delmod_str[] = { |
"Fixed", |
"Lowest Priority", |
"SMI", |
"Reserved", |
"NMI", |
"INIT", |
"STARTUP", |
"ExtInt" |
}; |
static char *destmod_str[] = { |
"Physical", |
"Logical" |
}; |
static char *trigmod_str[] = { |
"Edge", |
"Level" |
}; |
static char *mask_str[] = { |
"Unmasked", |
"Masked" |
}; |
static char *delivs_str[] = { |
"Idle", |
"Send Pending" |
}; |
static char *tm_mode_str[] = { |
"One-shot", |
"Periodic" |
}; |
static char *intpol_str[] = { |
"Polarity High", |
"Polarity Low" |
}; |
#endif /* LAPIC_VERBOSE */ |
/** APIC spurious interrupt handler. |
* |
* @param n Interrupt vector. |
* @param istate Interrupted state. |
*/ |
static void apic_spurious(int n, istate_t *istate) |
{ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
#endif |
} |
static irq_ownership_t l_apic_timer_claim(void) |
{ |
return IRQ_ACCEPT; |
} |
static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...) |
{ |
clock(); |
} |
/** Initialize APIC on BSP. */ |
void apic_init(void) |
{ |
io_apic_id_t idreg; |
unsigned int i; |
exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
enable_irqs_function = io_apic_enable_irqs; |
disable_irqs_function = io_apic_disable_irqs; |
eoi_function = l_apic_eoi; |
/* |
* Configure interrupt routing. |
* IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
* Other interrupts will be forwarded to the lowest priority CPU. |
*/ |
io_apic_disable_irqs(0xffff); |
irq_initialize(&l_apic_timer_irq); |
l_apic_timer_irq.devno = device_assign_devno(); |
l_apic_timer_irq.inr = IRQ_CLK; |
l_apic_timer_irq.claim = l_apic_timer_claim; |
l_apic_timer_irq.handler = l_apic_timer_irq_handler; |
irq_register(&l_apic_timer_irq); |
for (i = 0; i < IRQ_COUNT; i++) { |
int pin; |
if ((pin = smp_irq_to_pin(i)) != -1) |
io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI); |
} |
/* |
* Ensure that io_apic has unique ID. |
*/ |
idreg.value = io_apic_read(IOAPICID); |
if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
for (i = 0; i < APIC_ID_COUNT; i++) { |
if (!((1 << i) & apic_id_mask)) { |
idreg.apic_id = i; |
io_apic_write(IOAPICID, idreg.value); |
break; |
} |
} |
} |
/* |
* Configure the BSP's lapic. |
*/ |
l_apic_init(); |
l_apic_debug(); |
} |
/** Poll for APIC errors. |
* |
* Examine Error Status Register and report all errors found. |
* |
* @return 0 on error, 1 on success. |
*/ |
int apic_poll_errors(void) |
{ |
esr_t esr; |
esr.value = l_apic[ESR]; |
if (esr.send_checksum_error) |
printf("Send Checksum Error\n"); |
if (esr.receive_checksum_error) |
printf("Receive Checksum Error\n"); |
if (esr.send_accept_error) |
printf("Send Accept Error\n"); |
if (esr.receive_accept_error) |
printf("Receive Accept Error\n"); |
if (esr.send_illegal_vector) |
printf("Send Illegal Vector\n"); |
if (esr.received_illegal_vector) |
printf("Received Illegal Vector\n"); |
if (esr.illegal_register_address) |
printf("Illegal Register Address\n"); |
return !esr.err_bitmap; |
} |
/** Send all CPUs excluding CPU IPI vector. |
* |
* @param vector Interrupt vector to be sent. |
* |
* @return 0 on failure, 1 on success. |
*/ |
int l_apic_broadcast_custom_ipi(uint8_t vector) |
{ |
icr_t icr; |
icr.lo = l_apic[ICRlo]; |
icr.delmod = DELMOD_FIXED; |
icr.destmod = DESTMOD_LOGIC; |
icr.level = LEVEL_ASSERT; |
icr.shorthand = SHORTHAND_ALL_EXCL; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.vector = vector; |
l_apic[ICRlo] = icr.lo; |
icr.lo = l_apic[ICRlo]; |
if (icr.delivs == DELIVS_PENDING) { |
#ifdef CONFIG_DEBUG |
printf("IPI is pending.\n"); |
#endif |
} |
return apic_poll_errors(); |
} |
/** Universal Start-up Algorithm for bringing up the AP processors. |
* |
* @param apicid APIC ID of the processor to be brought up. |
* |
* @return 0 on failure, 1 on success. |
*/ |
int l_apic_send_init_ipi(uint8_t apicid) |
{ |
icr_t icr; |
int i; |
/* |
* Read the ICR register in and zero all non-reserved fields. |
*/ |
icr.lo = l_apic[ICRlo]; |
icr.hi = l_apic[ICRhi]; |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_ASSERT; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.shorthand = SHORTHAND_NONE; |
icr.vector = 0; |
icr.dest = apicid; |
l_apic[ICRhi] = icr.hi; |
l_apic[ICRlo] = icr.lo; |
/* |
* According to MP Specification, 20us should be enough to |
* deliver the IPI. |
*/ |
delay(20); |
if (!apic_poll_errors()) |
return 0; |
icr.lo = l_apic[ICRlo]; |
if (icr.delivs == DELIVS_PENDING) { |
#ifdef CONFIG_DEBUG |
printf("IPI is pending.\n"); |
#endif |
} |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_DEASSERT; |
icr.shorthand = SHORTHAND_NONE; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.vector = 0; |
l_apic[ICRlo] = icr.lo; |
/* |
* Wait 10ms as MP Specification specifies. |
*/ |
delay(10000); |
if (!is_82489DX_apic(l_apic[LAVR])) { |
/* |
* If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
*/ |
for (i = 0; i<2; i++) { |
icr.lo = l_apic[ICRlo]; |
icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
icr.delmod = DELMOD_STARTUP; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_ASSERT; |
icr.shorthand = SHORTHAND_NONE; |
icr.trigger_mode = TRIGMOD_LEVEL; |
l_apic[ICRlo] = icr.lo; |
delay(200); |
} |
} |
return apic_poll_errors(); |
} |
/** Initialize Local APIC. */ |
void l_apic_init(void) |
{ |
lvt_error_t error; |
lvt_lint_t lint; |
tpr_t tpr; |
svr_t svr; |
icr_t icr; |
tdcr_t tdcr; |
lvt_tm_t tm; |
ldr_t ldr; |
dfr_t dfr; |
uint32_t t1, t2; |
/* Initialize LVT Error register. */ |
error.value = l_apic[LVT_Err]; |
error.masked = true; |
l_apic[LVT_Err] = error.value; |
/* Initialize LVT LINT0 register. */ |
lint.value = l_apic[LVT_LINT0]; |
lint.masked = true; |
l_apic[LVT_LINT0] = lint.value; |
/* Initialize LVT LINT1 register. */ |
lint.value = l_apic[LVT_LINT1]; |
lint.masked = true; |
l_apic[LVT_LINT1] = lint.value; |
/* Task Priority Register initialization. */ |
tpr.value = l_apic[TPR]; |
tpr.pri_sc = 0; |
tpr.pri = 0; |
l_apic[TPR] = tpr.value; |
/* Spurious-Interrupt Vector Register initialization. */ |
svr.value = l_apic[SVR]; |
svr.vector = VECTOR_APIC_SPUR; |
svr.lapic_enabled = true; |
svr.focus_checking = true; |
l_apic[SVR] = svr.value; |
if (CPU->arch.family >= 6) |
enable_l_apic_in_msr(); |
/* Interrupt Command Register initialization. */ |
icr.lo = l_apic[ICRlo]; |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_DEASSERT; |
icr.shorthand = SHORTHAND_ALL_INCL; |
icr.trigger_mode = TRIGMOD_LEVEL; |
l_apic[ICRlo] = icr.lo; |
/* Timer Divide Configuration Register initialization. */ |
tdcr.value = l_apic[TDCR]; |
tdcr.div_value = DIVIDE_1; |
l_apic[TDCR] = tdcr.value; |
/* Program local timer. */ |
tm.value = l_apic[LVT_Tm]; |
tm.vector = VECTOR_CLK; |
tm.mode = TIMER_PERIODIC; |
tm.masked = false; |
l_apic[LVT_Tm] = tm.value; |
/* |
* Measure and configure the timer to generate timer |
* interrupt with period 1s/HZ seconds. |
*/ |
t1 = l_apic[CCRT]; |
l_apic[ICRT] = 0xffffffff; |
while (l_apic[CCRT] == t1) |
; |
t1 = l_apic[CCRT]; |
delay(1000000/HZ); |
t2 = l_apic[CCRT]; |
l_apic[ICRT] = t1-t2; |
/* Program Logical Destination Register. */ |
ldr.value = l_apic[LDR]; |
if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
ldr.id = (1<<CPU->id); |
l_apic[LDR] = ldr.value; |
/* Program Destination Format Register for Flat mode. */ |
dfr.value = l_apic[DFR]; |
dfr.model = MODEL_FLAT; |
l_apic[DFR] = dfr.value; |
} |
/** Local APIC End of Interrupt. */ |
void l_apic_eoi(void) |
{ |
l_apic[EOI] = 0; |
} |
/** Dump content of Local APIC registers. */ |
void l_apic_debug(void) |
{ |
#ifdef LAPIC_VERBOSE |
lvt_tm_t tm; |
lvt_lint_t lint; |
lvt_error_t error; |
printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
tm.value = l_apic[LVT_Tm]; |
printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
lint.value = l_apic[LVT_LINT0]; |
printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
lint.value = l_apic[LVT_LINT1]; |
printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
error.value = l_apic[LVT_Err]; |
printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
#endif |
} |
/** Get Local APIC ID. |
* |
* @return Local APIC ID. |
*/ |
uint8_t l_apic_id(void) |
{ |
l_apic_id_t idreg; |
idreg.value = l_apic[L_APIC_ID]; |
return idreg.apic_id; |
} |
/** Read from IO APIC register. |
* |
* @param address IO APIC register address. |
* |
* @return Content of the addressed IO APIC register. |
*/ |
uint32_t io_apic_read(uint8_t address) |
{ |
io_regsel_t regsel; |
regsel.value = io_apic[IOREGSEL]; |
regsel.reg_addr = address; |
io_apic[IOREGSEL] = regsel.value; |
return io_apic[IOWIN]; |
} |
/** Write to IO APIC register. |
* |
* @param address IO APIC register address. |
* @param x Content to be written to the addressed IO APIC register. |
*/ |
void io_apic_write(uint8_t address, uint32_t x) |
{ |
io_regsel_t regsel; |
regsel.value = io_apic[IOREGSEL]; |
regsel.reg_addr = address; |
io_apic[IOREGSEL] = regsel.value; |
io_apic[IOWIN] = x; |
} |
/** Change some attributes of one item in I/O Redirection Table. |
* |
* @param pin IO APIC pin number. |
* @param dest Interrupt destination address. |
* @param v Interrupt vector to trigger. |
* @param flags Flags. |
*/ |
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
{ |
io_redirection_reg_t reg; |
int dlvr = DELMOD_FIXED; |
if (flags & LOPRI) |
dlvr = DELMOD_LOWPRI; |
reg.lo = io_apic_read(IOREDTBL + pin*2); |
reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
reg.dest = dest; |
reg.destmod = DESTMOD_LOGIC; |
reg.trigger_mode = TRIGMOD_EDGE; |
reg.intpol = POLARITY_HIGH; |
reg.delmod = dlvr; |
reg.intvec = v; |
io_apic_write(IOREDTBL + pin*2, reg.lo); |
io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
} |
/** Mask IRQs in IO APIC. |
* |
* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
*/ |
void io_apic_disable_irqs(uint16_t irqmask) |
{ |
io_redirection_reg_t reg; |
unsigned int i; |
int pin; |
for (i = 0; i < 16; i++) { |
if (irqmask & (1 << i)) { |
/* |
* Mask the signal input in IO APIC if there is a |
* mapping for the respective IRQ number. |
*/ |
pin = smp_irq_to_pin(i); |
if (pin != -1) { |
reg.lo = io_apic_read(IOREDTBL + pin * 2); |
reg.masked = true; |
io_apic_write(IOREDTBL + pin * 2, reg.lo); |
} |
} |
} |
} |
/** Unmask IRQs in IO APIC. |
* |
* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
*/ |
void io_apic_enable_irqs(uint16_t irqmask) |
{ |
unsigned int i; |
int pin; |
io_redirection_reg_t reg; |
for (i = 0;i < 16; i++) { |
if (irqmask & (1 << i)) { |
/* |
* Unmask the signal input in IO APIC if there is a |
* mapping for the respective IRQ number. |
*/ |
pin = smp_irq_to_pin(i); |
if (pin != -1) { |
reg.lo = io_apic_read(IOREDTBL + pin * 2); |
reg.masked = false; |
io_apic_write(IOREDTBL + pin * 2, reg.lo); |
} |
} |
} |
} |
#endif /* CONFIG_SMP */ |
/** @} |
*/ |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32 |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/types.h> |
#include <arch/smp/apic.h> |
#include <arch/smp/ap.h> |
#include <arch/smp/mps.h> |
#include <arch/boot/boot.h> |
#include <mm/page.h> |
#include <time/delay.h> |
#include <interrupt.h> |
#include <arch/interrupt.h> |
#include <print.h> |
#include <arch/asm.h> |
#include <arch.h> |
#include <ddi/irq.h> |
#include <ddi/device.h> |
#ifdef CONFIG_SMP |
/* |
* Advanced Programmable Interrupt Controller for SMP systems. |
* Tested on: |
* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
* VMware Workstation 5.5 with 2 CPUs |
* QEMU 0.8.0 with 2-15 CPUs |
* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
*/ |
/* |
* These variables either stay configured as initilalized, or are changed by |
* the MP configuration code. |
* |
* Pay special attention to the volatile keyword. Without it, gcc -O2 would |
* optimize the code too much and accesses to l_apic and io_apic, that must |
* always be 32-bit, would use byte oriented instructions. |
*/ |
volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
uint32_t apic_id_mask = 0; |
static irq_t l_apic_timer_irq; |
static int apic_poll_errors(void); |
#ifdef LAPIC_VERBOSE |
static char *delmod_str[] = { |
"Fixed", |
"Lowest Priority", |
"SMI", |
"Reserved", |
"NMI", |
"INIT", |
"STARTUP", |
"ExtInt" |
}; |
static char *destmod_str[] = { |
"Physical", |
"Logical" |
}; |
static char *trigmod_str[] = { |
"Edge", |
"Level" |
}; |
static char *mask_str[] = { |
"Unmasked", |
"Masked" |
}; |
static char *delivs_str[] = { |
"Idle", |
"Send Pending" |
}; |
static char *tm_mode_str[] = { |
"One-shot", |
"Periodic" |
}; |
static char *intpol_str[] = { |
"Polarity High", |
"Polarity Low" |
}; |
#endif /* LAPIC_VERBOSE */ |
/** APIC spurious interrupt handler. |
* |
* @param n Interrupt vector. |
* @param istate Interrupted state. |
*/ |
static void apic_spurious(int n, istate_t *istate) |
{ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
#endif |
} |
static irq_ownership_t l_apic_timer_claim(void) |
{ |
return IRQ_ACCEPT; |
} |
static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...) |
{ |
/* |
* Holding a spinlock could prevent clock() from preempting |
* the current thread. In this case, we don't need to hold the |
* irq->lock so we just unlock it and then lock it again. |
*/ |
spinlock_unlock(&irq->lock); |
clock(); |
spinlock_lock(&irq->lock); |
} |
/** Initialize APIC on BSP. */ |
void apic_init(void) |
{ |
io_apic_id_t idreg; |
unsigned int i; |
exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
enable_irqs_function = io_apic_enable_irqs; |
disable_irqs_function = io_apic_disable_irqs; |
eoi_function = l_apic_eoi; |
/* |
* Configure interrupt routing. |
* IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
* Other interrupts will be forwarded to the lowest priority CPU. |
*/ |
io_apic_disable_irqs(0xffff); |
irq_initialize(&l_apic_timer_irq); |
l_apic_timer_irq.preack = true; |
l_apic_timer_irq.devno = device_assign_devno(); |
l_apic_timer_irq.inr = IRQ_CLK; |
l_apic_timer_irq.claim = l_apic_timer_claim; |
l_apic_timer_irq.handler = l_apic_timer_irq_handler; |
irq_register(&l_apic_timer_irq); |
for (i = 0; i < IRQ_COUNT; i++) { |
int pin; |
if ((pin = smp_irq_to_pin(i)) != -1) |
io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI); |
} |
/* |
* Ensure that io_apic has unique ID. |
*/ |
idreg.value = io_apic_read(IOAPICID); |
if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
for (i = 0; i < APIC_ID_COUNT; i++) { |
if (!((1 << i) & apic_id_mask)) { |
idreg.apic_id = i; |
io_apic_write(IOAPICID, idreg.value); |
break; |
} |
} |
} |
/* |
* Configure the BSP's lapic. |
*/ |
l_apic_init(); |
l_apic_debug(); |
} |
/** Poll for APIC errors. |
* |
* Examine Error Status Register and report all errors found. |
* |
* @return 0 on error, 1 on success. |
*/ |
int apic_poll_errors(void) |
{ |
esr_t esr; |
esr.value = l_apic[ESR]; |
if (esr.send_checksum_error) |
printf("Send Checksum Error\n"); |
if (esr.receive_checksum_error) |
printf("Receive Checksum Error\n"); |
if (esr.send_accept_error) |
printf("Send Accept Error\n"); |
if (esr.receive_accept_error) |
printf("Receive Accept Error\n"); |
if (esr.send_illegal_vector) |
printf("Send Illegal Vector\n"); |
if (esr.received_illegal_vector) |
printf("Received Illegal Vector\n"); |
if (esr.illegal_register_address) |
printf("Illegal Register Address\n"); |
return !esr.err_bitmap; |
} |
/** Send all CPUs excluding CPU IPI vector. |
* |
* @param vector Interrupt vector to be sent. |
* |
* @return 0 on failure, 1 on success. |
*/ |
int l_apic_broadcast_custom_ipi(uint8_t vector) |
{ |
icr_t icr; |
icr.lo = l_apic[ICRlo]; |
icr.delmod = DELMOD_FIXED; |
icr.destmod = DESTMOD_LOGIC; |
icr.level = LEVEL_ASSERT; |
icr.shorthand = SHORTHAND_ALL_EXCL; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.vector = vector; |
l_apic[ICRlo] = icr.lo; |
icr.lo = l_apic[ICRlo]; |
if (icr.delivs == DELIVS_PENDING) { |
#ifdef CONFIG_DEBUG |
printf("IPI is pending.\n"); |
#endif |
} |
return apic_poll_errors(); |
} |
/** Universal Start-up Algorithm for bringing up the AP processors. |
* |
* @param apicid APIC ID of the processor to be brought up. |
* |
* @return 0 on failure, 1 on success. |
*/ |
int l_apic_send_init_ipi(uint8_t apicid) |
{ |
icr_t icr; |
int i; |
/* |
* Read the ICR register in and zero all non-reserved fields. |
*/ |
icr.lo = l_apic[ICRlo]; |
icr.hi = l_apic[ICRhi]; |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_ASSERT; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.shorthand = SHORTHAND_NONE; |
icr.vector = 0; |
icr.dest = apicid; |
l_apic[ICRhi] = icr.hi; |
l_apic[ICRlo] = icr.lo; |
/* |
* According to MP Specification, 20us should be enough to |
* deliver the IPI. |
*/ |
delay(20); |
if (!apic_poll_errors()) |
return 0; |
icr.lo = l_apic[ICRlo]; |
if (icr.delivs == DELIVS_PENDING) { |
#ifdef CONFIG_DEBUG |
printf("IPI is pending.\n"); |
#endif |
} |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_DEASSERT; |
icr.shorthand = SHORTHAND_NONE; |
icr.trigger_mode = TRIGMOD_LEVEL; |
icr.vector = 0; |
l_apic[ICRlo] = icr.lo; |
/* |
* Wait 10ms as MP Specification specifies. |
*/ |
delay(10000); |
if (!is_82489DX_apic(l_apic[LAVR])) { |
/* |
* If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
*/ |
for (i = 0; i<2; i++) { |
icr.lo = l_apic[ICRlo]; |
icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
icr.delmod = DELMOD_STARTUP; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_ASSERT; |
icr.shorthand = SHORTHAND_NONE; |
icr.trigger_mode = TRIGMOD_LEVEL; |
l_apic[ICRlo] = icr.lo; |
delay(200); |
} |
} |
return apic_poll_errors(); |
} |
/** Initialize Local APIC. */ |
void l_apic_init(void) |
{ |
lvt_error_t error; |
lvt_lint_t lint; |
tpr_t tpr; |
svr_t svr; |
icr_t icr; |
tdcr_t tdcr; |
lvt_tm_t tm; |
ldr_t ldr; |
dfr_t dfr; |
uint32_t t1, t2; |
/* Initialize LVT Error register. */ |
error.value = l_apic[LVT_Err]; |
error.masked = true; |
l_apic[LVT_Err] = error.value; |
/* Initialize LVT LINT0 register. */ |
lint.value = l_apic[LVT_LINT0]; |
lint.masked = true; |
l_apic[LVT_LINT0] = lint.value; |
/* Initialize LVT LINT1 register. */ |
lint.value = l_apic[LVT_LINT1]; |
lint.masked = true; |
l_apic[LVT_LINT1] = lint.value; |
/* Task Priority Register initialization. */ |
tpr.value = l_apic[TPR]; |
tpr.pri_sc = 0; |
tpr.pri = 0; |
l_apic[TPR] = tpr.value; |
/* Spurious-Interrupt Vector Register initialization. */ |
svr.value = l_apic[SVR]; |
svr.vector = VECTOR_APIC_SPUR; |
svr.lapic_enabled = true; |
svr.focus_checking = true; |
l_apic[SVR] = svr.value; |
if (CPU->arch.family >= 6) |
enable_l_apic_in_msr(); |
/* Interrupt Command Register initialization. */ |
icr.lo = l_apic[ICRlo]; |
icr.delmod = DELMOD_INIT; |
icr.destmod = DESTMOD_PHYS; |
icr.level = LEVEL_DEASSERT; |
icr.shorthand = SHORTHAND_ALL_INCL; |
icr.trigger_mode = TRIGMOD_LEVEL; |
l_apic[ICRlo] = icr.lo; |
/* Timer Divide Configuration Register initialization. */ |
tdcr.value = l_apic[TDCR]; |
tdcr.div_value = DIVIDE_1; |
l_apic[TDCR] = tdcr.value; |
/* Program local timer. */ |
tm.value = l_apic[LVT_Tm]; |
tm.vector = VECTOR_CLK; |
tm.mode = TIMER_PERIODIC; |
tm.masked = false; |
l_apic[LVT_Tm] = tm.value; |
/* |
* Measure and configure the timer to generate timer |
* interrupt with period 1s/HZ seconds. |
*/ |
t1 = l_apic[CCRT]; |
l_apic[ICRT] = 0xffffffff; |
while (l_apic[CCRT] == t1) |
; |
t1 = l_apic[CCRT]; |
delay(1000000/HZ); |
t2 = l_apic[CCRT]; |
l_apic[ICRT] = t1-t2; |
/* Program Logical Destination Register. */ |
ldr.value = l_apic[LDR]; |
if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
ldr.id = (1<<CPU->id); |
l_apic[LDR] = ldr.value; |
/* Program Destination Format Register for Flat mode. */ |
dfr.value = l_apic[DFR]; |
dfr.model = MODEL_FLAT; |
l_apic[DFR] = dfr.value; |
} |
/** Local APIC End of Interrupt. */ |
void l_apic_eoi(void) |
{ |
l_apic[EOI] = 0; |
} |
/** Dump content of Local APIC registers. */ |
void l_apic_debug(void) |
{ |
#ifdef LAPIC_VERBOSE |
lvt_tm_t tm; |
lvt_lint_t lint; |
lvt_error_t error; |
printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
tm.value = l_apic[LVT_Tm]; |
printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
lint.value = l_apic[LVT_LINT0]; |
printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
lint.value = l_apic[LVT_LINT1]; |
printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
error.value = l_apic[LVT_Err]; |
printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
#endif |
} |
/** Get Local APIC ID. |
* |
* @return Local APIC ID. |
*/ |
uint8_t l_apic_id(void) |
{ |
l_apic_id_t idreg; |
idreg.value = l_apic[L_APIC_ID]; |
return idreg.apic_id; |
} |
/** Read from IO APIC register. |
* |
* @param address IO APIC register address. |
* |
* @return Content of the addressed IO APIC register. |
*/ |
uint32_t io_apic_read(uint8_t address) |
{ |
io_regsel_t regsel; |
regsel.value = io_apic[IOREGSEL]; |
regsel.reg_addr = address; |
io_apic[IOREGSEL] = regsel.value; |
return io_apic[IOWIN]; |
} |
/** Write to IO APIC register. |
* |
* @param address IO APIC register address. |
* @param x Content to be written to the addressed IO APIC register. |
*/ |
void io_apic_write(uint8_t address, uint32_t x) |
{ |
io_regsel_t regsel; |
regsel.value = io_apic[IOREGSEL]; |
regsel.reg_addr = address; |
io_apic[IOREGSEL] = regsel.value; |
io_apic[IOWIN] = x; |
} |
/** Change some attributes of one item in I/O Redirection Table. |
* |
* @param pin IO APIC pin number. |
* @param dest Interrupt destination address. |
* @param v Interrupt vector to trigger. |
* @param flags Flags. |
*/ |
void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
{ |
io_redirection_reg_t reg; |
int dlvr = DELMOD_FIXED; |
if (flags & LOPRI) |
dlvr = DELMOD_LOWPRI; |
reg.lo = io_apic_read(IOREDTBL + pin*2); |
reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
reg.dest = dest; |
reg.destmod = DESTMOD_LOGIC; |
reg.trigger_mode = TRIGMOD_EDGE; |
reg.intpol = POLARITY_HIGH; |
reg.delmod = dlvr; |
reg.intvec = v; |
io_apic_write(IOREDTBL + pin*2, reg.lo); |
io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
} |
/** Mask IRQs in IO APIC. |
* |
* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
*/ |
void io_apic_disable_irqs(uint16_t irqmask) |
{ |
io_redirection_reg_t reg; |
unsigned int i; |
int pin; |
for (i = 0; i < 16; i++) { |
if (irqmask & (1 << i)) { |
/* |
* Mask the signal input in IO APIC if there is a |
* mapping for the respective IRQ number. |
*/ |
pin = smp_irq_to_pin(i); |
if (pin != -1) { |
reg.lo = io_apic_read(IOREDTBL + pin * 2); |
reg.masked = true; |
io_apic_write(IOREDTBL + pin * 2, reg.lo); |
} |
} |
} |
} |
/** Unmask IRQs in IO APIC. |
* |
* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
*/ |
void io_apic_enable_irqs(uint16_t irqmask) |
{ |
unsigned int i; |
int pin; |
io_redirection_reg_t reg; |
for (i = 0;i < 16; i++) { |
if (irqmask & (1 << i)) { |
/* |
* Unmask the signal input in IO APIC if there is a |
* mapping for the respective IRQ number. |
*/ |
pin = smp_irq_to_pin(i); |
if (pin != -1) { |
reg.lo = io_apic_read(IOREDTBL + pin * 2); |
reg.masked = false; |
io_apic_write(IOREDTBL + pin * 2, reg.lo); |
} |
} |
} |
} |
#endif /* CONFIG_SMP */ |
/** @} |
*/ |
/branches/rcu/kernel/arch/ia32/src/interrupt.c |
---|
1,239 → 1,248 |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <syscall/syscall.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <arch/drivers/i8259.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <ipc/sysipc.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(istate_t *istate) |
{ |
char *symbol = get_symtab_entry(istate->eip); |
if (!symbol) |
symbol = ""; |
if (CPU) |
printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id); |
else |
printf("----------------EXCEPTION OCCURED----------------\n"); |
printf("%%eip: %#x (%s)\n",istate->eip,symbol); |
printf("ERROR_WORD=%#x\n", istate->error_word); |
printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags); |
printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx); |
#endif |
printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); |
printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(istate); |
panic("unserviced interrupt: %d\n", n); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(istate); |
panic("stack fault\n"); |
} |
static void simd_fp_exception(int n, istate_t *istate) |
{ |
uint32_t mxcsr; |
asm ( |
"stmxcsr %0;\n" |
:"=m"(mxcsr) |
); |
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
(unative_t)mxcsr); |
decode_istate(istate); |
printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
panic("SIMD FP exception(19)\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
#ifdef CONFIG_SMP |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
#endif |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32interrupt |
* @{ |
*/ |
/** @file |
*/ |
#include <arch/interrupt.h> |
#include <syscall/syscall.h> |
#include <print.h> |
#include <debug.h> |
#include <panic.h> |
#include <arch/drivers/i8259.h> |
#include <func.h> |
#include <cpu.h> |
#include <arch/asm.h> |
#include <mm/tlb.h> |
#include <mm/as.h> |
#include <arch.h> |
#include <symtab.h> |
#include <proc/thread.h> |
#include <proc/task.h> |
#include <synch/spinlock.h> |
#include <arch/ddi/ddi.h> |
#include <ipc/sysipc.h> |
#include <interrupt.h> |
#include <ddi/irq.h> |
/* |
* Interrupt and exception dispatching. |
*/ |
void (* disable_irqs_function)(uint16_t irqmask) = NULL; |
void (* enable_irqs_function)(uint16_t irqmask) = NULL; |
void (* eoi_function)(void) = NULL; |
void decode_istate(istate_t *istate) |
{ |
char *symbol = get_symtab_entry(istate->eip); |
if (!symbol) |
symbol = ""; |
if (CPU) |
printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id); |
else |
printf("----------------EXCEPTION OCCURED----------------\n"); |
printf("%%eip: %#x (%s)\n",istate->eip,symbol); |
printf("ERROR_WORD=%#x\n", istate->error_word); |
printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags); |
printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx); |
#endif |
printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); |
printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); |
} |
static void trap_virtual_eoi(void) |
{ |
if (eoi_function) |
eoi_function(); |
else |
panic("no eoi_function\n"); |
} |
static void null_interrupt(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "unserviced interrupt: %d", n); |
decode_istate(istate); |
panic("unserviced interrupt: %d\n", n); |
} |
/** General Protection Fault. */ |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
spinlock_unlock(&TASK->lock); |
if (CPU->arch.iomapver_copy != ver) { |
/* |
* This fault can be caused by an early access |
* to I/O port because of an out-dated |
* I/O Permission bitmap installed on CPU. |
* Install the fresh copy and restart |
* the instruction. |
*/ |
io_perm_bitmap_install(); |
return; |
} |
fault_if_from_uspace(istate, "general protection fault"); |
} |
decode_istate(istate); |
panic("general protection fault\n"); |
} |
static void ss_fault(int n, istate_t *istate) |
{ |
fault_if_from_uspace(istate, "stack fault"); |
decode_istate(istate); |
panic("stack fault\n"); |
} |
static void simd_fp_exception(int n, istate_t *istate) |
{ |
uint32_t mxcsr; |
asm ( |
"stmxcsr %0;\n" |
:"=m"(mxcsr) |
); |
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", |
(unative_t)mxcsr); |
decode_istate(istate); |
printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); |
panic("SIMD FP exception(19)\n"); |
} |
static void nm_fault(int n, istate_t *istate) |
{ |
#ifdef CONFIG_FPU_LAZY |
scheduler_fpu_lazy_request(); |
#else |
fault_if_from_uspace(istate, "fpu fault"); |
panic("fpu fault"); |
#endif |
} |
#ifdef CONFIG_SMP |
static void tlb_shootdown_ipi(int n, istate_t *istate) |
{ |
trap_virtual_eoi(); |
tlb_shootdown_ipi_recv(); |
} |
#endif |
/** Handler of IRQ exceptions */ |
static void irq_interrupt(int n, istate_t *istate) |
{ |
ASSERT(n >= IVT_IRQBASE); |
int inum = n - IVT_IRQBASE; |
bool ack = false; |
ASSERT(inum < IRQ_COUNT); |
ASSERT((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); |
irq_t *irq = irq_dispatch_and_lock(inum); |
if (irq) { |
/* |
* The IRQ handler was found. |
*/ |
if (irq->preack) { |
/* Send EOI before processing the interrupt */ |
trap_virtual_eoi(); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
spinlock_unlock(&irq->lock); |
} else { |
/* |
* Spurious interrupt. |
*/ |
#ifdef CONFIG_DEBUG |
printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, inum); |
#endif |
} |
if (!ack) |
trap_virtual_eoi(); |
} |
void interrupt_init(void) |
{ |
int i; |
for (i = 0; i < IVT_ITEMS; i++) |
exc_register(i, "null", (iroutine) null_interrupt); |
for (i = 0; i < IRQ_COUNT; i++) { |
if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) |
exc_register(IVT_IRQBASE + i, "irq", (iroutine) irq_interrupt); |
} |
exc_register(7, "nm_fault", (iroutine) nm_fault); |
exc_register(12, "ss_fault", (iroutine) ss_fault); |
exc_register(13, "gp_fault", (iroutine) gp_fault); |
exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
#ifdef CONFIG_SMP |
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", (iroutine) tlb_shootdown_ipi); |
#endif |
} |
void trap_virtual_enable_irqs(uint16_t irqmask) |
{ |
if (enable_irqs_function) |
enable_irqs_function(irqmask); |
else |
panic("no enable_irqs_function\n"); |
} |
void trap_virtual_disable_irqs(uint16_t irqmask) |
{ |
if (disable_irqs_function) |
disable_irqs_function(irqmask); |
else |
panic("no disable_irqs_function\n"); |
} |
/** @} |
*/ |
/branches/rcu/kernel/arch/ia32/src/drivers/i8254.c |
---|
1,161 → 1,162 |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32 |
* @{ |
*/ |
/** |
* @file |
* @brief i8254 chip driver. |
* |
* Low level time functions. |
*/ |
#include <arch/types.h> |
#include <time/clock.h> |
#include <time/delay.h> |
#include <arch/cycle.h> |
#include <arch/interrupt.h> |
#include <arch/drivers/i8259.h> |
#include <arch/drivers/i8254.h> |
#include <cpu.h> |
#include <config.h> |
#include <arch/pm.h> |
#include <arch/asm.h> |
#include <arch/cpuid.h> |
#include <arch.h> |
#include <time/delay.h> |
#include <ddi/irq.h> |
#include <ddi/device.h> |
#define CLK_PORT1 0x40 |
#define CLK_PORT4 0x43 |
#define CLK_CONST 1193180 |
#define MAGIC_NUMBER 1194 |
static irq_t i8254_irq; |
static irq_ownership_t i8254_claim(void) |
{ |
return IRQ_ACCEPT; |
} |
static void i8254_irq_handler(irq_t *irq, void *arg, ...) |
{ |
/* |
* This IRQ is responsible for kernel preemption. |
* Nevertheless, we are now holding a spinlock which prevents |
* preemption. For this particular IRQ, we don't need the |
* lock. We just release it, call clock() and then reacquire it again. |
*/ |
spinlock_unlock(&irq->lock); |
clock(); |
spinlock_lock(&irq->lock); |
} |
void i8254_init(void) |
{ |
irq_initialize(&i8254_irq); |
i8254_irq.devno = device_assign_devno(); |
i8254_irq.inr = IRQ_CLK; |
i8254_irq.claim = i8254_claim; |
i8254_irq.handler = i8254_irq_handler; |
irq_register(&i8254_irq); |
i8254_normal_operation(); |
} |
void i8254_normal_operation(void) |
{ |
outb(CLK_PORT4, 0x36); |
pic_disable_irqs(1 << IRQ_CLK); |
outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
pic_enable_irqs(1 << IRQ_CLK); |
} |
#define LOOPS 150000 |
#define SHIFT 11 |
void i8254_calibrate_delay_loop(void) |
{ |
uint64_t clk1, clk2; |
uint32_t t1, t2, o1, o2; |
uint8_t not_ok; |
/* |
* One-shot timer. Count-down from 0xffff at 1193180Hz |
* MAGIC_NUMBER is the magic value for 1ms. |
*/ |
outb(CLK_PORT4, 0x30); |
outb(CLK_PORT1, 0xff); |
outb(CLK_PORT1, 0xff); |
do { |
/* will read both status and count */ |
outb(CLK_PORT4, 0xc2); |
not_ok = (inb(CLK_PORT1)>>6)&1; |
t1 = inb(CLK_PORT1); |
t1 |= inb(CLK_PORT1) << 8; |
} while (not_ok); |
asm_delay_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
t2 = inb(CLK_PORT1); |
t2 |= inb(CLK_PORT1) << 8; |
/* |
* We want to determine the overhead of the calibrating mechanism. |
*/ |
outb(CLK_PORT4, 0xd2); |
o1 = inb(CLK_PORT1); |
o1 |= inb(CLK_PORT1) << 8; |
asm_fake_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
o2 = inb(CLK_PORT1); |
o2 |= inb(CLK_PORT1) << 8; |
CPU->delay_loop_const = |
((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |
(((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); |
clk1 = get_cycle(); |
delay(1 << SHIFT); |
clk2 = get_cycle(); |
CPU->frequency_mhz = (clk2 - clk1) >> SHIFT; |
return; |
} |
/** @} |
*/ |
/* |
* Copyright (c) 2001-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup ia32 |
* @{ |
*/ |
/** |
* @file |
* @brief i8254 chip driver. |
* |
* Low level time functions. |
*/ |
#include <arch/types.h> |
#include <time/clock.h> |
#include <time/delay.h> |
#include <arch/cycle.h> |
#include <arch/interrupt.h> |
#include <arch/drivers/i8259.h> |
#include <arch/drivers/i8254.h> |
#include <cpu.h> |
#include <config.h> |
#include <arch/pm.h> |
#include <arch/asm.h> |
#include <arch/cpuid.h> |
#include <arch.h> |
#include <time/delay.h> |
#include <ddi/irq.h> |
#include <ddi/device.h> |
#define CLK_PORT1 0x40 |
#define CLK_PORT4 0x43 |
#define CLK_CONST 1193180 |
#define MAGIC_NUMBER 1194 |
static irq_t i8254_irq; |
static irq_ownership_t i8254_claim(void) |
{ |
return IRQ_ACCEPT; |
} |
static void i8254_irq_handler(irq_t *irq, void *arg, ...) |
{ |
/* |
* This IRQ is responsible for kernel preemption. |
* Nevertheless, we are now holding a spinlock which prevents |
* preemption. For this particular IRQ, we don't need the |
* lock. We just release it, call clock() and then reacquire it again. |
*/ |
spinlock_unlock(&irq->lock); |
clock(); |
spinlock_lock(&irq->lock); |
} |
void i8254_init(void) |
{ |
irq_initialize(&i8254_irq); |
i8254_irq.preack = true; |
i8254_irq.devno = device_assign_devno(); |
i8254_irq.inr = IRQ_CLK; |
i8254_irq.claim = i8254_claim; |
i8254_irq.handler = i8254_irq_handler; |
irq_register(&i8254_irq); |
i8254_normal_operation(); |
} |
void i8254_normal_operation(void) |
{ |
outb(CLK_PORT4, 0x36); |
pic_disable_irqs(1 << IRQ_CLK); |
outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
pic_enable_irqs(1 << IRQ_CLK); |
} |
#define LOOPS 150000 |
#define SHIFT 11 |
void i8254_calibrate_delay_loop(void) |
{ |
uint64_t clk1, clk2; |
uint32_t t1, t2, o1, o2; |
uint8_t not_ok; |
/* |
* One-shot timer. Count-down from 0xffff at 1193180Hz |
* MAGIC_NUMBER is the magic value for 1ms. |
*/ |
outb(CLK_PORT4, 0x30); |
outb(CLK_PORT1, 0xff); |
outb(CLK_PORT1, 0xff); |
do { |
/* will read both status and count */ |
outb(CLK_PORT4, 0xc2); |
not_ok = (inb(CLK_PORT1)>>6)&1; |
t1 = inb(CLK_PORT1); |
t1 |= inb(CLK_PORT1) << 8; |
} while (not_ok); |
asm_delay_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
t2 = inb(CLK_PORT1); |
t2 |= inb(CLK_PORT1) << 8; |
/* |
* We want to determine the overhead of the calibrating mechanism. |
*/ |
outb(CLK_PORT4, 0xd2); |
o1 = inb(CLK_PORT1); |
o1 |= inb(CLK_PORT1) << 8; |
asm_fake_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
o2 = inb(CLK_PORT1); |
o2 |= inb(CLK_PORT1) << 8; |
CPU->delay_loop_const = |
((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |
(((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); |
clk1 = get_cycle(); |
delay(1 << SHIFT); |
clk2 = get_cycle(); |
CPU->frequency_mhz = (clk2 - clk1) >> SHIFT; |
return; |
} |
/** @} |
*/ |