/branches/network/kernel/arch/sparc64/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/sparc64/include/types.h |
---|
46,8 → 46,6 |
typedef unsigned long uint64_t; |
typedef uint64_t size_t; |
typedef uint64_t count_t; |
typedef uint64_t index_t; |
typedef uint64_t uintptr_t; |
typedef uint64_t pfn_t; |
60,11 → 58,9 |
typedef struct { |
} fncptr_t; |
/**< Formats for uintptr_t, size_t, count_t and index_t */ |
/**< Formats for uintptr_t, size_t */ |
#define PRIp "llx" |
#define PRIs "llu" |
#define PRIc "llu" |
#define PRIi "llu" |
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ |
#define PRId8 "d" |
/branches/network/kernel/arch/sparc64/include/mm/tlb.h |
---|
322,7 → 322,7 |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(index_t entry) |
static inline uint64_t itlb_data_access_read(size_t entry) |
{ |
itlb_data_access_addr_t reg; |
336,7 → 336,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void itlb_data_access_write(index_t entry, uint64_t value) |
static inline void itlb_data_access_write(size_t entry, uint64_t value) |
{ |
itlb_data_access_addr_t reg; |
353,7 → 353,7 |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(index_t entry) |
static inline uint64_t dtlb_data_access_read(size_t entry) |
{ |
dtlb_data_access_addr_t reg; |
367,7 → 367,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
static inline void dtlb_data_access_write(size_t entry, uint64_t value) |
{ |
dtlb_data_access_addr_t reg; |
383,7 → 383,7 |
* |
* @return Current value of specified IMMU TLB Tag Read Register. |
*/ |
static inline uint64_t itlb_tag_read_read(index_t entry) |
static inline uint64_t itlb_tag_read_read(size_t entry) |
{ |
itlb_tag_read_addr_t tag; |
398,7 → 398,7 |
* |
* @return Current value of specified DMMU TLB Tag Read Register. |
*/ |
static inline uint64_t dtlb_tag_read_read(index_t entry) |
static inline uint64_t dtlb_tag_read_read(size_t entry) |
{ |
dtlb_tag_read_addr_t tag; |
418,7 → 418,7 |
* @return Current value of specified IMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
static inline uint64_t itlb_data_access_read(int tlb, size_t entry) |
{ |
itlb_data_access_addr_t reg; |
433,7 → 433,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void itlb_data_access_write(int tlb, index_t entry, |
static inline void itlb_data_access_write(int tlb, size_t entry, |
uint64_t value) |
{ |
itlb_data_access_addr_t reg; |
453,7 → 453,7 |
* @return Current value of specified DMMU TLB Data Access |
* Register. |
*/ |
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) |
{ |
dtlb_data_access_addr_t reg; |
469,7 → 469,7 |
* @param entry TLB Entry index. |
* @param value Value to be written. |
*/ |
static inline void dtlb_data_access_write(int tlb, index_t entry, |
static inline void dtlb_data_access_write(int tlb, size_t entry, |
uint64_t value) |
{ |
dtlb_data_access_addr_t reg; |
488,7 → 488,7 |
* |
* @return Current value of specified IMMU TLB Tag Read Register. |
*/ |
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) |
{ |
itlb_tag_read_addr_t tag; |
505,7 → 505,7 |
* |
* @return Current value of specified DMMU TLB Tag Read Register. |
*/ |
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) |
{ |
dtlb_tag_read_addr_t tag; |
/branches/network/kernel/arch/sparc64/include/mm/tsb.h |
---|
160,9 → 160,9 |
struct as; |
struct pte; |
extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
extern void itsb_pte_copy(struct pte *t, index_t index); |
extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages); |
extern void itsb_pte_copy(struct pte *t, size_t index); |
extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro); |
#endif /* !def __ASM__ */ |
/branches/network/kernel/arch/sparc64/Makefile.inc |
---|
40,7 → 40,8 |
LFLAGS += -no-check-sections -N |
DEFS += -D__64_BITS__ |
BITS = 64 |
ENDIANESS = BE |
ifeq ($(PROCESSOR),us) |
DEFS += -DUS |
/branches/network/kernel/arch/sparc64/src/smp/smp.c |
---|
61,7 → 61,7 |
void smp_init(void) |
{ |
ofw_tree_node_t *node; |
count_t cnt = 0; |
size_t cnt = 0; |
if (is_us() || is_us_iii()) { |
node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu"); |
/branches/network/kernel/arch/sparc64/src/mm/tlb.c |
---|
54,8 → 54,8 |
#include <arch/mm/tsb.h> |
#endif |
static void dtlb_pte_copy(pte_t *, index_t, bool); |
static void itlb_pte_copy(pte_t *, index_t); |
static void dtlb_pte_copy(pte_t *, size_t, bool); |
static void itlb_pte_copy(pte_t *, size_t); |
static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); |
static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, |
const char *); |
130,7 → 130,7 |
* @param ro If true, the entry will be created read-only, regardless |
* of its w field. |
*/ |
void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
void dtlb_pte_copy(pte_t *t, size_t index, bool ro) |
{ |
tlb_tag_access_reg_t tag; |
tlb_data_t data; |
167,7 → 167,7 |
* @param t Page Table Entry to be copied. |
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
*/ |
void itlb_pte_copy(pte_t *t, index_t index) |
void itlb_pte_copy(pte_t *t, size_t index) |
{ |
tlb_tag_access_reg_t tag; |
tlb_data_t data; |
200,7 → 200,7 |
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
{ |
uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
pte_t *t; |
page_table_lock(AS, true); |
245,7 → 245,7 |
{ |
uintptr_t page_8k; |
uintptr_t page_16k; |
index_t index; |
size_t index; |
pte_t *t; |
page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH; |
309,7 → 309,7 |
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
{ |
uintptr_t page_16k; |
index_t index; |
size_t index; |
pte_t *t; |
page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
497,38 → 497,7 |
dtlb_sfsr_write(0); |
} |
#if defined (US3) |
/** Invalidates given TLB entry if and only if it is non-locked or global. |
* |
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1, |
* TLB_ISMALL, TLB_IBIG). |
* @param entry Entry index within the given TLB. |
*/ |
static void tlb_invalidate_entry(int tlb, index_t entry) |
{ |
tlb_data_t d; |
tlb_tag_read_reg_t t; |
if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) { |
d.value = dtlb_data_access_read(tlb, entry); |
if (!d.l || d.g) { |
t.value = dtlb_tag_read_read(tlb, entry); |
d.v = false; |
dtlb_tag_access_write(t.value); |
dtlb_data_access_write(tlb, entry, d.value); |
} |
} else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) { |
d.value = itlb_data_access_read(tlb, entry); |
if (!d.l || d.g) { |
t.value = itlb_tag_read_read(tlb, entry); |
d.v = false; |
itlb_tag_access_write(t.value); |
itlb_data_access_write(tlb, entry, d.value); |
} |
} |
} |
#endif |
#if defined (US) |
/** Invalidate all unlocked ITLB and DTLB entries. */ |
void tlb_invalidate_all(void) |
{ |
543,7 → 512,6 |
* be safe to invalidate them as late as now. |
*/ |
#if defined (US) |
tlb_data_t d; |
tlb_tag_read_reg_t t; |
567,22 → 535,19 |
} |
} |
} |
#elif defined (US3) |
for (i = 0; i < tlb_ismall_size(); i++) |
tlb_invalidate_entry(TLB_ISMALL, i); |
for (i = 0; i < tlb_ibig_size(); i++) |
tlb_invalidate_entry(TLB_IBIG, i); |
for (i = 0; i < tlb_dsmall_size(); i++) |
tlb_invalidate_entry(TLB_DSMALL, i); |
for (i = 0; i < tlb_dbig_size(); i++) |
tlb_invalidate_entry(TLB_DBIG_0, i); |
for (i = 0; i < tlb_dbig_size(); i++) |
tlb_invalidate_entry(TLB_DBIG_1, i); |
/** Invalidate all unlocked ITLB and DTLB entries. */ |
void tlb_invalidate_all(void) |
{ |
itlb_demap(TLB_DEMAP_ALL, 0, 0); |
dtlb_demap(TLB_DEMAP_ALL, 0, 0); |
} |
#endif |
} |
/** Invalidate all ITLB and DTLB entries that belong to specified ASID |
* (Context). |
* |
614,7 → 579,7 |
* @param page First page which to sweep out from ITLB and DTLB. |
* @param cnt Number of ITLB and DTLB entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) |
{ |
unsigned int i; |
tlb_context_reg_t pc_save, ctx; |
/branches/network/kernel/arch/sparc64/src/mm/as.c |
---|
89,7 → 89,7 |
* The count must be calculated with respect to the emualted 16K page |
* size. |
*/ |
count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
return cnt; |
101,7 → 101,7 |
int as_create_arch(as_t *as, int flags) |
{ |
#ifdef CONFIG_TSB |
tsb_invalidate(as, 0, (count_t) -1); |
tsb_invalidate(as, 0, (size_t) -1); |
#endif |
return 0; |
} |
/branches/network/kernel/arch/sparc64/src/mm/tsb.c |
---|
50,13 → 50,14 |
* |
* @param as Address space. |
* @param page First page to invalidate in TSB. |
* @param pages Number of pages to invalidate. Value of (count_t) -1 means the |
* @param pages Number of pages to invalidate. Value of (size_t) -1 means the |
* whole TSB. |
*/ |
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
void tsb_invalidate(as_t *as, uintptr_t page, size_t pages) |
{ |
index_t i0, i; |
count_t cnt; |
size_t i0; |
size_t i; |
size_t cnt; |
ASSERT(as->arch.itsb && as->arch.dtsb); |
63,7 → 64,7 |
i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); |
if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) |
if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) |
cnt = ITSB_ENTRY_COUNT; |
else |
cnt = pages * 2; |
81,11 → 82,11 |
* @param t Software PTE. |
* @param index Zero if lower 8K-subpage, one if higher 8K subpage. |
*/ |
void itsb_pte_copy(pte_t *t, index_t index) |
void itsb_pte_copy(pte_t *t, size_t index) |
{ |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
size_t entry; |
ASSERT(index <= 1); |
127,11 → 128,11 |
* @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
* @param ro If true, the mapping is copied read-only. |
*/ |
void dtsb_pte_copy(pte_t *t, index_t index, bool ro) |
void dtsb_pte_copy(pte_t *t, size_t index, bool ro) |
{ |
as_t *as; |
tsb_entry_t *tsb; |
index_t entry; |
size_t entry; |
ASSERT(index <= 1); |
/branches/network/kernel/arch/sparc64/src/drivers/fhc.c |
---|
71,7 → 71,7 |
if (!prop || !prop->value) |
return NULL; |
count_t regs = prop->size / sizeof(ofw_central_reg_t); |
size_t regs = prop->size / sizeof(ofw_central_reg_t); |
if (regs + 1 < UART_IMAP_REG) |
return NULL; |
/branches/network/kernel/arch/sparc64/src/drivers/sgcn.c |
---|
279,7 → 279,7 |
*/ |
void sgcn_grab(void) |
{ |
kbd_disabled = true; |
kbd_disabled = false; |
} |
/** |
344,16 → 344,17 |
sgcn_instance_t *instance = |
malloc(sizeof(sgcn_instance_t), FRAME_ATOMIC); |
if (!instance) |
return NULL; |
if (instance) { |
instance->srlnin = NULL; |
instance->thread = thread_create(ksgcnpoll, instance, TASK, 0, |
"ksgcnpoll", true); |
if (!instance->thread) { |
free(instance); |
return NULL; |
} |
} |
return instance; |
} |
/branches/network/kernel/arch/sparc64/src/drivers/pci.c |
---|
91,7 → 91,7 |
return NULL; |
ofw_upa_reg_t *reg = prop->value; |
count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
size_t regs = prop->size / sizeof(ofw_upa_reg_t); |
if (regs < SABRE_INTERNAL_REG + 1) |
return NULL; |
138,7 → 138,7 |
return NULL; |
ofw_upa_reg_t *reg = prop->value; |
count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
size_t regs = prop->size / sizeof(ofw_upa_reg_t); |
if (regs < PSYCHO_INTERNAL_REG + 1) |
return NULL; |
/branches/network/kernel/arch/ia64/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/ia64/include/types.h |
---|
54,8 → 54,6 |
} uint128_t; |
typedef uint64_t size_t; |
typedef uint64_t count_t; |
typedef uint64_t index_t; |
typedef uint64_t uintptr_t; |
typedef uint64_t pfn_t; |
72,8 → 70,6 |
#define PRIp "lx" /**< Format for uintptr_t. */ |
#define PRIs "lu" /**< Format for size_t. */ |
#define PRIc "lu" /**< Format for count_t. */ |
#define PRIi "lu" /**< Format for index_t. */ |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
/branches/network/kernel/arch/ia64/include/mm/page.h |
---|
240,7 → 240,7 |
* |
* @return Current contents of rr[i]. |
*/ |
static inline uint64_t rr_read(index_t i) |
static inline uint64_t rr_read(size_t i) |
{ |
uint64_t ret; |
ASSERT(i < REGION_REGISTERS); |
253,7 → 253,7 |
* @param i Region register index. |
* @param v Value to be written to rr[i]. |
*/ |
static inline void rr_write(index_t i, uint64_t v) |
static inline void rr_write(size_t i, uint64_t v) |
{ |
ASSERT(i < REGION_REGISTERS); |
asm volatile ( |
/branches/network/kernel/arch/ia64/include/mm/tlb.h |
---|
76,12 → 76,12 |
extern void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry); |
extern void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry); |
extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr); |
extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr); |
extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr); |
extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, size_t tr); |
extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr); |
extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr); |
extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr); |
extern void dtr_purge(uintptr_t page, count_t width); |
extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, size_t tr); |
extern void dtr_purge(uintptr_t page, size_t width); |
extern void dtc_pte_copy(pte_t *t); |
extern void itc_pte_copy(pte_t *t); |
/branches/network/kernel/arch/ia64/Makefile.inc |
---|
41,7 → 41,8 |
LFLAGS += -EL |
AFLAGS += -mconstant-gp |
DEFS += -D__64_BITS__ |
BITS = 64 |
ENDIANESS = LE |
ARCH_SOURCES = \ |
arch/$(KARCH)/src/start.S \ |
/branches/network/kernel/arch/ia64/src/mm/tlb.c |
---|
100,7 → 100,7 |
} |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) |
{ |
region_register rr; |
bool restore_rr = false; |
267,7 → 267,7 |
* @param tr Translation register. |
*/ |
void |
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr) |
{ |
tr_mapping_insert(va, asid, entry, false, tr); |
} |
281,7 → 281,7 |
* @param tr Translation register. |
*/ |
void |
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr) |
{ |
tr_mapping_insert(va, asid, entry, true, tr); |
} |
298,7 → 298,7 |
*/ |
void |
tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, |
index_t tr) |
size_t tr) |
{ |
region_register rr; |
bool restore_rr = false; |
353,7 → 353,7 |
*/ |
void |
dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, |
index_t tr) |
size_t tr) |
{ |
tlb_entry_t entry; |
382,7 → 382,7 |
* @param page Virtual page address including VRN bits. |
* @param width Width of the purge in bits. |
*/ |
void dtr_purge(uintptr_t page, count_t width) |
void dtr_purge(uintptr_t page, size_t width) |
{ |
asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2)); |
} |
/branches/network/kernel/arch/ia64/src/mm/vhpt.c |
---|
53,7 → 53,7 |
void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
{ |
region_register rr_save, rr; |
index_t vrn; |
size_t vrn; |
rid_t rid; |
uint64_t tag; |
/branches/network/kernel/arch/ia64/src/mm/page.c |
---|
131,7 → 131,7 |
vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid) |
{ |
region_register rr_save, rr; |
index_t vrn; |
size_t vrn; |
rid_t rid; |
vhpt_entry_t *v; |
176,7 → 176,7 |
bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v) |
{ |
region_register rr_save, rr; |
index_t vrn; |
size_t vrn; |
rid_t rid; |
bool match; |
223,7 → 223,7 |
int flags) |
{ |
region_register rr_save, rr; |
index_t vrn; |
size_t vrn; |
rid_t rid; |
uint64_t tag; |
/branches/network/kernel/arch/ia64/src/drivers/ski.c |
---|
44,12 → 44,18 |
#include <string.h> |
#include <arch.h> |
#define POLL_INTERVAL 10000 /* 10 ms */ |
enum { |
/** Interval between polling in microseconds */ |
POLL_INTERVAL = 10000, /* 0.01 s */ |
#define SKI_INIT_CONSOLE 20 |
#define SKI_GETCHAR 21 |
#define SKI_PUTCHAR 31 |
/** Max. number of characters to pull out at a time */ |
POLL_LIMIT = 30, |
SKI_INIT_CONSOLE = 20, |
SKI_GETCHAR = 21, |
SKI_PUTCHAR = 31 |
}; |
static void ski_putchar(outdev_t *, const wchar_t, bool); |
static outdev_operations_t skiout_ops = { |
154,17 → 160,30 |
return (wchar_t) ch; |
} |
/** Ask keyboard if a key was pressed. */ |
/** Ask keyboard if a key was pressed. |
* |
* If so, it will repeat and pull up to POLL_LIMIT characters. |
*/ |
static void poll_keyboard(ski_instance_t *instance) |
{ |
wchar_t ch; |
int count; |
if (kbd_disabled) |
return; |
wchar_t ch = ski_getchar(); |
count = POLL_LIMIT; |
if (ch != 0) |
while (count > 0) { |
ch = ski_getchar(); |
if (ch == '\0') |
break; |
indev_push_character(instance->srlnin, ch); |
--count; |
} |
} |
/** Kernel thread for polling keyboard. */ |
static void kskipoll(void *arg) |
215,12 → 234,12 |
void ski_kbd_grab(void) |
{ |
kbd_disabled = true; |
kbd_disabled = false; |
} |
void ski_kbd_release(void) |
{ |
kbd_disabled = false; |
kbd_disabled = true; |
} |
/** @} |
/branches/network/kernel/arch/arm32/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/arm32/include/types.h |
---|
53,8 → 53,6 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
69,8 → 67,6 |
#define PRIp "x" /**< Format for uintptr_t. */ |
#define PRIs "u" /**< Format for size_t. */ |
#define PRIc "u" /**< Format for count_t. */ |
#define PRIi "u" /**< Format for index_t. */ |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
/branches/network/kernel/arch/arm32/include/mm/page.h |
---|
94,21 → 94,21 |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x)) |
/* Macros for querying the last-level PTE entries. */ |
#define PTE_VALID_ARCH(pte) \ |
204,7 → 204,7 |
* @param pt Level 0 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i) |
{ |
pte_level0_t *p = &pt[i]; |
int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
219,7 → 219,7 |
* @param pt Level 1 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i) |
{ |
pte_level1_t *p = &pt[i]; |
244,7 → 244,7 |
* @param i index of the entry to be changed |
* @param flags new flags |
*/ |
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags) |
{ |
pte_level0_t *p = &pt[i]; |
272,7 → 272,7 |
* @param i Index of the entry to be changed. |
* @param flags New flags. |
*/ |
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags) |
{ |
pte_level1_t *p = &pt[i]; |
/branches/network/kernel/arch/arm32/Makefile.inc |
---|
39,7 → 39,8 |
GCC_CFLAGS += -fno-zero-initialized-in-bss |
DEFS += -D__32_BITS__ |
BITS = 32 |
ENDIANESS = LE |
ARCH_SOURCES = \ |
arch/$(KARCH)/src/start.S \ |
/branches/network/kernel/arch/arm32/src/mm/tlb.c |
---|
80,7 → 80,7 |
* @param page Address of the first page whose entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt) |
{ |
unsigned int i; |
/branches/network/kernel/arch/ppc32/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/ppc32/include/types.h |
---|
46,8 → 46,6 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
60,11 → 58,9 |
typedef struct { |
} fncptr_t; |
/**< Formats for uintptr_t, size_t, count_t and index_t */ |
/**< Formats for uintptr_t, size_t */ |
#define PRIp "x" |
#define PRIs "u" |
#define PRIc "u" |
#define PRIi "u" |
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ |
#define PRId8 "d" |
/branches/network/kernel/arch/ppc32/include/mm/page.h |
---|
102,21 → 102,21 |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl3), (size_t) (i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) |
/* Macros for querying the last-level PTEs. */ |
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
130,7 → 130,7 |
#include <mm/mm.h> |
#include <arch/interrupt.h> |
static inline int get_pt_flags(pte_t *pt, index_t i) |
static inline int get_pt_flags(pte_t *pt, size_t i) |
{ |
pte_t *p = &pt[i]; |
143,7 → 143,7 |
(p->global << PAGE_GLOBAL_SHIFT)); |
} |
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
static inline void set_pt_flags(pte_t *pt, size_t i, int flags) |
{ |
pte_t *p = &pt[i]; |
/branches/network/kernel/arch/ppc32/Makefile.inc |
---|
39,7 → 39,8 |
AFLAGS += -a32 |
LFLAGS += -no-check-sections -N |
DEFS += -D__32_BITS__ |
BITS = 32 |
ENDIANESS = BE |
ARCH_SOURCES = \ |
arch/$(KARCH)/src/context.S \ |
/branches/network/kernel/arch/ppc32/src/mm/tlb.c |
---|
549,7 → 549,7 |
} |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) |
{ |
// TODO |
tlb_invalidate_all(); |
/branches/network/kernel/arch/ppc32/src/mm/frame.c |
---|
57,7 → 57,7 |
void frame_arch_init(void) |
{ |
pfn_t minconf = 2; |
count_t i; |
size_t i; |
pfn_t start, conf; |
size_t size; |
/branches/network/kernel/arch/amd64/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/amd64/include/types.h |
---|
46,8 → 46,6 |
typedef unsigned long long uint64_t; |
typedef uint64_t size_t; |
typedef uint64_t count_t; |
typedef uint64_t index_t; |
typedef uint64_t uintptr_t; |
typedef uint64_t pfn_t; |
60,11 → 58,9 |
typedef struct { |
} fncptr_t; |
/**< Formats for uintptr_t, size_t, count_t and index_t */ |
/**< Formats for uintptr_t, size_t */ |
#define PRIp "llx" |
#define PRIs "llu" |
#define PRIc "llu" |
#define PRIi "llu" |
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ |
#define PRId8 "d" |
/branches/network/kernel/arch/amd64/include/atomic.h |
---|
115,9 → 115,7 |
preemption_disable(); |
asm volatile ( |
"0:\n" |
#ifdef CONFIG_HT |
"pause\n" |
#endif |
"mov %[count], %[tmp]\n" |
"testq %[tmp], %[tmp]\n" |
"jnz 0b\n" /* lightweight looping on locked spinlock */ |
/branches/network/kernel/arch/amd64/include/proc/task.h |
---|
40,7 → 40,7 |
typedef struct { |
/** I/O Permission bitmap Generation counter. */ |
count_t iomapver; |
size_t iomapver; |
/** I/O Permission bitmap. */ |
bitmap_t iomap; |
} task_arch_t; |
/branches/network/kernel/arch/amd64/include/mm/page.h |
---|
112,33 → 112,33 |
#define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
(write_cr3((uintptr_t) (ptl0))) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
set_pt_addr((pte_t *) (ptl0), (index_t) (i), a) |
set_pt_addr((pte_t *) (ptl0), (size_t) (i), a) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) \ |
set_pt_addr((pte_t *) (ptl1), (index_t) (i), a) |
set_pt_addr((pte_t *) (ptl1), (size_t) (i), a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) \ |
set_pt_addr((pte_t *) (ptl2), (index_t) (i), a) |
set_pt_addr((pte_t *) (ptl2), (size_t) (i), a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
set_pt_addr((pte_t *) (ptl3), (index_t) (i), a) |
set_pt_addr((pte_t *) (ptl3), (size_t) (i), a) |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
get_pt_flags((pte_t *) (ptl1), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl1), (size_t) (i)) |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
get_pt_flags((pte_t *) (ptl2), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl2), (size_t) (i)) |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl3), (size_t) (i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) \ |
set_pt_flags((pte_t *) (ptl1), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl1), (size_t) (i), (x)) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) \ |
set_pt_flags((pte_t *) (ptl2), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl2), (size_t) (i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) |
/* Macros for querying the last-level PTE entries. */ |
#define PTE_VALID_ARCH(p) \ |
176,7 → 176,7 |
*/ |
#define PFERR_CODE_ID (1 << 4) |
static inline int get_pt_flags(pte_t *pt, index_t i) |
static inline int get_pt_flags(pte_t *pt, size_t i) |
{ |
pte_t *p = &pt[i]; |
189,7 → 189,7 |
p->global << PAGE_GLOBAL_SHIFT); |
} |
static inline void set_pt_addr(pte_t *pt, index_t i, uintptr_t a) |
static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) |
{ |
pte_t *p = &pt[i]; |
197,7 → 197,7 |
p->addr_32_51 = a >> 32; |
} |
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
static inline void set_pt_flags(pte_t *pt, size_t i, int flags) |
{ |
pte_t *p = &pt[i]; |
/branches/network/kernel/arch/amd64/include/cpu.h |
---|
64,7 → 64,7 |
int stepping; |
tss_t *tss; |
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ |
size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ |
} cpu_arch_t; |
struct star_msr { |
/branches/network/kernel/arch/amd64/Makefile.inc |
---|
41,7 → 41,8 |
ICC_CFLAGS += $(CMN1) |
SUNCC_CFLAGS += -m64 -xmodel=kernel |
DEFS += -D__64_BITS__ |
BITS = 64 |
ENDIANESS = LE |
## Accepted CPUs |
# |
/branches/network/kernel/arch/amd64/src/ddi/ddi.c |
---|
56,7 → 56,7 |
*/ |
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
{ |
count_t bits; |
size_t bits; |
bits = ioaddr + size; |
if (bits > IO_PORTS) |
98,7 → 98,7 |
/* |
* Enable the range and we are done. |
*/ |
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size); |
bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); |
/* |
* Increment I/O Permission bitmap generation counter. |
117,11 → 117,11 |
*/ |
void io_perm_bitmap_install(void) |
{ |
count_t bits; |
size_t bits; |
ptr_16_64_t cpugdtr; |
descriptor_t *gdt_p; |
tss_descriptor_t *tss_desc; |
count_t ver; |
size_t ver; |
/* First, copy the I/O Permission Bitmap. */ |
spinlock_lock(&TASK->lock); |
/branches/network/kernel/arch/amd64/src/interrupt.c |
---|
101,7 → 101,7 |
static void gp_fault(int n, istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
size_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
/branches/network/kernel/arch/mips32/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/mips32/include/types.h |
---|
46,8 → 46,6 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
62,8 → 60,6 |
#define PRIp "x" /**< Format for uintptr_t. */ |
#define PRIs "u" /**< Format for size_t. */ |
#define PRIc "u" /**< Format for count_t. */ |
#define PRIi "u" /**< Format for index_t. */ |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
/branches/network/kernel/arch/mips32/include/elf.h |
---|
37,7 → 37,7 |
#define ELF_MACHINE EM_MIPS |
#ifdef BIG_ENDIAN |
#ifdef __BE__ |
# define ELF_DATA_ENCODING ELFDATA2MSB |
#else |
# define ELF_DATA_ENCODING ELFDATA2LSB |
/branches/network/kernel/arch/mips32/include/arch.h |
---|
42,7 → 42,7 |
#include <typedefs.h> |
extern count_t cpu_count; |
extern size_t cpu_count; |
typedef struct { |
uintptr_t addr; |
/branches/network/kernel/arch/mips32/include/mm/page.h |
---|
112,21 → 112,21 |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl3), (size_t) (i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) |
/* Last-level info macros. */ |
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
140,7 → 140,7 |
#include <mm/mm.h> |
#include <arch/exception.h> |
static inline int get_pt_flags(pte_t *pt, index_t i) |
static inline int get_pt_flags(pte_t *pt, size_t i) |
{ |
pte_t *p = &pt[i]; |
153,7 → 153,7 |
(p->g << PAGE_GLOBAL_SHIFT)); |
} |
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
static inline void set_pt_flags(pte_t *pt, size_t i, int flags) |
{ |
pte_t *p = &pt[i]; |
/branches/network/kernel/arch/mips32/include/debugger.h |
---|
53,7 → 53,7 |
unative_t instruction; /**< Original instruction */ |
unative_t nextinstruction; /**< Original instruction following break */ |
int flags; /**< Flags regarding breakpoint */ |
count_t counter; |
size_t counter; |
void (*bkfunc)(void *b, istate_t *istate); |
} bpinfo_t; |
/branches/network/kernel/arch/mips32/Makefile.inc |
---|
36,7 → 36,7 |
GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 |
DEFS += -D__32_BITS__ |
BITS = 32 |
## Accepted MACHINEs |
# |
43,15 → 43,18 |
ifeq ($(MACHINE),lgxemul) |
BFD_NAME = elf32-tradlittlemips |
ENDIANESS = LE |
endif |
ifeq ($(MACHINE),bgxemul) |
BFD_NAME = elf32-tradbigmips |
TOOLCHAIN_DIR = $(CROSS_PREFIX)/mips |
TARGET = mips-linux-gnu |
GCC_CFLAGS += -DBIG_ENDIAN |
ENDIANESS = BE |
GCC_CFLAGS += -D__BE__ |
endif |
ifeq ($(MACHINE),msim) |
BFD_NAME = elf32-tradlittlemips |
ENDIANESS = LE |
GCC_CFLAGS += -mhard-float |
endif |
/branches/network/kernel/arch/mips32/src/mm/tlb.c |
---|
560,7 → 560,7 |
* @param page First page whose TLB entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) |
{ |
unsigned int i; |
ipl_t ipl; |
/branches/network/kernel/arch/mips32/src/mm/frame.c |
---|
62,7 → 62,7 |
pfn_t count; |
} phys_region_t; |
static count_t phys_regions_count = 0; |
static size_t phys_regions_count = 0; |
static phys_region_t phys_regions[MAX_REGIONS]; |
/** Check whether frame is available |
119,7 → 119,7 |
/* Init tasks */ |
bool safe = true; |
count_t i; |
size_t i; |
for (i = 0; i < init.cnt; i++) |
if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
KA2PA(init.tasks[i].addr), init.tasks[i].size)) { |
174,7 → 174,7 |
cp0_entry_lo1_write(0); |
cp0_entry_hi_write(0); |
count_t i; |
size_t i; |
for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
cp0_index_write(i); |
tlbwi(); |
251,7 → 251,7 |
printf("Base Size\n"); |
printf("---------- ----------\n"); |
count_t i; |
size_t i; |
for (i = 0; i < phys_regions_count; i++) { |
printf("%#010x %10u\n", |
PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count)); |
/branches/network/kernel/arch/mips32/src/mips32.c |
---|
76,7 → 76,7 |
/* Stack pointer saved when entering user mode */ |
uintptr_t supervisor_sp __attribute__ ((section (".text"))); |
count_t cpu_count = 0; |
size_t cpu_count = 0; |
/** Performs mips32-specific initialization before main_bsp() is called. */ |
void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo) |
84,7 → 84,7 |
/* Setup usermode */ |
init.cnt = bootinfo->cnt; |
count_t i; |
size_t i; |
for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) { |
init.tasks[i].addr = bootinfo->tasks[i].addr; |
init.tasks[i].size = bootinfo->tasks[i].size; |
/branches/network/kernel/arch/ia32/include/byteorder.h |
---|
File deleted |
/branches/network/kernel/arch/ia32/include/types.h |
---|
46,8 → 46,6 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
62,8 → 60,6 |
#define PRIp "x" /**< Format for uintptr_t. */ |
#define PRIs "u" /**< Format for size_t. */ |
#define PRIc "u" /**< Format for count_t. */ |
#define PRIi "u" /**< Format for index_t. */ |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
/branches/network/kernel/arch/ia32/include/smp/smp.h |
---|
39,10 → 39,10 |
/** SMP config opertaions interface. */ |
struct smp_config_operations { |
count_t (* cpu_count)(void); /**< Return number of detected processors. */ |
bool (* cpu_enabled)(index_t i); /**< Check whether the processor of index i is enabled. */ |
bool (*cpu_bootstrap)(index_t i); /**< Check whether the processor of index i is BSP. */ |
uint8_t (*cpu_apic_id)(index_t i); /**< Return APIC ID of the processor of index i. */ |
size_t (* cpu_count)(void); /**< Return number of detected processors. */ |
bool (* cpu_enabled)(size_t i); /**< Check whether the processor of index i is enabled. */ |
bool (*cpu_bootstrap)(size_t i); /**< Check whether the processor of index i is BSP. */ |
uint8_t (*cpu_apic_id)(size_t i); /**< Return APIC ID of the processor of index i. */ |
int (*irq_to_pin)(unsigned int irq); /**< Return mapping between irq and APIC pin. */ |
}; |
/branches/network/kernel/arch/ia32/include/atomic.h |
---|
114,9 → 114,7 |
preemption_disable(); |
asm volatile ( |
"0:\n" |
#ifdef CONFIG_HT |
"pause\n" /* Pentium 4's HT love this instruction */ |
#endif |
"mov %[count], %[tmp]\n" |
"testl %[tmp], %[tmp]\n" |
"jnz 0b\n" /* lightweight looping on locked spinlock */ |
/branches/network/kernel/arch/ia32/include/proc/task.h |
---|
40,7 → 40,7 |
typedef struct { |
/** I/O Permission bitmap Generation counter. */ |
count_t iomapver; |
size_t iomapver; |
/** I/O Permission bitmap. */ |
bitmap_t iomap; |
} task_arch_t; |
/branches/network/kernel/arch/ia32/include/mm/page.h |
---|
95,21 → 95,21 |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
get_pt_flags((pte_t *) (ptl3), (size_t) (i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) |
/* Macros for querying the last level entries. */ |
#define PTE_VALID_ARCH(p) \ |
145,7 → 145,7 |
/** When bit on this position is 1, a reserved bit was set in page directory. */ |
#define PFERR_CODE_RSVD (1 << 3) |
static inline int get_pt_flags(pte_t *pt, index_t i) |
static inline int get_pt_flags(pte_t *pt, size_t i) |
{ |
pte_t *p = &pt[i]; |
158,7 → 158,7 |
p->global << PAGE_GLOBAL_SHIFT); |
} |
static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
static inline void set_pt_flags(pte_t *pt, size_t i, int flags) |
{ |
pte_t *p = &pt[i]; |
/branches/network/kernel/arch/ia32/include/cpu.h |
---|
57,7 → 57,7 |
unsigned int stepping; |
tss_t *tss; |
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ |
size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ |
} cpu_arch_t; |
#endif |
/branches/network/kernel/arch/ia32/Makefile.inc |
---|
35,7 → 35,8 |
TARGET = i686-pc-linux-gnu |
TOOLCHAIN_DIR = $(CROSS_PREFIX)/i686 |
DEFS += -D__32_BITS__ |
BITS = 32 |
ENDIANESS = LE |
CMN1 = -m32 |
GCC_CFLAGS += $(CMN1) |
/branches/network/kernel/arch/ia32/src/smp/mps.c |
---|
86,10 → 86,10 |
/* |
* Implementation of IA-32 SMP configuration interface. |
*/ |
static count_t get_cpu_count(void); |
static bool is_cpu_enabled(index_t i); |
static bool is_bsp(index_t i); |
static uint8_t get_cpu_apic_id(index_t i); |
static size_t get_cpu_count(void); |
static bool is_cpu_enabled(size_t i); |
static bool is_bsp(size_t i); |
static uint8_t get_cpu_apic_id(size_t i); |
static int mps_irq_to_pin(unsigned int irq); |
struct smp_config_operations mps_config_operations = { |
100,24 → 100,24 |
.irq_to_pin = mps_irq_to_pin |
}; |
count_t get_cpu_count(void) |
size_t get_cpu_count(void) |
{ |
return processor_entry_cnt; |
} |
bool is_cpu_enabled(index_t i) |
bool is_cpu_enabled(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01); |
} |
bool is_bsp(index_t i) |
bool is_bsp(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02); |
} |
uint8_t get_cpu_apic_id(index_t i) |
uint8_t get_cpu_apic_id(size_t i) |
{ |
ASSERT(i < processor_entry_cnt); |
return processor_entries[i].l_apic_id; |
/branches/network/kernel/arch/ia32/src/ddi/ddi.c |
---|
57,7 → 57,7 |
*/ |
int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
{ |
count_t bits; |
size_t bits; |
bits = ioaddr + size; |
if (bits > IO_PORTS) |
99,7 → 99,7 |
/* |
* Enable the range and we are done. |
*/ |
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size); |
bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); |
/* |
* Increment I/O Permission bitmap generation counter. |
118,10 → 118,10 |
*/ |
void io_perm_bitmap_install(void) |
{ |
count_t bits; |
size_t bits; |
ptr_16_32_t cpugdtr; |
descriptor_t *gdt_p; |
count_t ver; |
size_t ver; |
/* First, copy the I/O Permission Bitmap. */ |
spinlock_lock(&TASK->lock); |
/branches/network/kernel/arch/ia32/src/mm/tlb.c |
---|
59,7 → 59,7 |
* @param page Address of the first page whose entry is to be invalidated. |
* @param cnt Number of entries to invalidate. |
*/ |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt) |
void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt) |
{ |
unsigned int i; |
/branches/network/kernel/arch/ia32/src/mm/frame.c |
---|
70,7 → 70,7 |
#endif |
pfn_t pfn; |
count_t count; |
size_t count; |
if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) { |
/* To be safe, make available zone possibly smaller */ |
/branches/network/kernel/arch/ia32/src/interrupt.c |
---|
101,7 → 101,7 |
static void gp_fault(int n __attribute__((unused)), istate_t *istate) |
{ |
if (TASK) { |
count_t ver; |
size_t ver; |
spinlock_lock(&TASK->lock); |
ver = TASK->arch.iomapver; |
/branches/network/kernel/arch/ia32/src/atomic.S |
---|
42,9 → 42,7 |
movl 12(%esp),%ebx |
0: |
#ifdef CONFIG_HT |
pause # Pentium 4's with HT love this instruction |
#endif |
movl (%ebx),%eax |
testl %eax,%eax |
jnz 0b # lightweight looping while it is locked |