/branches/network/kernel/arch/sparc64/include/atomic.h |
---|
37,6 → 37,7 |
#include <arch/barrier.h> |
#include <arch/types.h> |
#include <preemption.h> |
/** Atomic add operation. |
* |
56,7 → 57,8 |
a = *((uint64_t *) x); |
b = a + i; |
asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a)); |
asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), |
"+r" (b) : "r" (a)); |
} while (a != b); |
return a; |
97,7 → 99,8 |
uint64_t v = 1; |
volatile uintptr_t x = (uint64_t) &val->count; |
asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), |
"+r" (v) : "r" (0)); |
return v; |
} |
109,6 → 112,8 |
volatile uintptr_t x = (uint64_t) &val->count; |
preemption_disable(); |
asm volatile ( |
"0:\n" |
"casx %0, %3, %1\n" |
/branches/network/kernel/arch/sparc64/include/mm/page.h |
---|
53,11 → 53,6 |
#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
/* |
* With 16K pages, there is only one page color. |
*/ |
#define PAGE_COLOR_BITS 0 /**< 14 - 14; 2^14 == 16K == alias boundary. */ |
#ifdef KERNEL |
#ifndef __ASM__ |
/branches/network/kernel/arch/sparc64/include/mm/tlb.h |
---|
160,7 → 160,7 |
static inline void mmu_primary_context_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
flush(); |
flush_pipeline(); |
} |
/** Read MMU Secondary Context Register. |
179,7 → 179,7 |
static inline void mmu_secondary_context_write(uint64_t v) |
{ |
asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
flush(); |
flush_pipeline(); |
} |
/** Read IMMU TLB Data Access Register. |
209,7 → 209,7 |
reg.value = 0; |
reg.tlb_entry = entry; |
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
flush(); |
flush_pipeline(); |
} |
/** Read DMMU TLB Data Access Register. |
279,7 → 279,7 |
static inline void itlb_tag_access_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
flush(); |
flush_pipeline(); |
} |
/** Read IMMU TLB Tag Access Register. |
318,7 → 318,7 |
static inline void itlb_data_in_write(uint64_t v) |
{ |
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
flush(); |
flush_pipeline(); |
} |
/** Write DMMU TLB Data in Register. |
347,7 → 347,7 |
static inline void itlb_sfsr_write(uint64_t v) |
{ |
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
flush(); |
flush_pipeline(); |
} |
/** Read DTLB Synchronous Fault Status Register. |
400,7 → 400,7 |
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
* address within the |
* ASI */ |
flush(); |
flush_pipeline(); |
} |
/** Perform DMMU TLB Demap Operation. |
/branches/network/kernel/arch/sparc64/include/mm/cache_spec.h |
---|
0,0 → 1,57 |
/* |
* Copyright (c) 2008 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_sparc64_CACHE_SPEC_H_ |
#define KERN_sparc64_CACHE_SPEC_H_ |
/* |
* The following macros are valid for the following processors: |
* |
* UltraSPARC, UltraSPARC II, UltraSPARC IIi |
* |
* Should we support other UltraSPARC processors, we need to make sure that |
* the macros are defined correctly for them. |
*/ |
#define DCACHE_SIZE (16 * 1024) |
#define DCACHE_LINE_SIZE 32 |
#define ICACHE_SIZE (16 * 1024) |
#define ICACHE_WAYS 2 |
#define ICACHE_LINE_SIZE 32 |
#endif |
/** @} |
*/ |
/branches/network/kernel/arch/sparc64/include/barrier.h |
---|
57,8 → 57,11 |
#define write_barrier() \ |
asm volatile ("membar #StoreStore\n" ::: "memory") |
/** Flush Instruction Memory instruction. */ |
static inline void flush(void) |
#define flush(a) \ |
asm volatile ("flush %0\n" :: "r" ((a)) : "memory") |
/** Flush Instruction pipeline. */ |
static inline void flush_pipeline(void) |
{ |
/* |
* The FLUSH instruction takes address parameter. |
79,6 → 82,21 |
asm volatile ("membar #Sync\n"); |
} |
#define smc_coherence(a) \ |
{ \ |
write_barrier(); \ |
flush((a)); \ |
} |
#define FLUSH_INVAL_MIN 4 |
#define smc_coherence_block(a, l) \ |
{ \ |
unsigned long i; \ |
write_barrier(); \ |
for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ |
flush((void *)(a) + i); \ |
} |
#endif |
/** @} |
/branches/network/kernel/arch/sparc64/include/memstr.h |
---|
37,10 → 37,10 |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); |
extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); |
extern void memsetw(void *dst, size_t cnt, uint16_t x); |
extern void memsetb(void *dst, size_t cnt, uint8_t x); |
extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); |
extern int memcmp(const void *a, const void *b, size_t cnt); |
#endif |
/branches/network/kernel/arch/sparc64/include/asm.h |
---|
37,6 → 37,7 |
#include <arch/arch.h> |
#include <arch/types.h> |
#include <typedefs.h> |
#include <align.h> |
#include <arch/register.h> |
#include <config.h> |
/branches/network/kernel/arch/sparc64/include/cpu.h |
---|
36,6 → 36,7 |
#define KERN_sparc64_CPU_H_ |
#include <arch/types.h> |
#include <typedefs.h> |
#include <arch/register.h> |
#include <arch/asm.h> |
/branches/network/kernel/arch/sparc64/include/types.h |
---|
35,10 → 35,6 |
#ifndef KERN_sparc64_TYPES_H_ |
#define KERN_sparc64_TYPES_H_ |
#define NULL 0 |
#define false 0 |
#define true 1 |
typedef signed char int8_t; |
typedef signed short int16_t; |
typedef signed int int32_t; |
61,13 → 57,31 |
typedef uint64_t unative_t; |
typedef int64_t native_t; |
typedef uint8_t bool; |
typedef uint64_t thread_id_t; |
typedef uint64_t task_id_t; |
typedef uint32_t context_id_t; |
/**< Formats for uintptr_t, size_t, count_t and index_t */ |
#define PRIp "llx" |
#define PRIs "llu" |
#define PRIc "llu" |
#define PRIi "llu" |
typedef int32_t inr_t; |
typedef int32_t devno_t; |
/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ |
#define PRId8 "d" |
#define PRId16 "d" |
#define PRId32 "d" |
#define PRId64 "lld" |
#define PRIdn "lld" |
#define PRIu8 "u" |
#define PRIu16 "u" |
#define PRIu32 "u" |
#define PRIu64 "llu" |
#define PRIun "llu" |
#define PRIx8 "x" |
#define PRIx16 "x" |
#define PRIx32 "x" |
#define PRIx64 "llx" |
#define PRIxn "llx" |
typedef uint8_t asi_t; |
#endif |
/branches/network/kernel/arch/sparc64/include/context_offset.h |
---|
48,4 → 48,60 |
#define OFFSET_L6 0x80 |
#define OFFSET_L7 0x88 |
#ifndef KERNEL |
# define OFFSET_TP 0x90 |
#endif |
#ifdef __ASM__ |
.macro CONTEXT_SAVE_ARCH_CORE ctx:req |
stx %sp, [\ctx + OFFSET_SP] |
stx %o7, [\ctx + OFFSET_PC] |
stx %i0, [\ctx + OFFSET_I0] |
stx %i1, [\ctx + OFFSET_I1] |
stx %i2, [\ctx + OFFSET_I2] |
stx %i3, [\ctx + OFFSET_I3] |
stx %i4, [\ctx + OFFSET_I4] |
stx %i5, [\ctx + OFFSET_I5] |
stx %fp, [\ctx + OFFSET_FP] |
stx %i7, [\ctx + OFFSET_I7] |
stx %l0, [\ctx + OFFSET_L0] |
stx %l1, [\ctx + OFFSET_L1] |
stx %l2, [\ctx + OFFSET_L2] |
stx %l3, [\ctx + OFFSET_L3] |
stx %l4, [\ctx + OFFSET_L4] |
stx %l5, [\ctx + OFFSET_L5] |
stx %l6, [\ctx + OFFSET_L6] |
stx %l7, [\ctx + OFFSET_L7] |
#ifndef KERNEL |
stx %g7, [\ctx + OFFSET_TP] |
#endif |
.endm |
.macro CONTEXT_RESTORE_ARCH_CORE ctx:req |
ldx [\ctx + OFFSET_SP], %sp |
ldx [\ctx + OFFSET_PC], %o7 |
ldx [\ctx + OFFSET_I0], %i0 |
ldx [\ctx + OFFSET_I1], %i1 |
ldx [\ctx + OFFSET_I2], %i2 |
ldx [\ctx + OFFSET_I3], %i3 |
ldx [\ctx + OFFSET_I4], %i4 |
ldx [\ctx + OFFSET_I5], %i5 |
ldx [\ctx + OFFSET_FP], %fp |
ldx [\ctx + OFFSET_I7], %i7 |
ldx [\ctx + OFFSET_L0], %l0 |
ldx [\ctx + OFFSET_L1], %l1 |
ldx [\ctx + OFFSET_L2], %l2 |
ldx [\ctx + OFFSET_L3], %l3 |
ldx [\ctx + OFFSET_L4], %l4 |
ldx [\ctx + OFFSET_L5], %l5 |
ldx [\ctx + OFFSET_L6], %l6 |
ldx [\ctx + OFFSET_L7], %l7 |
#ifndef KERNEL |
ldx [\ctx + OFFSET_TP], %g7 |
#endif |
.endm |
#endif /* __ASM__ */ |
#endif |
/branches/network/kernel/arch/sparc64/include/byteorder.h |
---|
35,14 → 35,8 |
#ifndef KERN_sparc64_BYTEORDER_H_ |
#define KERN_sparc64_BYTEORDER_H_ |
#include <byteorder.h> |
#define ARCH_IS_BIG_ENDIAN |
#define uint32_t_le2host(n) uint32_t_byteorder_swap(n) |
#define uint64_t_le2host(n) uint64_t_byteorder_swap(n) |
#define uint32_t_be2host(n) (n) |
#define uint64_t_be2host(n) (n) |
#endif |
/** @} |