WebSVN – HelenOS – Path Comparison – / – /branches/network/kernel/arch/sparc64/ Rev 4252 and /branches/network/kernel/arch/sparc64 Rev 3386

Ignore whitespace Rev 4252 → Rev 3386

/branches/network/kernel/arch/sparc64/include/cpu_node.h
File deleted

/branches/network/kernel/arch/sparc64/include/cpu_family.h
File deleted

 /branches/network/kernel/arch/sparc64/include/mm/tlb.h
 ,17 → 35,9
 #ifndef KERN_sparc64_TLB_H_
 #define KERN_sparc64_TLB_H_
-#if defined (US)
 #define ITLB_ENTRY_COUNT        64
 #define DTLB_ENTRY_COUNT        64
-#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
-#endif
-/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
-#if defined (US3)
-#define DTLB_MAX_LOCKED_ENTRIES     16
-#endif
 #define MEM_CONTEXT_KERNEL      0
 #define MEM_CONTEXT_TEMP        1
 ,9 → 53,6
 /* TLB Demap Operation types. */
 #define TLB_DEMAP_PAGE      0
 #define TLB_DEMAP_CONTEXT   1
-#if defined (US3)
-#define TLB_DEMAP_ALL       2
-#endif
 #define TLB_DEMAP_TYPE_SHIFT    6
 ,18 → 61,6
 #define TLB_DEMAP_SECONDARY 1
 #define TLB_DEMAP_NUCLEUS   2
-/* There are more TLBs in one MMU in US3, their codes are defined here. */
-#if defined (US3)
-/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
-#define TLB_DSMALL  0
-#define TLB_DBIG_0  2
-#define TLB_DBIG_1  3
-/* I-MMU: one small (16-entry) TLB and one big TLB */
-#define TLB_ISMALL  0
-#define TLB_IBIG    2
-#endif
 #define TLB_DEMAP_CONTEXT_SHIFT 4
 /* TLB Tag Access shifts */
 ,8 → 76,6
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <arch/types.h>
-#include <arch/register.h>
-#include <arch/cpu.h>
 union tlb_context_reg {
     uint64_t v;
 ,9 → 90,6
 typedef tte_data_t tlb_data_t;
 /** I-/D-TLB Data Access Address in Alternate Space. */
-#if defined (US)
 union tlb_data_access_addr {
     uint64_t value;
     struct {
 ,54 → 98,9
         unsigned : 3;
     } __attribute__ ((packed));
 };
-typedef union tlb_data_access_addr dtlb_data_access_addr_t;
-typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
-typedef union tlb_data_access_addr itlb_data_access_addr_t;
-typedef union tlb_data_access_addr itlb_tag_read_addr_t;
+typedef union tlb_data_access_addr tlb_data_access_addr_t;
+typedef union tlb_data_access_addr tlb_tag_read_addr_t;
-#elif defined (US3)
-/*
- * In US3, I-MMU and D-MMU have different formats of the data
- * access register virtual address. In the corresponding
- * structures the member variable for the entry number is
- * called "local_tlb_entry" - it contrasts with the "tlb_entry"
- * for the US data access register VA structure. The rationale
- * behind this is to prevent careless mistakes in the code
- * caused by setting only the entry number and not the TLB
- * number in the US3 code (when taking the code from US).
- */
-union dtlb_data_access_addr {
-    uint64_t value;
-    struct {
-        uint64_t : 45;
-        unsigned : 1;
-        unsigned tlb_number : 2;
-        unsigned : 4;
-        unsigned local_tlb_entry : 9;
-        unsigned : 3;
-    } __attribute__ ((packed));
-};
-typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
-typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
-union itlb_data_access_addr {
-    uint64_t value;
-    struct {
-        uint64_t : 45;
-        unsigned : 1;
-        unsigned tlb_number : 2;
-        unsigned : 6;
-        unsigned local_tlb_entry : 7;
-        unsigned : 3;
-    } __attribute__ ((packed));
-};
-typedef union itlb_data_access_addr itlb_data_access_addr_t;
-typedef union itlb_data_access_addr itlb_tag_read_addr_t;
-#endif
 /** I-/D-TLB Tag Read Register. */
 union tlb_tag_read_reg {
     uint64_t value;
 ,13 → 118,8
     uint64_t value;
     struct {
         uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
-#if defined (US)
         unsigned : 6;       /**< Ignored. */
         unsigned type : 1;  /**< The type of demap operation. */
-#elif defined (US3)
-        unsigned : 5;       /**< Ignored. */
-        unsigned type: 2;   /**< The type of demap operation. */
-#endif
         unsigned context : 2;   /**< Context register selection. */
         unsigned : 4;       /**< Zero. */
     } __attribute__ ((packed));
 ,19 → 130,10
 union tlb_sfsr_reg {
     uint64_t value;
     struct {
-#if defined (US)
         unsigned long : 40; /**< Implementation dependent. */
         unsigned asi : 8;   /**< ASI. */
         unsigned : 2;
         unsigned ft : 7;    /**< Fault type. */
-#elif defined (US3)
-        unsigned long : 39; /**< Implementation dependent. */
-        unsigned nf : 1;    /**< Non-faulting load. */
-        unsigned asi : 8;   /**< ASI. */
-        unsigned tm : 1;    /**< I-TLB miss. */
-        unsigned : 3;       /**< Reserved. */
-        unsigned ft : 5;    /**< Fault type. */
-#endif
         unsigned e : 1;     /**< Side-effect bit. */
         unsigned ct : 2;    /**< Context Register selection. */
         unsigned pr : 1;    /**< Privilege bit. */
 ,53 → 144,9
 };
 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
-#if defined (US3)
-/*
- * Functions for determining the number of entries in TLBs. They either return
- * a constant value or a value based on the CPU autodetection.
- */
-/**
- * Determine the number of entries in the DMMU's small TLB.
- */
-static inline uint16_t tlb_dsmall_size(void)
-{
-    return 16;
-}
-/**
- * Determine the number of entries in each DMMU's big TLB.
- */
-static inline uint16_t tlb_dbig_size(void)
-{
-    return 512;
-}
-/**
- * Determine the number of entries in the IMMU's small TLB.
- */
-static inline uint16_t tlb_ismall_size(void)
-{
-    return 16;
-}
-/**
- * Determine the number of entries in the IMMU's big TLB.
- */
-static inline uint16_t tlb_ibig_size(void)
-{
-    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
-        return 512;
-    else
-        return 128;
-}
-#endif
 /** Read MMU Primary Context Register.
  *
- * @return      Current value of Primary Context Register.
+ * @return Current value of Primary Context Register.
  */
 static inline uint64_t mmu_primary_context_read(void)
 {
 ,7 → 155,7
 /** Write MMU Primary Context Register.
  *
- * @param v     New value of Primary Context Register.
+ * @param v New value of Primary Context Register.
  */
 static inline void mmu_primary_context_write(uint64_t v)
 {
 ,7 → 165,7
 /** Read MMU Secondary Context Register.
  *
- * @return      Current value of Secondary Context Register.
+ * @return Current value of Secondary Context Register.
  */
 static inline uint64_t mmu_secondary_context_read(void)
 {
 ,7 → 174,7
 /** Write MMU Primary Context Register.
  *
- * @param v     New value of Primary Context Register.
+ * @param v New value of Primary Context Register.
  */
 static inline void mmu_secondary_context_write(uint64_t v)
 {
 ,18 → 182,15
     flush_pipeline();
 }
-#if defined (US)
 /** Read IMMU TLB Data Access Register.
  *
- * @param entry     TLB Entry index.
+ * @param entry TLB Entry index.
  *
- * @return      Current value of specified IMMU TLB Data Access
- *          Register.
+ * @return Current value of specified IMMU TLB Data Access Register.
  */
 static inline uint64_t itlb_data_access_read(index_t entry)
 {
-    itlb_data_access_addr_t reg;
+    tlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,12 → 199,12
 /** Write IMMU TLB Data Access Register.
  *
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
+ * @param entry TLB Entry index.
+ * @param value Value to be written.
  */
 static inline void itlb_data_access_write(index_t entry, uint64_t value)
 {
-    itlb_data_access_addr_t reg;
+    tlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,14 → 214,13
 /** Read DMMU TLB Data Access Register.
  *
- * @param entry     TLB Entry index.
+ * @param entry TLB Entry index.
  *
- * @return      Current value of specified DMMU TLB Data Access
- *          Register.
+ * @return Current value of specified DMMU TLB Data Access Register.
  */
 static inline uint64_t dtlb_data_access_read(index_t entry)
 {
-    dtlb_data_access_addr_t reg;
+    tlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,12 → 229,12
 /** Write DMMU TLB Data Access Register.
  *
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
+ * @param entry TLB Entry index.
+ * @param value Value to be written.
  */
 static inline void dtlb_data_access_write(index_t entry, uint64_t value)
 {
-    dtlb_data_access_addr_t reg;
+    tlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,13 → 244,13
 /** Read IMMU TLB Tag Read Register.
  *
- * @param entry     TLB Entry index.
+ * @param entry TLB Entry index.
  *
- * @return      Current value of specified IMMU TLB Tag Read Register.
+ * @return Current value of specified IMMU TLB Tag Read Register.
  */
 static inline uint64_t itlb_tag_read_read(index_t entry)
 {
-    itlb_tag_read_addr_t tag;
+    tlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
 ,13 → 259,13
 /** Read DMMU TLB Tag Read Register.
  *
- * @param entry     TLB Entry index.
+ * @param entry TLB Entry index.
  *
- * @return      Current value of specified DMMU TLB Tag Read Register.
+ * @return Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(index_t entry)
 {
-    dtlb_tag_read_addr_t tag;
+    tlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
 ,120 → 272,9
     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
 }
-#elif defined (US3)
-/** Read IMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write IMMU TLB Data Access Register.
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void itlb_data_access_write(int tlb, index_t entry,
-    uint64_t value)
-{
-    itlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-    flush_pipeline();
-}
-/** Read DMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Data Access
- *          Register.
- */
-static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
-}
-/** Write DMMU TLB Data Access Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
- * @param entry     TLB Entry index.
- * @param value     Value to be written.
- */
-static inline void dtlb_data_access_write(int tlb, index_t entry,
-    uint64_t value)
-{
-    dtlb_data_access_addr_t reg;
-    reg.value = 0;
-    reg.tlb_number = tlb;
-    reg.local_tlb_entry = entry;
-    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
-    membar();
-}
-/** Read IMMU TLB Tag Read Register.
- *
- * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified IMMU TLB Tag Read Register.
- */
-static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
-{
-    itlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_number = tlb;
-    tag.local_tlb_entry = entry;
-    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
-}
-/** Read DMMU TLB Tag Read Register.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
- * @param entry     TLB Entry index.
- *
- * @return      Current value of specified DMMU TLB Tag Read Register.
- */
-static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
-{
-    dtlb_tag_read_addr_t tag;
-    tag.value = 0;
-    tag.tlb_number = tlb;
-    tag.local_tlb_entry = entry;
-    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
-}
-#endif
 /** Write IMMU TLB Tag Access Register.
  *
- * @param v     Value to be written.
+ * @param v Value to be written.
  */
 static inline void itlb_tag_access_write(uint64_t v)
 {
 ,7 → 284,7
 /** Read IMMU TLB Tag Access Register.
  *
- * @return      Current value of IMMU TLB Tag Access Register.
+ * @return Current value of IMMU TLB Tag Access Register.
  */
 static inline uint64_t itlb_tag_access_read(void)
 {
 ,7 → 293,7
 /** Write DMMU TLB Tag Access Register.
  *
- * @param v     Value to be written.
+ * @param v Value to be written.
  */
 static inline void dtlb_tag_access_write(uint64_t v)
 {
 ,7 → 303,7
 /** Read DMMU TLB Tag Access Register.
  *
- * @return      Current value of DMMU TLB Tag Access Register.
+ * @return Current value of DMMU TLB Tag Access Register.
  */
 static inline uint64_t dtlb_tag_access_read(void)
 {
 ,7 → 313,7
 /** Write IMMU TLB Data in Register.
  *
- * @param v     Value to be written.
+ * @param v Value to be written.
  */
 static inline void itlb_data_in_write(uint64_t v)
 {
 ,7 → 323,7
 /** Write DMMU TLB Data in Register.
  *
- * @param v     Value to be written.
+ * @param v Value to be written.
  */
 static inline void dtlb_data_in_write(uint64_t v)
 {
 ,7 → 333,7
 /** Read ITLB Synchronous Fault Status Register.
  *
- * @return      Current content of I-SFSR register.
+ * @return Current content of I-SFSR register.
  */
 static inline uint64_t itlb_sfsr_read(void)
 {
 ,7 → 342,7
 /** Write ITLB Synchronous Fault Status Register.
  *
- * @param v     New value of I-SFSR register.
+ * @param v New value of I-SFSR register.
  */
 static inline void itlb_sfsr_write(uint64_t v)
 {
 ,7 → 352,7
 /** Read DTLB Synchronous Fault Status Register.
  *
- * @return      Current content of D-SFSR register.
+ * @return Current content of D-SFSR register.
  */
 static inline uint64_t dtlb_sfsr_read(void)
 {
 ,7 → 361,7
 /** Write DTLB Synchronous Fault Status Register.
  *
- * @param v     New value of D-SFSR register.
+ * @param v New value of D-SFSR register.
  */
 static inline void dtlb_sfsr_write(uint64_t v)
 {
 ,7 → 371,7
 /** Read DTLB Synchronous Fault Address Register.
  *
- * @return      Current content of D-SFAR register.
+ * @return Current content of D-SFAR register.
  */
 static inline uint64_t dtlb_sfar_read(void)
 {
 ,11 → 380,10
 /** Perform IMMU TLB Demap Operation.
  *
- * @param type      Selects between context and page demap (and entire MMU
- *          demap on US3).
+ * @param type Selects between context and page demap.
  * @param context_encoding Specifies which Context register has Context ID for
- *          demap.
- * @param page      Address which is on the page to be demapped.
+ *  demap.
+ * @param page Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 ,19 → 397,18
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    /* da.value is the address within the ASI */
-    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
+    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
+                             * address within the
+                             * ASI */
     flush_pipeline();
 }
 /** Perform DMMU TLB Demap Operation.
  *
- * @param type      Selects between context and page demap (and entire MMU
- *          demap on US3).
+ * @param type Selects between context and page demap.
  * @param context_encoding Specifies which Context register has Context ID for
- *          demap.
- * @param page      Address which is on the page to be demapped.
+ *   demap.
+ * @param page Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 ,17 → 422,17
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    /* da.value is the address within the ASI */
-    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
+    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
+                             * address within the
+                             * ASI */
     membar();
 }
-extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
-extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
-extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
+extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
+extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
+extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
-extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
+extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 extern void dump_sfsr_and_sfar(void);

 /branches/network/kernel/arch/sparc64/include/mm/cache_spec.h
 ,20 → 38,19
 /*
  * The following macros are valid for the following processors:
  *
- *  UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
- *  UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
+ *  UltraSPARC, UltraSPARC II, UltraSPARC IIi
  *
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
-#if defined (US)
 #define DCACHE_SIZE     (16 * 1024)
-#elif defined (US3)
-#define DCACHE_SIZE     (64 * 1024)
-#endif
 #define DCACHE_LINE_SIZE    32
+#define ICACHE_SIZE     (16 * 1024)
+#define ICACHE_WAYS     2
+#define ICACHE_LINE_SIZE    32
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/mm/frame.h
 ,13 → 59,8
 union frame_address {
     uintptr_t address;
     struct {
-#if defined (US)
         unsigned : 23;
         uint64_t pfn : 28;      /**< Physical Frame Number. */
-#elif defined (US3)
-        unsigned : 21;
-        uint64_t pfn : 30;      /**< Physical Frame Number. */
-#endif
         unsigned offset : 13;       /**< Offset. */
     } __attribute__ ((packed));
 };

 /branches/network/kernel/arch/sparc64/include/mm/cache.h
 ,6 → 38,15
 #include <mm/page.h>
 #include <mm/frame.h>
+#define dcache_flush_page(p) \
+    dcache_flush_color(PAGE_COLOR((p)))
+#define dcache_flush_frame(p, f) \
+    dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f)));
+extern void dcache_flush(void);
+extern void dcache_flush_color(int c);
+extern void dcache_flush_tag(int c, pfn_t tag);
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/mm/tsb.h
 ,55 → 107,6
     asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
 }
-#if defined (US3)
-/** Write DTSB Primary Extension register.
- *
- * @param v New content of the DTSB Primary Extension register.
- */
-static inline void dtsb_primary_extension_write(uint64_t v)
-{
-    asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
-}
-/** Write DTSB Secondary Extension register.
- *
- * @param v New content of the DTSB Secondary Extension register.
- */
-static inline void dtsb_secondary_extension_write(uint64_t v)
-{
-    asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
-}
-/** Write DTSB Nucleus Extension register.
- *
- * @param v New content of the DTSB Nucleus Extension register.
- */
-static inline void dtsb_nucleus_extension_write(uint64_t v)
-{
-    asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
-}
-/** Write ITSB Primary Extension register.
- *
- * @param v New content of the ITSB Primary Extension register.
- */
-static inline void itsb_primary_extension_write(uint64_t v)
-{
-    asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
-}
-/** Write ITSB Nucleus Extension register.
- *
- * @param v New content of the ITSB Nucleus Extension register.
- */
-static inline void itsb_nucleus_extension_write(uint64_t v)
-{
-    asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
-}
-#endif
 /* Forward declarations. */
 struct as;
 struct pte;

 /branches/network/kernel/arch/sparc64/include/mm/mmu.h
 ,10 → 35,8
 #ifndef KERN_sparc64_MMU_H_
 #define KERN_sparc64_MMU_H_
-#if defined(US)
 /* LSU Control Register ASI. */
 #define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
-#endif
 /* I-MMU ASIs. */
 #define ASI_IMMU            0x50
 ,12 → 52,7
 #define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
 #define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
 #define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
-#if defined (US3)
-#define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
-#define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
-#endif
 /* D-MMU ASIs. */
 #define ASI_DMMU            0x58
 #define ASI_DMMU_TSB_8KB_PTR_REG    0x59
 ,11 → 73,6
 #define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
 #define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
 #define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
-#if defined (US3)
-#define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
-#define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
-#define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
-#endif
 #ifndef __ASM__
 ,7 → 80,6
 #include <arch/barrier.h>
 #include <arch/types.h>
-#if defined(US)
 /** LSU Control Register. */
 typedef union {
     uint64_t value;
 ,7 → 100,6
     } __attribute__ ((packed));
 } lsu_cr_reg_t;
-#endif /* US */
 #endif /* !def __ASM__ */

 /branches/network/kernel/arch/sparc64/include/mm/tte.h
 ,7 → 50,6
 #include <arch/types.h>
-/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
 #define VA_TAG_PAGE_SHIFT   22
 /** Translation Table Entry - Tag. */
 ,13 → 75,8
         unsigned nfo : 1;   /**< No-Fault-Only. */
         unsigned ie : 1;    /**< Invert Endianness. */
         unsigned soft2 : 9; /**< Software defined field. */
-#if defined (US)
         unsigned diag : 9;  /**< Diagnostic data. */
         unsigned pfn : 28;  /**< Physical Address bits, bits 40:13. */
-#elif defined (US3)
-        unsigned : 7;       /**< Reserved. */
-        unsigned pfn : 30;  /**< Physical Address bits, bits 42:13 */
-#endif
         unsigned soft : 6;  /**< Software defined field. */
         unsigned l : 1;     /**< Lock. */
         unsigned cp : 1;    /**< Cacheable in physically indexed cache. */

 /branches/network/kernel/arch/sparc64/include/barrier.h
 ,8 → 82,6
     asm volatile ("membar #Sync\n");
 }
-#if defined (US)
 #define smc_coherence(a)    \
 {               \
     write_barrier();    \
 ,22 → 97,6
         flush((void *)(a) + i);         \
 }
-#elif defined (US3)
-#define smc_coherence(a)    \
-{               \
-    write_barrier();    \
-    flush_pipeline();   \
-}
-#define smc_coherence_block(a, l)   \
-{                   \
-    write_barrier();        \
-    flush_pipeline();       \
-}
-#endif  /* defined(US3) */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/asm.h
 ,56 → 42,7
 #include <arch/register.h>
 #include <config.h>
 #include <arch/stack.h>
-#include <arch/barrier.h>
-static inline void pio_write_8(ioport8_t *port, uint8_t v)
-{
-    *port = v;
-    memory_barrier();
-}
-static inline void pio_write_16(ioport16_t *port, uint16_t v)
-{
-    *port = v;
-    memory_barrier();
-}
-static inline void pio_write_32(ioport32_t *port, uint32_t v)
-{
-    *port = v;
-    memory_barrier();
-}
-static inline uint8_t pio_read_8(ioport8_t *port)
-{
-    uint8_t rv;
-    rv = *port;
-    memory_barrier();
-    return rv;
-}
-static inline uint16_t pio_read_16(ioport16_t *port)
-{
-    uint16_t rv;
-    rv = *port;
-    memory_barrier();
-    return rv;
-}
-static inline uint32_t pio_read_32(ioport32_t *port)
-{
-    uint32_t rv;
-    rv = *port;
-    memory_barrier();
-    return rv;
-}
 /** Read Processor State register.
  *
  * @return Value of PSTATE register.
 ,28 → 87,6
     asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
 }
-/** Read STICK_compare Register.
- *
- * @return Value of STICK_compare register.
- */
-static inline uint64_t stick_compare_read(void)
-{
-    uint64_t v;
-    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
-    return v;
-}
-/** Write STICK_compare Register.
- *
- * @param v New value of STICK_comapre register.
- */
-static inline void stick_compare_write(uint64_t v)
-{
-    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
-}
 /** Read TICK Register.
  *
  * @return Value of TICK register.
 ,6 → 358,15
     asm volatile ("wrpr %g0, %g0, %tl\n");
 }
+/** Read UPA_CONFIG register.
+ *
+ * @return Value of the UPA_CONFIG register.
+ */
+static inline uint64_t upa_config_read(void)
+{
+    return asi_u64_read(ASI_UPA_CONFIG, 0);
+}
 extern void cpu_halt(void);
 extern void cpu_sleep(void);
 extern void asm_delay_loop(const uint32_t usec);

 /branches/network/kernel/arch/sparc64/include/cpu.h
 ,6 → 35,15
 #ifndef KERN_sparc64_CPU_H_
 #define KERN_sparc64_CPU_H_
+#include <arch/types.h>
+#include <typedefs.h>
+#include <arch/register.h>
+#include <arch/asm.h>
+#ifdef CONFIG_SMP
+#include <arch/mm/cache.h>
+#endif
 #define MANUF_FUJITSU       0x04
 #define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
 #define MANUF_SUN       0x3e
 ,29 → 52,14
 #define IMPL_ULTRASPARCII   0x11
 #define IMPL_ULTRASPARCII_I 0x12
 #define IMPL_ULTRASPARCII_E 0x13
-#define IMPL_ULTRASPARCIII  0x14
-#define IMPL_ULTRASPARCIII_PLUS 0x15
-#define IMPL_ULTRASPARCIII_I    0x16
-#define IMPL_ULTRASPARCIV   0x18
+#define IMPL_ULTRASPARCIII  0x15
 #define IMPL_ULTRASPARCIV_PLUS  0x19
 #define IMPL_SPARC64V       0x5
-#ifndef __ASM__
-#include <arch/types.h>
-#include <typedefs.h>
-#include <arch/register.h>
-#include <arch/regdef.h>
-#include <arch/asm.h>
-#ifdef CONFIG_SMP
-#include <arch/mm/cache.h>
-#endif
 typedef struct {
     uint32_t mid;           /**< Processor ID as read from
-                         UPA_CONFIG/FIREPLANE_CONFIG. */
+                         UPA_CONFIG. */
     ver_reg_t ver;
     uint32_t clock_frequency;   /**< Processor frequency in Hz. */
     uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
 ,28 → 66,8
                          generated when the TICK register
                          matches this value. */
 } cpu_arch_t;
-/**
- * Reads the module ID (agent ID/CPUID) of the current CPU.
- */
-static inline uint32_t read_mid(void)
-{
-    uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
-    icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
-#if defined (US)
-    return icbus_config & 0x1f;
-#elif defined (US3)
-    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
-        return icbus_config & 0x1f;
-    else
-        return icbus_config & 0x3ff;
 #endif
-}
-#endif
-#endif
 /** @}
  */

 /branches/network/kernel/arch/sparc64/include/types.h
 ,9 → 57,6
 typedef uint64_t unative_t;
 typedef int64_t native_t;
-typedef struct {
-} fncptr_t;
 /**< Formats for uintptr_t, size_t, count_t and index_t */
 #define PRIp "llx"
 #define PRIs "llu"

 /branches/network/kernel/arch/sparc64/include/trap/syscall.h
 ,14 → 31,26
  */
 /**
  * @file
- * @brief
+ * @brief This file contains the trap_instruction handler.
+ *
+ * The trap_instruction trap is used to implement syscalls.
  */
 #ifndef KERN_sparc64_SYSCALL_TRAP_H_
 #define KERN_sparc64_SYSCALL_TRAP_H_
-#define TT_TRAP_INSTRUCTION_0       0x100
+#define TT_TRAP_INSTRUCTION(n)      (0x100 + (n))
+#define TT_TRAP_INSTRUCTION_LAST    TT_TRAP_INSTRUCTION(127)
+#ifdef __ASM__
+.macro TRAP_INSTRUCTION n
+    ba trap_instruction_handler
+    mov TT_TRAP_INSTRUCTION(\n) - TT_TRAP_INSTRUCTION(0), %g2
+.endm
+#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/trap/interrupt.h
 ,43 → 49,21
 /* Interrupt ASI registers. */
-#define ASI_INTR_W          0x77
+#define ASI_UDB_INTR_W          0x77
 #define ASI_INTR_DISPATCH_STATUS    0x48
-#define ASI_INTR_R          0x7f
+#define ASI_UDB_INTR_R          0x7f
 #define ASI_INTR_RECEIVE        0x49
-/* VA's used with ASI_INTR_W register. */
-#if defined (US)
+/* VA's used with ASI_UDB_INTR_W register. */
 #define ASI_UDB_INTR_W_DATA_0   0x40
 #define ASI_UDB_INTR_W_DATA_1   0x50
 #define ASI_UDB_INTR_W_DATA_2   0x60
-#elif defined (US3)
-#define VA_INTR_W_DATA_0    0x40
-#define VA_INTR_W_DATA_1    0x48
-#define VA_INTR_W_DATA_2    0x50
-#define VA_INTR_W_DATA_3    0x58
-#define VA_INTR_W_DATA_4    0x60
-#define VA_INTR_W_DATA_5    0x68
-#define VA_INTR_W_DATA_6    0x80
-#define VA_INTR_W_DATA_7    0x88
-#endif
-#define VA_INTR_W_DISPATCH  0x70
+#define ASI_UDB_INTR_W_DISPATCH 0x70
-/* VA's used with ASI_INTR_R register. */
-#if defined(US)
+/* VA's used with ASI_UDB_INTR_R register. */
 #define ASI_UDB_INTR_R_DATA_0   0x40
 #define ASI_UDB_INTR_R_DATA_1   0x50
 #define ASI_UDB_INTR_R_DATA_2   0x60
-#elif defined (US3)
-#define VA_INTR_R_DATA_0    0x40
-#define VA_INTR_R_DATA_1    0x48
-#define VA_INTR_R_DATA_2    0x50
-#define VA_INTR_R_DATA_3    0x58
-#define VA_INTR_R_DATA_4    0x60
-#define VA_INTR_R_DATA_5    0x68
-#define VA_INTR_R_DATA_6    0x80
-#define VA_INTR_R_DATA_7    0x88
-#endif
 /* Shifts in the Interrupt Vector Dispatch virtual address. */
 #define INTR_VEC_DISPATCH_MID_SHIFT 14

 /branches/network/kernel/arch/sparc64/include/trap/regwin.h
 ,7 → 39,6
 #include <arch/stack.h>
 #include <arch/arch.h>
-#include <align.h>
 #define TT_CLEAN_WINDOW         0x24
 #define TT_SPILL_0_NORMAL       0x80    /* kernel spills */
 ,11 → 72,6
 #define I6_OFFSET   112
 #define I7_OFFSET   120
-/* Uspace Window Buffer constants. */
-#define UWB_SIZE    ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE)
-#define UWB_ALIGNMENT   1024
-#define UWB_ASIZE   ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT)
 #ifdef __ASM__
 /*

/branches/network/kernel/arch/sparc64/include/drivers/sgcn.h
File deleted

 /branches/network/kernel/arch/sparc64/include/drivers/scr.h
 ,14 → 42,12
     SCR_UNKNOWN,
     SCR_ATYFB,
     SCR_FFB,
-    SCR_CGSIX,
-    SCR_XVR
+    SCR_CGSIX
 } scr_type_t;
 extern scr_type_t scr_type;
 extern void scr_init(ofw_tree_node_t *node);
-extern void scr_redraw(void);
 #endif

 /branches/network/kernel/arch/sparc64/include/drivers/z8530.h
 ,0 → 1,140
+/*
+ * Copyright (c) 2006 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_sparc64_Z8530_H_
+#define KERN_sparc64_Z8530_H_
+#include <arch/types.h>
+#include <arch/drivers/kbd.h>
+#define Z8530_CHAN_A    4
+#define Z8530_CHAN_B    0
+#define WR0 0
+#define WR1 1
+#define WR2 2
+#define WR3 3
+#define WR4 4
+#define WR5 5
+#define WR6 6
+#define WR7 7
+#define WR8 8
+#define WR9 9
+#define WR10    10
+#define WR11    11
+#define WR12    12
+#define WR13    13
+#define WR14    14
+#define WR15    15
+#define RR0 0
+#define RR1 1
+#define RR2 2
+#define RR3 3
+#define RR8 8
+#define RR10    10
+#define RR12    12
+#define RR13    13
+#define RR14    14
+#define RR15    15
+/* Write Register 0 */
+#define WR0_TX_IP_RST   (0x5<<3)    /** Reset pending TX interrupt. */
+#define WR0_ERR_RST (0x6<<3)
+/* Write Register 1 */
+#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
+#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
+#define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
+#define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
+#define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
+/* Write Register 3 */
+#define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
+#define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
+/* Write Register 9 */
+#define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
+/* Read Register 0 */
+#define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
+/** Structure representing the z8530 device. */
+typedef struct {
+    devno_t devno;
+    volatile uint8_t *reg;      /** Memory mapped registers of the z8530. */
+} z8530_t;
+static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val)
+{
+    /*
+     * Registers 8-15 will automatically issue the Point High
+     * command as their bit 3 is 1.
+     */
+    dev->reg[WR0+chan] = reg;   /* select register */
+    dev->reg[WR0+chan] = val;   /* write value */
+}
+static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val)
+{
+    z8530_write(dev, Z8530_CHAN_A, reg, val);
+}
+static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val)
+{
+    z8530_write(dev, Z8530_CHAN_B, reg, val);
+}
+static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg)
+{
+    /*
+     * Registers 8-15 will automatically issue the Point High
+     * command as their bit 3 is 1.
+     */
+    dev->reg[WR0+chan] = reg;   /* select register */
+    return dev->reg[WR0+chan];
+}
+static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg)
+{
+    return z8530_read(dev, Z8530_CHAN_A, reg);
+}
+static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg)
+{
+    return z8530_read(dev, Z8530_CHAN_B, reg);
+}
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/sparc64/include/drivers/pci.h
 ,8 → 51,8
 };
 struct pci_operations {
-    void (* enable_interrupt)(pci_t *, int);
-    void (* clear_interrupt)(pci_t *, int);
+    void (* enable_interrupt)(pci_t *pci, int inr);
+    void (* clear_interrupt)(pci_t *pci, int inr);
 };
 struct pci {
 ,9 → 61,9
     volatile uint64_t *reg;     /**< Registers including interrupt registers. */
 };
-extern pci_t *pci_init(ofw_tree_node_t *);
-extern void pci_enable_interrupt(pci_t *, int);
-extern void pci_clear_interrupt(void *, int);
+extern pci_t *pci_init(ofw_tree_node_t *node);
+extern void pci_enable_interrupt(pci_t *pci, int inr);
+extern void pci_clear_interrupt(pci_t *pci, int inr);
 #endif

 /branches/network/kernel/arch/sparc64/include/drivers/fhc.h
 ,9 → 44,9
 extern fhc_t *central_fhc;
-extern fhc_t *fhc_init(ofw_tree_node_t *);
-extern void fhc_enable_interrupt(fhc_t *, int);
-extern void fhc_clear_interrupt(void *, int);
+extern fhc_t *fhc_init(ofw_tree_node_t *node);
+extern void fhc_enable_interrupt(fhc_t *fhc, int inr);
+extern void fhc_clear_interrupt(fhc_t *fhc, int inr);
 #endif

 /branches/network/kernel/arch/sparc64/include/drivers/kbd.h
 ,8 → 41,7
 typedef enum {
     KBD_UNKNOWN,
     KBD_Z8530,
-    KBD_NS16550,
-    KBD_SGCN
+    KBD_NS16550
 } kbd_type_t;
 extern kbd_type_t kbd_type;

 /branches/network/kernel/arch/sparc64/include/drivers/ns16550.h
 ,0 → 1,102
+/*
+ * Copyright (c) 2006 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_sparc64_NS16550_H_
+#define KERN_sparc64_NS16550_H_
+#include <arch/types.h>
+#include <arch/drivers/kbd.h>
+/* NS16550 registers */
+#define RBR_REG     0    /** Receiver Buffer Register. */
+#define IER_REG     1   /** Interrupt Enable Register. */
+#define IIR_REG     2   /** Interrupt Ident Register (read). */
+#define FCR_REG     2   /** FIFO control register (write). */
+#define LCR_REG     3   /** Line Control register. */
+#define LSR_REG     5   /** Line Status Register. */
+#define IER_ERBFI   0x01    /** Enable Receive Buffer Full Interrupt. */
+#define LCR_DLAB    0x80    /** Divisor Latch Access bit. */
+/** Structure representing the ns16550 device. */
+typedef struct {
+    devno_t devno;
+    volatile uint8_t *reg;  /** Memory mapped registers of the ns16550. */
+} ns16550_t;
+static inline uint8_t ns16550_rbr_read(ns16550_t *dev)
+{
+    return dev->reg[RBR_REG];
+}
+static inline uint8_t ns16550_ier_read(ns16550_t *dev)
+{
+    return dev->reg[IER_REG];
+}
+static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v)
+{
+    dev->reg[IER_REG] = v;
+}
+static inline uint8_t ns16550_iir_read(ns16550_t *dev)
+{
+    return dev->reg[IIR_REG];
+}
+static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v)
+{
+    dev->reg[FCR_REG] = v;
+}
+static inline uint8_t ns16550_lcr_read(ns16550_t *dev)
+{
+    return dev->reg[LCR_REG];
+}
+static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v)
+{
+    dev->reg[LCR_REG] = v;
+}
+static inline uint8_t ns16550_lsr_read(ns16550_t *dev)
+{
+    return dev->reg[LSR_REG];
+}
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/sparc64/include/boot/boot.h
 ,12 → 48,9
 #define TASKMAP_MAX_RECORDS 32
 #define MEMMAP_MAX_RECORDS  32
-#define BOOTINFO_TASK_NAME_BUFLEN 32
 typedef struct {
     void * addr;
     uint32_t size;
-    char name[BOOTINFO_TASK_NAME_BUFLEN];
 } utask_t;
 typedef struct {

/branches/network/kernel/arch/sparc64/include/fpu_context.h
37,6 → 37,7

#include <arch/types.h>

#define ARCH_HAS_FPU
#define FPU_CONTEXT_ALIGN 8

typedef struct {

 /branches/network/kernel/arch/sparc64/include/regdef.h
 ,11 → 55,8
 #define WSTATE_NORMAL(n)    (n)
 #define WSTATE_OTHER(n)     ((n) << 3)
-/*
- * The following definitions concern the UPA_CONFIG register on US and the
- * FIREPLANE_CONFIG register on US3.
- */
-#define ICBUS_CONFIG_MID_SHIFT    17
+#define UPA_CONFIG_MID_SHIFT    17
+#define UPA_CONFIG_MID_MASK     0x1f
 #endif

 /branches/network/kernel/arch/sparc64/include/arch.h
 ,16 → 41,10
 #define ASI_AIUS        0x11    /** Access to secondary context with user privileges. */
 #define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
 #define ASI_DCACHE_TAG      0x47    /** ASI D-Cache Tag. */
-#define ASI_ICBUS_CONFIG        0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
+#define ASI_UPA_CONFIG      0x4a    /** ASI of the UPA_CONFIG register. */
 #define NWINDOWS        8   /** Number of register window sets. */
-#ifndef __ASM__
-extern void arch_pre_main(void);
-#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/register.h
 ,6 → 117,23
 };
 typedef union fprs_reg fprs_reg_t;
+/** UPA_CONFIG register.
+ *
+ * Note that format of this register differs significantly from
+ * processor version to version. The format defined here
+ * is the common subset for all supported processor versions.
+ */
+union upa_config {
+    uint64_t value;
+    struct {
+        uint64_t : 34;
+        unsigned pcon : 8;  /**< Processor configuration. */
+        unsigned mid : 5;   /**< Module (processor) ID register. */
+        unsigned pcap : 17; /**< Processor capabilities. */
+    } __attribute__ ((packed));
+};
+typedef union upa_config upa_config_t;
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/Makefile.inc
 ,6 → 29,10
 ## Toolchain configuration
 #
+ifndef CROSS_PREFIX
+    CROSS_PREFIX = /usr/local
+endif
 BFD_NAME = elf64-sparc
 BFD_ARCH = sparc
 BFD = binary
 ,55 → 46,80
 DEFS += -D__64_BITS__
-ifeq ($(PROCESSOR),us)
-    DEFS += -DUS
-endif
+## Own configuration directives
+#
-ifeq ($(PROCESSOR),us3)
-    DEFS += -DUS3
+## Compile with page hash table support.
+#
+CONFIG_PAGE_HT = y
+DEFS += -DCONFIG_PAGE_HT
+## Compile with support for address space identifiers.
+#
+CONFIG_ASID = y
+CONFIG_ASID_FIFO = y
+## Compile with support for framebuffer.
+#
+CONFIG_FB = y
+## Compile with support for Sun keyboard.
+#
+CONFIG_SUN_KBD = y
+## Compile with support for OpenFirmware device tree.
+#
+CONFIG_OFW_TREE = y
+ifeq ($(CONFIG_SMP),y)
+    DEFS += -DCONFIG_SMP
 endif
 ARCH_SOURCES = \
-    arch/$(KARCH)/src/cpu/cpu.c \
-    arch/$(KARCH)/src/asm.S \
-    arch/$(KARCH)/src/panic.S \
-    arch/$(KARCH)/src/console.c \
-    arch/$(KARCH)/src/context.S \
-    arch/$(KARCH)/src/fpu_context.c \
-    arch/$(KARCH)/src/dummy.s \
-    arch/$(KARCH)/src/mm/as.c \
-    arch/$(KARCH)/src/mm/cache.S \
-    arch/$(KARCH)/src/mm/frame.c \
-    arch/$(KARCH)/src/mm/page.c \
-    arch/$(KARCH)/src/mm/tlb.c \
-    arch/$(KARCH)/src/sparc64.c \
-    arch/$(KARCH)/src/start.S \
-    arch/$(KARCH)/src/proc/scheduler.c \
-    arch/$(KARCH)/src/proc/thread.c \
-    arch/$(KARCH)/src/trap/mmu.S \
-    arch/$(KARCH)/src/trap/trap_table.S \
-    arch/$(KARCH)/src/trap/trap.c \
-    arch/$(KARCH)/src/trap/exception.c \
-    arch/$(KARCH)/src/trap/interrupt.c \
-    arch/$(KARCH)/src/ddi/ddi.c \
-    arch/$(KARCH)/src/drivers/tick.c \
-    arch/$(KARCH)/src/drivers/kbd.c \
-    arch/$(KARCH)/src/drivers/sgcn.c \
-    arch/$(KARCH)/src/drivers/pci.c \
-    arch/$(KARCH)/src/drivers/fhc.c
+    arch/$(ARCH)/src/cpu/cpu.c \
+    arch/$(ARCH)/src/asm.S \
+    arch/$(ARCH)/src/panic.S \
+    arch/$(ARCH)/src/console.c \
+    arch/$(ARCH)/src/context.S \
+    arch/$(ARCH)/src/fpu_context.c \
+    arch/$(ARCH)/src/dummy.s \
+    arch/$(ARCH)/src/mm/as.c \
+    arch/$(ARCH)/src/mm/cache.S \
+    arch/$(ARCH)/src/mm/frame.c \
+    arch/$(ARCH)/src/mm/page.c \
+    arch/$(ARCH)/src/mm/tlb.c \
+    arch/$(ARCH)/src/sparc64.c \
+    arch/$(ARCH)/src/start.S \
+    arch/$(ARCH)/src/proc/scheduler.c \
+    arch/$(ARCH)/src/proc/thread.c \
+    arch/$(ARCH)/src/trap/mmu.S \
+    arch/$(ARCH)/src/trap/trap_table.S \
+    arch/$(ARCH)/src/trap/trap.c \
+    arch/$(ARCH)/src/trap/exception.c \
+    arch/$(ARCH)/src/trap/interrupt.c \
+    arch/$(ARCH)/src/ddi/ddi.c \
+    arch/$(ARCH)/src/drivers/tick.c \
+    arch/$(ARCH)/src/drivers/kbd.c \
+    arch/$(ARCH)/src/drivers/scr.c \
+    arch/$(ARCH)/src/drivers/pci.c
-ifeq ($(CONFIG_FB),y)
-    ARCH_SOURCES += \
-        arch/$(KARCH)/src/drivers/scr.c
-endif
 ifeq ($(CONFIG_SMP),y)
-    ARCH_SOURCES += \
-        arch/$(KARCH)/src/smp/ipi.c \
-        arch/$(KARCH)/src/smp/smp.c
+ARCH_SOURCES += \
+    arch/$(ARCH)/src/smp/ipi.c \
+    arch/$(ARCH)/src/smp/smp.c
 endif
 ifeq ($(CONFIG_TSB),y)
-    ARCH_SOURCES += \
-        arch/$(KARCH)/src/mm/tsb.c
+ARCH_SOURCES += \
+    arch/$(ARCH)/src/mm/tsb.c
 endif
+ifdef CONFIG_Z8530
+ARCH_SOURCES += \
+    arch/$(ARCH)/src/drivers/fhc.c
+endif

 /branches/network/kernel/arch/sparc64/src/mm/cache.S
 ,3 → 47,45
     retl
     ! beware SF Erratum #51, do not put the MEMBAR here
     nop
+/** Flush only D-cache lines of one virtual color.
+ *
+ * @param o0    Virtual color to be flushed.
+ */
+.global dcache_flush_color
+dcache_flush_color:
+    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
+    set DCACHE_SIZE / 2, %g2
+    sllx %g2, %o0, %g2
+    sub %g2, DCACHE_LINE_SIZE, %g2
+:  stxa %g0, [%g2] ASI_DCACHE_TAG
+    membar #Sync
+    subcc %g1, 1, %g1
+    bnz,pt %xcc, 0b
+    sub %g2, DCACHE_LINE_SIZE, %g2
+    retl
+    nop
+/** Flush only D-cache lines of one virtual color and one tag.
+ *
+ * @param o0    Virtual color to lookup the tag.
+ * @param o1    Tag of the cachelines to be flushed.
+ */
+.global dcache_flush_tag
+dcache_flush_tag:
+    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
+    set DCACHE_SIZE / 2, %g2
+    sllx %g2, %o0, %g2
+    sub %g2, DCACHE_LINE_SIZE, %g2
+:  ldxa [%g2] ASI_DCACHE_TAG, %g3
+    srlx %g3, DCACHE_TAG_SHIFT, %g3
+    cmp %g3, %o1
+    bnz 1f
+    nop
+    stxa %g0, [%g2] ASI_DCACHE_TAG
+    membar #Sync
+:  subcc %g1, 1, %g1
+    bnz,pt %xcc, 0b
+    sub %g2, DCACHE_LINE_SIZE, %g2
+    retl
+    nop

 /branches/network/kernel/arch/sparc64/src/mm/as.c
 ,25 → 164,7
     itsb_base_write(tsb_base.value);
     tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
     dtsb_base_write(tsb_base.value);
-#if defined (US3)
-    /*
-     * Clear the extension registers.
-     * In HelenOS, primary and secondary context registers contain
-     * equal values and kernel misses (context 0, ie. the nucleus context)
-     * are excluded from the TSB miss handler, so it makes no sense
-     * to have separate TSBs for primary, secondary and nucleus contexts.
-     * Clearing the extension registers will ensure that the value of the
-     * TSB Base register will be used as an address of TSB, making the code
-     * compatible with the US port.
-     */
-    itsb_primary_extension_write(0);
-    itsb_nucleus_extension_write(0);
-    dtsb_primary_extension_write(0);
-    dtsb_secondary_extension_write(0);
-    dtsb_nucleus_extension_write(0);
 #endif
-#endif
 }
 /** Perform sparc64-specific tasks when an address space is removed from the

 /branches/network/kernel/arch/sparc64/src/mm/tlb.c
 ,13 → 54,14
 #include <arch/mm/tsb.h>
 #endif
-static void dtlb_pte_copy(pte_t *, index_t, bool);
-static void itlb_pte_copy(pte_t *, index_t);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
-static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
-    const char *);
-static void do_fast_data_access_protection_fault(istate_t *,
-    tlb_tag_access_reg_t, const char *);
+static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
+static void itlb_pte_copy(pte_t *t, index_t index);
+static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
+    const char *str);
+static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
+    tlb_tag_access_reg_t tag, const char *str);
+static void do_fast_data_access_protection_fault(istate_t *istate,
+    tlb_tag_access_reg_t tag, const char *str);
 char *context_encoding[] = {
     "Primary",
 ,11 → 86,11
 /** Insert privileged mapping into DMMU TLB.
  *
- * @param page      Virtual page address.
- * @param frame     Physical frame address.
- * @param pagesize  Page size.
- * @param locked    True for permanent mappings, false otherwise.
- * @param cacheable True if the mapping is cacheable, false otherwise.
+ * @param page Virtual page address.
+ * @param frame Physical frame address.
+ * @param pagesize Page size.
+ * @param locked True for permanent mappings, false otherwise.
+ * @param cacheable True if the mapping is cacheable, false otherwise.
  */
 void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
     bool locked, bool cacheable)
 ,7 → 103,7
     pg.address = page;
     fr.address = frame;
-    tag.context = ASID_KERNEL;
+    tag.value = ASID_KERNEL;
     tag.vpn = pg.vpn;
     dtlb_tag_access_write(tag.value);
 ,10 → 126,10
 /** Copy PTE to TLB.
  *
- * @param t         Page Table Entry to be copied.
- * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
- * @param ro        If true, the entry will be created read-only, regardless
- *          of its w field.
+ * @param t     Page Table Entry to be copied.
+ * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param ro    If true, the entry will be created read-only, regardless of its
+ *      w field.
  */
 void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
 {
 ,8 → 165,8
 /** Copy PTE to ITLB.
  *
- * @param t     Page Table Entry to be copied.
- * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param t     Page Table Entry to be copied.
+ * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
  */
 void itlb_pte_copy(pte_t *t, index_t index)
 {
 ,11 → 235,10
  * Note that some faults (e.g. kernel faults) were already resolved by the
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param tag       Content of the TLB Tag Access register as it existed
- *          when the trap happened. This is to prevent confusion
- *          created by clobbered Tag Access register during a nested
- *          DTLB miss.
- * @param istate    Interrupted state saved on the stack.
+ * @param tag Content of the TLB Tag Access register as it existed when the
+ *    trap happened. This is to prevent confusion created by clobbered
+ *    Tag Access register during a nested DTLB miss.
+ * @param istate Interrupted state saved on the stack.
  */
 void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
 {
 ,11 → 287,10
 /** DTLB protection fault handler.
  *
- * @param tag       Content of the TLB Tag Access register as it existed
- *          when the trap happened. This is to prevent confusion
- *          created by clobbered Tag Access register during a nested
- *          DTLB miss.
- * @param istate    Interrupted state saved on the stack.
+ * @param tag Content of the TLB Tag Access register as it existed when the
+ *    trap happened. This is to prevent confusion created by clobbered
+ *    Tag Access register during a nested DTLB miss.
+ * @param istate Interrupted state saved on the stack.
  */
 void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
 {
 ,26 → 331,6
     }
 }
-/** Print TLB entry (for debugging purposes).
- *
- * The diag field has been left out in order to make this function more generic
- * (there is no diag field in US3 architeture).
- *
- * @param i     TLB entry number
- * @param t     TLB entry tag
- * @param d     TLB entry data
- */
-static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
-{
-    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
-        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
-        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
-        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
-}
-#if defined (US)
 /** Print contents of both TLBs. */
 void tlb_print(void)
 {
 ,7 → 342,12
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         t.value = itlb_tag_read_read(i);
-        print_tlb_entry(i, t, d);
+        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
+            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
+            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
+            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
+            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
     }
     printf("D-TLB contents:\n");
 ,63 → 354,22
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         t.value = dtlb_tag_read_read(i);
-        print_tlb_entry(i, t, d);
+        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
+            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
+            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
+            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
+            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
     }
-}
-#elif defined (US3)
-/** Print contents of all TLBs. */
-void tlb_print(void)
-{
-    int i;
-    tlb_data_t d;
-    tlb_tag_read_reg_t t;
-    printf("TLB_ISMALL contents:\n");
-    for (i = 0; i < tlb_ismall_size(); i++) {
-        d.value = dtlb_data_access_read(TLB_ISMALL, i);
-        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
-        print_tlb_entry(i, t, d);
-    }
-    printf("TLB_IBIG contents:\n");
-    for (i = 0; i < tlb_ibig_size(); i++) {
-        d.value = dtlb_data_access_read(TLB_IBIG, i);
-        t.value = dtlb_tag_read_read(TLB_IBIG, i);
-        print_tlb_entry(i, t, d);
-    }
-    printf("TLB_DSMALL contents:\n");
-    for (i = 0; i < tlb_dsmall_size(); i++) {
-        d.value = dtlb_data_access_read(TLB_DSMALL, i);
-        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
-        print_tlb_entry(i, t, d);
-    }
-    printf("TLB_DBIG_1 contents:\n");
-    for (i = 0; i < tlb_dbig_size(); i++) {
-        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
-        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
-        print_tlb_entry(i, t, d);
-    }
-    printf("TLB_DBIG_2 contents:\n");
-    for (i = 0; i < tlb_dbig_size(); i++) {
-        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
-        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
-        print_tlb_entry(i, t, d);
-    }
 }
-#endif
 void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
     const char *str)
 {
-    fault_if_from_uspace(istate, "%s.", str);
+    fault_if_from_uspace(istate, "%s\n", str);
     dump_istate(istate);
-    panic("%s.", str);
+    panic("%s\n", str);
 }
 void do_fast_data_access_mmu_miss_fault(istate_t *istate,
 ,12 → 379,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
             tag.context);
     }
     dump_istate(istate);
-    printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
-    panic("%s.", str);
+    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
+    panic("%s\n", str);
 }
 void do_fast_data_access_protection_fault(istate_t *istate,
 ,12 → 395,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
             tag.context);
     }
     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
     dump_istate(istate);
-    panic("%s.", str);
+    panic("%s\n", str);
 }
 void dump_sfsr_and_sfar(void)
 ,71 → 411,30
     sfsr.value = dtlb_sfsr_read();
     sfar = dtlb_sfar_read();
-#if defined (US)
     printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
         "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
         sfsr.ow, sfsr.fv);
-#elif defined (US3)
-    printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
-        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
-        sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
-#endif
     printf("DTLB SFAR: address=%p\n", sfar);
     dtlb_sfsr_write(0);
 }
-#if defined (US3)
-/** Invalidates given TLB entry if and only if it is non-locked or global.
- *
- * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
- *          TLB_ISMALL, TLB_IBIG).
- * @param entry     Entry index within the given TLB.
- */
-static void tlb_invalidate_entry(int tlb, index_t entry)
+/** Invalidate all unlocked ITLB and DTLB entries. */
+void tlb_invalidate_all(void)
 {
+    int i;
     tlb_data_t d;
     tlb_tag_read_reg_t t;
-    if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) {
-        d.value = dtlb_data_access_read(tlb, entry);
-        if (!d.l || d.g) {
-            t.value = dtlb_tag_read_read(tlb, entry);
-            d.v = false;
-            dtlb_tag_access_write(t.value);
-            dtlb_data_access_write(tlb, entry, d.value);
-        }
-    } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) {
-        d.value = itlb_data_access_read(tlb, entry);
-        if (!d.l || d.g) {
-            t.value = itlb_tag_read_read(tlb, entry);
-            d.v = false;
-            itlb_tag_access_write(t.value);
-            itlb_data_access_write(tlb, entry, d.value);
-        }
-    }
-}
-#endif
-/** Invalidate all unlocked ITLB and DTLB entries. */
-void tlb_invalidate_all(void)
-{
-    int i;
     /*
      * Walk all ITLB and DTLB entries and remove all unlocked mappings.
      *
      * The kernel doesn't use global mappings so any locked global mappings
-     * found must have been created by someone else. Their only purpose now
+     * found  must have been created by someone else. Their only purpose now
      * is to collide with proper mappings. Invalidate immediately. It should
      * be safe to invalidate them as late as now.
      */
-#if defined (US)
-    tlb_data_t d;
-    tlb_tag_read_reg_t t;
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         if (!d.l || d.g) {
 ,7 → 444,7
             itlb_data_access_write(i, d.value);
         }
     }
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         if (!d.l || d.g) {
 ,21 → 454,7
             dtlb_data_access_write(i, d.value);
         }
     }
-#elif defined (US3)
-    for (i = 0; i < tlb_ismall_size(); i++)
-        tlb_invalidate_entry(TLB_ISMALL, i);
-    for (i = 0; i < tlb_ibig_size(); i++)
-        tlb_invalidate_entry(TLB_IBIG, i);
-    for (i = 0; i < tlb_dsmall_size(); i++)
-        tlb_invalidate_entry(TLB_DSMALL, i);
-    for (i = 0; i < tlb_dbig_size(); i++)
-        tlb_invalidate_entry(TLB_DBIG_0, i);
-    for (i = 0; i < tlb_dbig_size(); i++)
-        tlb_invalidate_entry(TLB_DBIG_1, i);
-#endif
 }
 /** Invalidate all ITLB and DTLB entries that belong to specified ASID
 ,9 → 484,9
 /** Invalidate all ITLB and DTLB entries for specified page range in specified
  * address space.
  *
- * @param asid      Address Space ID.
- * @param page      First page which to sweep out from ITLB and DTLB.
- * @param cnt       Number of ITLB and DTLB entries to invalidate.
+ * @param asid Address Space ID.
+ * @param page First page which to sweep out from ITLB and DTLB.
+ * @param cnt Number of ITLB and DTLB entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 {

 /branches/network/kernel/arch/sparc64/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,6 → 79,7
          */
         frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1);
     }
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/mm/page.c
 ,5 → 1,5
 /*
- * Copyright (c) 2009 Jakub Jermar
+ * Copyright (c) 2005 Jakub Jermar
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,27 → 42,126
 #include <align.h>
 #include <config.h>
+#ifdef CONFIG_SMP
+/** Entries locked in DTLB of BSP.
+ *
+ * Application processors need to have the same locked entries in their DTLBs as
+ * the bootstrap processor.
+ */
+static struct {
+    uintptr_t virt_page;
+    uintptr_t phys_page;
+    int pagesize_code;
+} bsp_locked_dtlb_entry[DTLB_ENTRY_COUNT];
+/** Number of entries in bsp_locked_dtlb_entry array. */
+static count_t bsp_locked_dtlb_entries = 0;
+#endif /* CONFIG_SMP */
 /** Perform sparc64 specific initialization of paging. */
 void page_arch_init(void)
 {
-    if (config.cpu_active == 1)
+    if (config.cpu_active == 1) {
         page_mapping_operations = &ht_mapping_operations;
+    } else {
+#ifdef CONFIG_SMP
+        unsigned int i;
+        /*
+         * Copy locked DTLB entries from the BSP.
+         */
+        for (i = 0; i < bsp_locked_dtlb_entries; i++) {
+            dtlb_insert_mapping(bsp_locked_dtlb_entry[i].virt_page,
+                bsp_locked_dtlb_entry[i].phys_page,
+                bsp_locked_dtlb_entry[i].pagesize_code, true,
+                false);
+        }
+#endif
+    }
 }
 /** Map memory-mapped device into virtual memory.
  *
- * We are currently using identity mapping for mapping device registers.
+ * So far, only DTLB is used to map devices into memory. Chances are that there
+ * will be only a limited amount of devices that the kernel itself needs to
+ * lock in DTLB.
  *
- * @param physaddr  Physical address of the page where the device is
- *          located.
- * @param size      Size of the device's registers. This argument is
- *          ignored.
+ * @param physaddr Physical address of the page where the device is located.
+ *  Must be at least page-aligned.
+ * @param size Size of the device's registers. Must not exceed 4M and must
+ *  include extra space caused by the alignment.
  *
- * @return      Virtual address of the page where the device is mapped.
+ * @return Virtual address of the page where the device is mapped.
  */
 uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
-    return PA2KA(physaddr);
+    unsigned int order;
+    unsigned int i;
+    ASSERT(config.cpu_active == 1);
+    struct {
+        int pagesize_code;
+        size_t increment;
+        count_t count;
+    } sizemap[] = {
+        { PAGESIZE_8K, 0, 1 },              /* 8K */
+        { PAGESIZE_8K, MMU_PAGE_SIZE, 2 },      /* 16K */
+        { PAGESIZE_8K, MMU_PAGE_SIZE, 4 },      /* 32K */
+        { PAGESIZE_64K, 0, 1},              /* 64K */
+        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 2 },     /* 128K */
+        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 4 },     /* 256K */
+        { PAGESIZE_512K, 0, 1 },            /* 512K */
+        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 2 },   /* 1M */
+        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 4 },   /* 2M */
+        { PAGESIZE_4M, 0, 1 },              /* 4M */
+        { PAGESIZE_4M, 512 * MMU_PAGE_SIZE, 2 }     /* 8M */
+    };
+    ASSERT(ALIGN_UP(physaddr, MMU_PAGE_SIZE) == physaddr);
+    ASSERT(size <= 8 * 1024 * 1024);
+    if (size <= MMU_FRAME_SIZE)
+        order = 0;
+    else
+        order = (fnzb64(size - 1) + 1) - MMU_FRAME_WIDTH;
+    /*
+     * Use virtual addresses that are beyond the limit of physical memory.
+     * Thus, the physical address space will not be wasted by holes created
+     * by frame_alloc().
+     */
+    ASSERT(PA2KA(last_frame));
+    uintptr_t virtaddr = ALIGN_UP(PA2KA(last_frame),
+<< (order + FRAME_WIDTH));
+    last_frame = ALIGN_UP(KA2PA(virtaddr) + size,
+<< (order + FRAME_WIDTH));
+    for (i = 0; i < sizemap[order].count; i++) {
+        /*
+         * First, insert the mapping into DTLB.
+         */
+        dtlb_insert_mapping(virtaddr + i * sizemap[order].increment,
+            physaddr + i * sizemap[order].increment,
+            sizemap[order].pagesize_code, true, false);
+#ifdef CONFIG_SMP
+        /*
+         * Second, save the information about the mapping for APs.
+         */
+        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].virt_page =
+            virtaddr + i * sizemap[order].increment;
+        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].phys_page =
+            physaddr + i * sizemap[order].increment;
+        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].pagesize_code =
+            sizemap[order].pagesize_code;
+        bsp_locked_dtlb_entries++;
+#endif
+    }
+    return virtaddr;
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/mm/tsb.c
 ,9 → 112,9
     tsb->data.value = 0;
     tsb->data.size = PAGESIZE_8K;
     tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-    tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
-    tsb->data.p = t->k; /* p as privileged, k as kernel */
-    tsb->data.v = t->p; /* v as valid, p as present */
+    tsb->data.cp = t->c;
+    tsb->data.p = t->k;     /* p as privileged */
+    tsb->data.v = t->p;
     write_barrier();
 ,4 → 173,3
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/smp/smp.c
 ,7 → 35,6
 #include <smp/smp.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <cpu.h>
-#include <arch/cpu_family.h>
 #include <arch/cpu.h>
 #include <arch.h>
 #include <config.h>
 ,7 → 43,6
 #include <synch/synch.h>
 #include <synch/waitq.h>
 #include <print.h>
-#include <arch/cpu_node.h>
 /**
  * This global variable is used to pick-up application processors
 ,55 → 61,15
     ofw_tree_node_t *node;
     count_t cnt = 0;
-    if (is_us() || is_us_iii()) {
-        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
-        while (node) {
-            cnt++;
-            node = ofw_tree_find_peer_by_device_type(node, "cpu");
-        }
-    } else if (is_us_iv()) {
-        node = ofw_tree_find_child(cpus_parent(), "cmp");
-        while (node) {
-            cnt += 2;
-            node = ofw_tree_find_peer_by_name(node, "cmp");
-        }
+    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
+    while (node) {
+        cnt++;
+        node = ofw_tree_find_peer_by_device_type(node, "cpu");
     }
     config.cpu_count = max(1, cnt);
 }
-/**
- * Wakes up the CPU which is represented by the "node" OFW tree node.
- * If "node" represents the current CPU, calling the function has
- * no effect.
- */
-static void wakeup_cpu(ofw_tree_node_t *node)
-{
-    uint32_t mid;
-    ofw_tree_property_t *prop;
-    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
-    prop = ofw_tree_getprop(node, "upa-portid");
-    if ((!prop) || (!prop->value))
-        prop = ofw_tree_getprop(node, "portid");
-    if ((!prop) || (!prop->value))
-        prop = ofw_tree_getprop(node, "cpuid");
-    if (!prop || prop->value == NULL)
-        return;
-    mid = *((uint32_t *) prop->value);
-    if (CPU->arch.mid == mid)
-        return;
-    waking_up_mid = mid;
-    if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) ==
-        ESYNCH_TIMEOUT)
-        printf("%s: waiting for processor (mid = %" PRIu32
-            ") timed out\n", __func__, mid);
-}
 /** Wake application processors up. */
 void kmp(void *arg)
 {
 ,18 → 76,31
     ofw_tree_node_t *node;
     int i;
-    if (is_us() || is_us_iii()) {
-        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
-        for (i = 0; node;
-                     node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++)
-            wakeup_cpu(node);
-    } else if (is_us_iv()) {
-        node = ofw_tree_find_child(cpus_parent(), "cmp");
-        while (node) {
-            wakeup_cpu(ofw_tree_find_child(node, "cpu@0"));
-            wakeup_cpu(ofw_tree_find_child(node, "cpu@1"));
-            node = ofw_tree_find_peer_by_name(node, "cmp");
+    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
+    for (i = 0; node; node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++) {
+        uint32_t mid;
+        ofw_tree_property_t *prop;
+        prop = ofw_tree_getprop(node, "upa-portid");
+        if (!prop || !prop->value)
+            continue;
+        mid = *((uint32_t *) prop->value);
+        if (CPU->arch.mid == mid) {
+            /*
+             * Skip the current CPU.
+             */
+            continue;
         }
+        /*
+         * Processor with ID == mid can proceed with its initialization.
+         */
+        waking_up_mid = mid;
+        if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT)
+            printf("%s: waiting for processor (mid = %" PRIu32 ") timed out\n",
+                __func__, mid);
     }
 }

 /branches/network/kernel/arch/sparc64/src/smp/ipi.c
 ,33 → 46,6
 #include <time/delay.h>
 #include <panic.h>
-/** Set the contents of the outgoing interrupt vector data.
- *
- * The first data item (data 0) will be set to the value of func, the
- * rest of the vector will contain zeros.
- *
- * This is a helper function used from within the cross_call function.
- *
- * @param func value the first data item of the vector will be set to
- */
-static inline void set_intr_w_data(void (* func)(void))
-{
-#if defined (US)
-    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
-    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
-    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
-#elif defined (US3)
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
-    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
-#endif
-}
 /** Invoke function on another processor.
  *
  * Currently, only functions without arguments are supported.
 ,15 → 71,16
     status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
     if (status & INTR_DISPATCH_STATUS_BUSY)
-        panic("Interrupt Dispatch Status busy bit set.");
+        panic("Interrupt Dispatch Status busy bit set\n");
-    ASSERT(!(pstate_read() & PSTATE_IE_BIT));
     do {
-        set_intr_w_data(func);
-        asi_u64_write(ASI_INTR_W,
+        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0,
+            (uintptr_t) func);
+        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
+        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
+        asi_u64_write(ASI_UDB_INTR_W,
             (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
-            VA_INTR_W_DISPATCH, 0);
+            ASI_UDB_INTR_W_DISPATCH, 0);
         membar();
 ,7 → 125,7
         func = tlb_shootdown_ipi_recv;
         break;
     default:
-        panic("Unknown IPI (%d).", ipi);
+        panic("Unknown IPI (%d).\n", ipi);
         break;
     }

 /branches/network/kernel/arch/sparc64/src/trap/exception.c
 ,67 → 40,62
 #include <arch/asm.h>
 #include <arch/register.h>
 #include <debug.h>
+#include <symtab.h>
 #include <print.h>
-#include <symtab.h>
 void dump_istate(istate_t *istate)
 {
-    char *tpcs, *tnpcs;
-    tpcs = symtab_fmt_name_lookup(istate->tpc);
-    tnpcs = symtab_fmt_name_lookup(istate->tnpc);
     printf("TSTATE=%#" PRIx64 "\n", istate->tstate);
-    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, tpcs);
-    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, tnpcs);
+    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, get_symtab_entry(istate->tpc));
+    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, get_symtab_entry(istate->tnpc));
 }
 /** Handle instruction_access_exception. (0x8) */
 void instruction_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle instruction_access_error. (0xa) */
 void instruction_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle illegal_instruction. (0x10) */
 void illegal_instruction(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle privileged_opcode. (0x11) */
 void privileged_opcode(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle unimplemented_LDD. (0x12) */
 void unimplemented_LDD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle unimplemented_STD. (0x13) */
 void unimplemented_STD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle fp_disabled. (0x20) */
 ,9 → 113,9
 #ifdef CONFIG_FPU_LAZY
     scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 #endif
 }
 ,98 → 122,98
 /** Handle fp_exception_ieee_754. (0x21) */
 void fp_exception_ieee_754(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle fp_exception_other. (0x22) */
 void fp_exception_other(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle tag_overflow. (0x23) */
 void tag_overflow(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle division_by_zero. (0x28) */
 void division_by_zero(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle data_access_exception. (0x30) */
 void data_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
     dump_sfsr_and_sfar();
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle data_access_error. (0x32) */
 void data_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle mem_address_not_aligned. (0x34) */
 void mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle LDDF_mem_address_not_aligned. (0x35) */
 void LDDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle STDF_mem_address_not_aligned. (0x36) */
 void STDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle privileged_action. (0x37) */
 void privileged_action(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle LDQF_mem_address_not_aligned. (0x38) */
 void LDQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** Handle STQF_mem_address_not_aligned. (0x39) */
 void STQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s.", __func__);
+    fault_if_from_uspace(istate, "%s\n", __func__);
     dump_istate(istate);
-    panic("%s.", __func__);
+    panic("%s\n", __func__);
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/trap/interrupt.c
 ,19 → 67,11
  */
 void interrupt(int n, istate_t *istate)
 {
-    uint64_t status;
     uint64_t intrcv;
     uint64_t data0;
-    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
-    if (status & (!INTR_DISPATCH_STATUS_BUSY))
-        panic("Interrupt Dispatch Status busy bit not set.");
     intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
-#if defined (US)
-    data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0);
-#elif defined (US3)
-    data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
-#endif
+    data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
     irq_t *irq = irq_dispatch_and_lock(data0);
     if (irq) {
 ,13 → 78,7
         /*
          * The IRQ handler was found.
          */
-        irq->handler(irq);
-        /*
-         * See if there is a clear-interrupt-routine and call it.
-         */
-        if (irq->cir) {
-            irq->cir(irq->cir_arg, irq->inr);
-        }
+        irq->handler(irq, irq->arg);
         spinlock_unlock(&irq->lock);
     } else if (data0 > config.base) {
         /*
 ,7 → 98,7
          */
 #ifdef CONFIG_DEBUG
         printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64
-            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
+            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
 #endif
     }

 /branches/network/kernel/arch/sparc64/src/trap/trap_table.S
 ,22 → 329,198
 fill_1_normal_tl0:
     FILL_NORMAL_HANDLER_USERSPACE
-/* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */
-.irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\
-, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\
-, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\
-, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\
-, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\
-, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\
-, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\
-.org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE
-.global trap_instruction_\cur\()_tl0
-trap_instruction_\cur\()_tl0:
-    ba trap_instruction_handler
-    mov \cur, %g2
-.endr
+/* TT = 0x100, TL = 0, trap_instruction_0 */
+.org trap_table + TT_TRAP_INSTRUCTION(0)*ENTRY_SIZE
+.global trap_instruction_0_tl0
+trap_instruction_0_tl0:
+    TRAP_INSTRUCTION 0
+/* TT = 0x101, TL = 0, trap_instruction_1 */
+.org trap_table + TT_TRAP_INSTRUCTION(1)*ENTRY_SIZE
+.global trap_instruction_1_tl0
+trap_instruction_1_tl0:
+    TRAP_INSTRUCTION 1
+/* TT = 0x102, TL = 0, trap_instruction_2 */
+.org trap_table + TT_TRAP_INSTRUCTION(2)*ENTRY_SIZE
+.global trap_instruction_2_tl0
+trap_instruction_2_tl0:
+    TRAP_INSTRUCTION 2
+/* TT = 0x103, TL = 0, trap_instruction_3 */
+.org trap_table + TT_TRAP_INSTRUCTION(3)*ENTRY_SIZE
+.global trap_instruction_3_tl0
+trap_instruction_3_tl0:
+    TRAP_INSTRUCTION 3
+/* TT = 0x104, TL = 0, trap_instruction_4 */
+.org trap_table + TT_TRAP_INSTRUCTION(4)*ENTRY_SIZE
+.global trap_instruction_4_tl0
+trap_instruction_4_tl0:
+    TRAP_INSTRUCTION 4
+/* TT = 0x105, TL = 0, trap_instruction_5 */
+.org trap_table + TT_TRAP_INSTRUCTION(5)*ENTRY_SIZE
+.global trap_instruction_5_tl0
+trap_instruction_5_tl0:
+    TRAP_INSTRUCTION 5
+/* TT = 0x106, TL = 0, trap_instruction_6 */
+.org trap_table + TT_TRAP_INSTRUCTION(6)*ENTRY_SIZE
+.global trap_instruction_6_tl0
+trap_instruction_6_tl0:
+    TRAP_INSTRUCTION 6
+/* TT = 0x107, TL = 0, trap_instruction_7 */
+.org trap_table + TT_TRAP_INSTRUCTION(7)*ENTRY_SIZE
+.global trap_instruction_7_tl0
+trap_instruction_7_tl0:
+    TRAP_INSTRUCTION 7
+/* TT = 0x108, TL = 0, trap_instruction_8 */
+.org trap_table + TT_TRAP_INSTRUCTION(8)*ENTRY_SIZE
+.global trap_instruction_8_tl0
+trap_instruction_8_tl0:
+    TRAP_INSTRUCTION 8
+/* TT = 0x109, TL = 0, trap_instruction_9 */
+.org trap_table + TT_TRAP_INSTRUCTION(9)*ENTRY_SIZE
+.global trap_instruction_9_tl0
+trap_instruction_9_tl0:
+    TRAP_INSTRUCTION 9
+/* TT = 0x10a, TL = 0, trap_instruction_10 */
+.org trap_table + TT_TRAP_INSTRUCTION(10)*ENTRY_SIZE
+.global trap_instruction_10_tl0
+trap_instruction_10_tl0:
+    TRAP_INSTRUCTION 10
+/* TT = 0x10b, TL = 0, trap_instruction_11 */
+.org trap_table + TT_TRAP_INSTRUCTION(11)*ENTRY_SIZE
+.global trap_instruction_11_tl0
+trap_instruction_11_tl0:
+    TRAP_INSTRUCTION 11
+/* TT = 0x10c, TL = 0, trap_instruction_12 */
+.org trap_table + TT_TRAP_INSTRUCTION(12)*ENTRY_SIZE
+.global trap_instruction_12_tl0
+trap_instruction_12_tl0:
+    TRAP_INSTRUCTION 12
+/* TT = 0x10d, TL = 0, trap_instruction_13 */
+.org trap_table + TT_TRAP_INSTRUCTION(13)*ENTRY_SIZE
+.global trap_instruction_13_tl0
+trap_instruction_13_tl0:
+    TRAP_INSTRUCTION 13
+/* TT = 0x10e, TL = 0, trap_instruction_14 */
+.org trap_table + TT_TRAP_INSTRUCTION(14)*ENTRY_SIZE
+.global trap_instruction_14_tl0
+trap_instruction_14_tl0:
+    TRAP_INSTRUCTION 14
+/* TT = 0x10f, TL = 0, trap_instruction_15 */
+.org trap_table + TT_TRAP_INSTRUCTION(15)*ENTRY_SIZE
+.global trap_instruction_15_tl0
+trap_instruction_15_tl0:
+    TRAP_INSTRUCTION 15
+/* TT = 0x110, TL = 0, trap_instruction_16 */
+.org trap_table + TT_TRAP_INSTRUCTION(16)*ENTRY_SIZE
+.global trap_instruction_16_tl0
+trap_instruction_16_tl0:
+    TRAP_INSTRUCTION 16
+/* TT = 0x111, TL = 0, trap_instruction_17 */
+.org trap_table + TT_TRAP_INSTRUCTION(17)*ENTRY_SIZE
+.global trap_instruction_17_tl0
+trap_instruction_17_tl0:
+    TRAP_INSTRUCTION 17
+/* TT = 0x112, TL = 0, trap_instruction_18 */
+.org trap_table + TT_TRAP_INSTRUCTION(18)*ENTRY_SIZE
+.global trap_instruction_18_tl0
+trap_instruction_18_tl0:
+    TRAP_INSTRUCTION 18
+/* TT = 0x113, TL = 0, trap_instruction_19 */
+.org trap_table + TT_TRAP_INSTRUCTION(19)*ENTRY_SIZE
+.global trap_instruction_19_tl0
+trap_instruction_19_tl0:
+    TRAP_INSTRUCTION 19
+/* TT = 0x114, TL = 0, trap_instruction_20 */
+.org trap_table + TT_TRAP_INSTRUCTION(20)*ENTRY_SIZE
+.global trap_instruction_20_tl0
+trap_instruction_20_tl0:
+    TRAP_INSTRUCTION 20
+/* TT = 0x115, TL = 0, trap_instruction_21 */
+.org trap_table + TT_TRAP_INSTRUCTION(21)*ENTRY_SIZE
+.global trap_instruction_21_tl0
+trap_instruction_21_tl0:
+    TRAP_INSTRUCTION 21
+/* TT = 0x116, TL = 0, trap_instruction_22 */
+.org trap_table + TT_TRAP_INSTRUCTION(22)*ENTRY_SIZE
+.global trap_instruction_22_tl0
+trap_instruction_22_tl0:
+    TRAP_INSTRUCTION 22
+/* TT = 0x117, TL = 0, trap_instruction_23 */
+.org trap_table + TT_TRAP_INSTRUCTION(23)*ENTRY_SIZE
+.global trap_instruction_23_tl0
+trap_instruction_23_tl0:
+    TRAP_INSTRUCTION 23
+/* TT = 0x118, TL = 0, trap_instruction_24 */
+.org trap_table + TT_TRAP_INSTRUCTION(24)*ENTRY_SIZE
+.global trap_instruction_24_tl0
+trap_instruction_24_tl0:
+    TRAP_INSTRUCTION 24
+/* TT = 0x119, TL = 0, trap_instruction_25 */
+.org trap_table + TT_TRAP_INSTRUCTION(25)*ENTRY_SIZE
+.global trap_instruction_25_tl0
+trap_instruction_25_tl0:
+    TRAP_INSTRUCTION 25
+/* TT = 0x11a, TL = 0, trap_instruction_26 */
+.org trap_table + TT_TRAP_INSTRUCTION(26)*ENTRY_SIZE
+.global trap_instruction_26_tl0
+trap_instruction_26_tl0:
+    TRAP_INSTRUCTION 26
+/* TT = 0x11b, TL = 0, trap_instruction_27 */
+.org trap_table + TT_TRAP_INSTRUCTION(27)*ENTRY_SIZE
+.global trap_instruction_27_tl0
+trap_instruction_27_tl0:
+    TRAP_INSTRUCTION 27
+/* TT = 0x11c, TL = 0, trap_instruction_28 */
+.org trap_table + TT_TRAP_INSTRUCTION(28)*ENTRY_SIZE
+.global trap_instruction_28_tl0
+trap_instruction_28_tl0:
+    TRAP_INSTRUCTION 28
+/* TT = 0x11d, TL = 0, trap_instruction_29 */
+.org trap_table + TT_TRAP_INSTRUCTION(29)*ENTRY_SIZE
+.global trap_instruction_29_tl0
+trap_instruction_29_tl0:
+    TRAP_INSTRUCTION 29
+/* TT = 0x11e, TL = 0, trap_instruction_30 */
+.org trap_table + TT_TRAP_INSTRUCTION(30)*ENTRY_SIZE
+.global trap_instruction_30_tl0
+trap_instruction_30_tl0:
+    TRAP_INSTRUCTION 30
+/* TT = 0x11f, TL = 0, trap_instruction_31 */
+.org trap_table + TT_TRAP_INSTRUCTION(31)*ENTRY_SIZE
+.global trap_instruction_31_tl0
+trap_instruction_31_tl0:
+    TRAP_INSTRUCTION 31
 /*
  * Handlers for TL>0.
  */
 ,10 → 782,10
     add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
 .else
     /*
-     * Call the higher-level syscall handler and enable interrupts.
+     * Call the higher-level syscall handler.
      */
     call syscall_handler
-    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT | PSTATE_IE_BIT, %pstate
+    nop
     mov %o0, %i0                ! copy the value returned by the syscall
 .endif
 ,8 → 924,9
      * Fill all windows stored in the buffer.
      */
     clr %g4
-:  andcc %g7, UWB_ALIGNMENT - 1, %g0   ! alignment check
-    bz 0f                   ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill
+    set PAGE_SIZE - 1, %g5
+:  andcc %g7, %g5, %g0         ! PAGE_SIZE alignment check
+    bz 0f                   ! %g7 is page-aligned, no more windows to refill
     nop
     add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7

 /branches/network/kernel/arch/sparc64/src/cpu/cpu.c
 ,46 → 32,12
 /** @file
  */
-#include <arch/cpu_family.h>
 #include <cpu.h>
 #include <arch.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <arch/drivers/tick.h>
 #include <print.h>
-#include <arch/cpu_node.h>
-/**
- * Finds out the clock frequency of the current CPU.
- *
- * @param node  node representing the current CPU in the OFW tree
- * @return  clock frequency if "node" is the current CPU and no error
- *      occurs, -1 if "node" is not the current CPU or on error
- */
-static int find_cpu_frequency(ofw_tree_node_t *node)
-{
-    ofw_tree_property_t *prop;
-    uint32_t mid;
-    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
-    prop = ofw_tree_getprop(node, "upa-portid");
-    if ((!prop) || (!prop->value))
-        prop = ofw_tree_getprop(node, "portid");
-    if ((!prop) || (!prop->value))
-        prop = ofw_tree_getprop(node, "cpuid");
-    if (prop && prop->value) {
-        mid = *((uint32_t *) prop->value);
-        if (mid == CPU->arch.mid) {
-            prop = ofw_tree_getprop(node, "clock-frequency");
-            if (prop && prop->value) {
-                return *((uint32_t *) prop->value);
-            }
-        }
-    }
-    return -1;
-}
 /** Perform sparc64 specific initialization of the processor structure for the
  * current processor.
  */
 ,37 → 44,34
 void cpu_arch_init(void)
 {
     ofw_tree_node_t *node;
+    uint32_t mid;
     uint32_t clock_frequency = 0;
+    upa_config_t upa_config;
-    CPU->arch.mid = read_mid();
+    upa_config.value = upa_config_read();
+    CPU->arch.mid = upa_config.mid;
     /*
      * Detect processor frequency.
      */
-    if (is_us() || is_us_iii()) {
-        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
-        while (node) {
-            int f = find_cpu_frequency(node);
-            if (f != -1)
-                clock_frequency = (uint32_t) f;
-            node = ofw_tree_find_peer_by_device_type(node, "cpu");
+    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
+    while (node) {
+        ofw_tree_property_t *prop;
+        prop = ofw_tree_getprop(node, "upa-portid");
+        if (prop && prop->value) {
+            mid = *((uint32_t *) prop->value);
+            if (mid == CPU->arch.mid) {
+                prop = ofw_tree_getprop(node,
+                    "clock-frequency");
+                if (prop && prop->value)
+                    clock_frequency = *((uint32_t *)
+                        prop->value);
+            }
         }
-    } else if (is_us_iv()) {
-        node = ofw_tree_find_child(cpus_parent(), "cmp");
-        while (node) {
-            int f;
-            f = find_cpu_frequency(
-                ofw_tree_find_child(node, "cpu@0"));
-            if (f != -1)
-                clock_frequency = (uint32_t) f;
-            f = find_cpu_frequency(
-                ofw_tree_find_child(node, "cpu@1"));
-            if (f != -1)
-                clock_frequency = (uint32_t) f;
-            node = ofw_tree_find_peer_by_name(node, "cmp");
-        }
+        node = ofw_tree_find_peer_by_device_type(node, "cpu");
     }
     CPU->arch.clock_frequency = clock_frequency;
     tick_init();
 }
 ,15 → 124,6
     case IMPL_ULTRASPARCIII:
         impl = "UltraSPARC III";
         break;
-    case IMPL_ULTRASPARCIII_PLUS:
-        impl = "UltraSPARC III+";
-        break;
-    case IMPL_ULTRASPARCIII_I:
-        impl = "UltraSPARC IIIi";
-        break;
-    case IMPL_ULTRASPARCIV:
-        impl = "UltraSPARC IV";
-        break;
     case IMPL_ULTRASPARCIV_PLUS:
         impl = "UltraSPARC IV+";
         break;

/branches/network/kernel/arch/sparc64/src/drivers/sgcn.c
File deleted

 /branches/network/kernel/arch/sparc64/src/drivers/scr.c
 ,7 → 37,7
 #include <genarch/fb/fb.h>
 #include <genarch/fb/visuals.h>
 #include <arch/types.h>
-#include <string.h>
+#include <func.h>
 #include <align.h>
 #include <print.h>
 ,10 → 55,6
 void scr_init(ofw_tree_node_t *node)
 {
     ofw_tree_property_t *prop;
-    ofw_pci_reg_t *pci_reg;
-    ofw_pci_reg_t pci_abs_reg;
-    ofw_upa_reg_t *upa_reg;
-    ofw_sbus_reg_t *sbus_reg;
     const char *name;
     name = ofw_tree_node_name(node);
 ,8 → 61,6
     if (strcmp(name, "SUNW,m64B") == 0)
         scr_type = SCR_ATYFB;
-    else if (strcmp(name, "SUNW,XVR-100") == 0)
-        scr_type = SCR_XVR;
     else if (strcmp(name, "SUNW,ffb") == 0)
         scr_type = SCR_FFB;
     else if (strcmp(name, "cgsix") == 0)
 ,12 → 67,11
         scr_type = SCR_CGSIX;
     if (scr_type == SCR_UNKNOWN) {
-        printf("Unknown screen device.\n");
+        printf("Unknown keyboard device.\n");
         return;
     }
     uintptr_t fb_addr;
-    unsigned int fb_offset = 0;
     uint32_t fb_width = 0;
     uint32_t fb_height = 0;
     uint32_t fb_depth = 0;
 ,7 → 97,7
     prop = ofw_tree_getprop(node, "reg");
     if (!prop)
-        panic("Cannot find 'reg' property.");
+        panic("Can't find \"reg\" property.\n");
     switch (scr_type) {
     case SCR_ATYFB:
 ,15 → 106,15
             return;
         }
-        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
+        ofw_pci_reg_t *fb_reg = &((ofw_pci_reg_t *) prop->value)[1];
+        ofw_pci_reg_t abs_reg;
-        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
+        if (!ofw_pci_reg_absolutize(node, fb_reg, &abs_reg)) {
             printf("Failed to absolutize fb register.\n");
             return;
         }
-        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
-            &fb_addr)) {
+        if (!ofw_pci_apply_ranges(node->parent, &abs_reg , &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,56 → 142,12
         }
         break;
-    case SCR_XVR:
-        if (prop->size / sizeof(ofw_pci_reg_t) < 2) {
-            printf("Too few screen registers.\n");
-            return;
-        }
-        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
-        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
-            printf("Failed to absolutize fb register.\n");
-            return;
-        }
-        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
-            &fb_addr)) {
-            printf("Failed to determine screen address.\n");
-            return;
-        }
-        fb_offset = 4 * 0x2000;
-        switch (fb_depth) {
-        case 8:
-            fb_scanline = fb_linebytes * (fb_depth >> 3);
-            visual = VISUAL_INDIRECT_8;
-            break;
-        case 16:
-            fb_scanline = fb_linebytes * (fb_depth >> 3);
-            visual = VISUAL_RGB_5_6_5;
-            break;
-        case 24:
-            fb_scanline = fb_linebytes * 4;
-            visual = VISUAL_RGB_8_8_8_0;
-            break;
-        case 32:
-            fb_scanline = fb_linebytes * (fb_depth >> 3);
-            visual = VISUAL_RGB_0_8_8_8;
-            break;
-        default:
-            printf("Unsupported bits per pixel.\n");
-            return;
-        }
-        break;
     case SCR_FFB:
         fb_scanline = 8192;
         visual = VISUAL_BGR_0_8_8_8;
-        upa_reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
-        if (!ofw_upa_apply_ranges(node->parent, upa_reg, &fb_addr)) {
+        ofw_upa_reg_t *reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
+        if (!ofw_upa_apply_ranges(node->parent, reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,8 → 164,8
             return;
         }
-        sbus_reg = &((ofw_sbus_reg_t *) prop->value)[0];
-        if (!ofw_sbus_apply_ranges(node->parent, sbus_reg, &fb_addr)) {
+        ofw_sbus_reg_t *cg6_reg = &((ofw_sbus_reg_t *) prop->value)[0];
+        if (!ofw_sbus_apply_ranges(node->parent, cg6_reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,24 → 172,11
         break;
     default:
-        panic("Unexpected type.");
+        panic("Unexpected type.\n");
     }
-    fb_properties_t props = {
-        .addr = fb_addr,
-        .offset = fb_offset,
-        .x = fb_width,
-        .y = fb_height,
-        .scan = fb_scanline,
-        .visual = visual,
-    };
-    fb_init(&props);
+    fb_init(fb_addr, fb_width, fb_height, fb_scanline, visual);
 }
-void scr_redraw(void)
-{
-    fb_redraw();
-}
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/drivers/tick.c
 ,12 → 45,11
 #define TICK_RESTART_TIME   50  /* Worst case estimate. */
-/** Initialize tick and stick interrupt. */
+/** Initialize tick interrupt. */
 void tick_init(void)
 {
-    /* initialize TICK interrupt */
     tick_compare_reg_t compare;
     interrupt_register(14, "tick_int", tick_interrupt);
     compare.int_dis = false;
     compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
 ,21 → 56,6
     CPU->arch.next_tick_cmpr = compare.tick_cmpr;
     tick_compare_write(compare.value);
     tick_write(0);
-#if defined (US3)
-    /* disable STICK interrupts and clear any pending ones */
-    tick_compare_reg_t stick_compare;
-    softint_reg_t clear;
-    stick_compare.value = stick_compare_read();
-    stick_compare.int_dis = true;
-    stick_compare.tick_cmpr = 0;
-    stick_compare_write(stick_compare.value);
-    clear.value = 0;
-    clear.stick_int = 1;
-    clear_softint_write(clear.value);
-#endif
 }
 /** Process tick interrupt.
 ,7 → 67,7
 {
     softint_reg_t softint, clear;
     uint64_t drift;
     softint.value = softint_read();
     /*

 /branches/network/kernel/arch/sparc64/src/drivers/fhc.c
 ,7 → 45,6
 #include <mm/slab.h>
 #include <arch/types.h>
 #include <genarch/ofw/ofw_tree.h>
-#include <sysinfo/sysinfo.h>
 fhc_t *central_fhc = NULL;
 ,13 → 86,6
     fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
-    /*
-     * Set sysinfo data needed by the uspace FHC driver.
-     */
-    sysinfo_set_item_val("fhc.uart.size", NULL, reg->size);
-    sysinfo_set_item_val("fhc.uart.physical", NULL, paddr);
-    sysinfo_set_item_val("kbd.cir.fhc", NULL, 1);
     return fhc;
 }
 ,14 → 96,13
         fhc->uart_imap[FHC_UART_IMAP] |= IMAP_V_MASK;
         break;
     default:
-        panic("Unexpected INR (%d).", inr);
+        panic("Unexpected INR (%d)\n", inr);
         break;
     }
 }
-void fhc_clear_interrupt(void *fhcp, int inr)
+void fhc_clear_interrupt(fhc_t *fhc, int inr)
 {
-    fhc_t *fhc = (fhc_t *)fhcp;
     ASSERT(fhc->uart_imap);
     switch (inr) {
 ,7 → 110,7
         fhc->uart_imap[FHC_UART_ICLR] = 0;
         break;
     default:
-        panic("Unexpected INR (%d).", inr);
+        panic("Unexpected INR (%d)\n", inr);
         break;
     }
 }

 /branches/network/kernel/arch/sparc64/src/drivers/kbd.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64
+/** @addtogroup sparc64
  * @{
  */
 /** @file
 ,30 → 34,22
 #include <arch/drivers/kbd.h>
 #include <genarch/ofw/ofw_tree.h>
-#ifdef CONFIG_SUN_KBD
-#include <genarch/kbrd/kbrd.h>
-#endif
 #ifdef CONFIG_Z8530
-#include <genarch/drivers/z8530/z8530.h>
+#include <genarch/kbd/z8530.h>
 #endif
 #ifdef CONFIG_NS16550
-#include <genarch/drivers/ns16550/ns16550.h>
+#include <genarch/kbd/ns16550.h>
 #endif
-#include <console/console.h>
+#include <ddi/device.h>
 #include <ddi/irq.h>
 #include <arch/mm/page.h>
 #include <arch/types.h>
 #include <align.h>
-#include <string.h>
+#include <func.h>
 #include <print.h>
-#include <sysinfo/sysinfo.h>
 kbd_type_t kbd_type = KBD_UNKNOWN;
-#ifdef CONFIG_SUN_KBD
 /** Initialize keyboard.
  *
  * Traverse OpenFirmware device tree in order to find necessary
 ,16 → 63,7
     uintptr_t aligned_addr;
     ofw_tree_property_t *prop;
     const char *name;
-    cir_t cir;
-    void *cir_arg;
-#ifdef CONFIG_NS16550
-    ns16550_t *ns16550;
-#endif
-#ifdef CONFIG_Z8530
-    z8530_t *z8530;
-#endif
     name = ofw_tree_node_name(node);
     /*
 ,32 → 84,30
      */
     uint32_t interrupts;
     prop = ofw_tree_getprop(node, "interrupts");
-    if ((!prop) || (!prop->value))
-        panic("Cannot find 'interrupt' property.");
+    if (!prop || !prop->value)
+        panic("Can't find \"interrupts\" property.\n");
     interrupts = *((uint32_t *) prop->value);
     /*
      * Read 'reg' property.
      */
     prop = ofw_tree_getprop(node, "reg");
-    if ((!prop) || (!prop->value))
-        panic("Cannot find 'reg' property.");
+    if (!prop || !prop->value)
+        panic("Can't find \"reg\" property.\n");
     uintptr_t pa;
     size_t size;
     inr_t inr;
+    devno_t devno = device_assign_devno();
     switch (kbd_type) {
     case KBD_Z8530:
         size = ((ofw_fhc_reg_t *) prop->value)->size;
-        if (!ofw_fhc_apply_ranges(node->parent,
-            ((ofw_fhc_reg_t *) prop->value), &pa)) {
+        if (!ofw_fhc_apply_ranges(node->parent, ((ofw_fhc_reg_t *) prop->value) , &pa)) {
             printf("Failed to determine keyboard address.\n");
             return;
         }
-        if (!ofw_fhc_map_interrupt(node->parent,
-            ((ofw_fhc_reg_t *) prop->value), interrupts, &inr, &cir,
-            &cir_arg)) {
+        if (!ofw_fhc_map_interrupt(node->parent, ((ofw_fhc_reg_t *) prop->value), interrupts, &inr)) {
             printf("Failed to determine keyboard interrupt.\n");
             return;
         }
 ,20 → 115,18
     case KBD_NS16550:
         size = ((ofw_ebus_reg_t *) prop->value)->size;
-        if (!ofw_ebus_apply_ranges(node->parent,
-            ((ofw_ebus_reg_t *) prop->value), &pa)) {
+        if (!ofw_ebus_apply_ranges(node->parent, ((ofw_ebus_reg_t *) prop->value) , &pa)) {
             printf("Failed to determine keyboard address.\n");
             return;
         }
-        if (!ofw_ebus_map_interrupt(node->parent,
-            ((ofw_ebus_reg_t *) prop->value), interrupts, &inr, &cir,
-            &cir_arg)) {
+        if (!ofw_ebus_map_interrupt(node->parent, ((ofw_ebus_reg_t *) prop->value), interrupts, &inr)) {
             printf("Failed to determine keyboard interrupt.\n");
             return;
         };
         break;
     default:
-        panic("Unexpected keyboard type.");
+        panic("Unexpected type.\n");
     }
     /*
 ,57 → 137,23
      */
     aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
     offset = pa - aligned_addr;
+    uintptr_t vaddr = hw_map(aligned_addr, offset + size) + offset;
     switch (kbd_type) {
 #ifdef CONFIG_Z8530
     case KBD_Z8530:
-        z8530 = (z8530_t *) hw_map(aligned_addr, offset + size) +
-            offset;
-        indev_t *kbrdin_z8530 = z8530_init(z8530, inr, cir, cir_arg);
-        if (kbrdin_z8530)
-            kbrd_init(kbrdin_z8530);
-        /*
-         * This is the necessary evil until the userspace drivers are
-         * entirely self-sufficient.
-         */
-        sysinfo_set_item_val("kbd", NULL, true);
-        sysinfo_set_item_val("kbd.type", NULL, KBD_Z8530);
-        sysinfo_set_item_val("kbd.inr", NULL, inr);
-        sysinfo_set_item_val("kbd.address.kernel", NULL,
-            (uintptr_t) z8530);
-        sysinfo_set_item_val("kbd.address.physical", NULL, pa);
+        z8530_init(devno, inr, vaddr);
         break;
 #endif
 #ifdef CONFIG_NS16550
     case KBD_NS16550:
-        ns16550 = (ns16550_t *) hw_map(aligned_addr, offset + size) +
-            offset;
-        indev_t *kbrdin_ns16550 = ns16550_init(ns16550, inr, cir, cir_arg);
-        if (kbrdin_ns16550)
-            kbrd_init(kbrdin_ns16550);
-        /*
-         * This is the necessary evil until the userspace driver is
-         * entirely self-sufficient.
-         */
-        sysinfo_set_item_val("kbd", NULL, true);
-        sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
-        sysinfo_set_item_val("kbd.inr", NULL, inr);
-        sysinfo_set_item_val("kbd.address.kernel", NULL,
-            (uintptr_t) ns16550);
-        sysinfo_set_item_val("kbd.address.physical", NULL, pa);
+        ns16550_init(devno, inr, vaddr);
         break;
 #endif
     default:
-        printf("Kernel is not compiled with the necessary keyboard "
-            "driver this machine requires.\n");
+        printf("Kernel is not compiled with the necessary keyboard driver this machine requires.\n");
     }
 }
-#endif
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/drivers/pci.c
 ,41 → 42,43
 #include <arch/types.h>
 #include <debug.h>
 #include <print.h>
-#include <string.h>
+#include <func.h>
 #include <arch/asm.h>
-#include <sysinfo/sysinfo.h>
-#define SABRE_INTERNAL_REG  0
-#define PSYCHO_INTERNAL_REG 2
+#define PCI_SABRE_REGS_REG  0
-#define OBIO_IMR_BASE   0x200
-#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
+#define PCI_SABRE_IMAP_BASE 0x200
+#define PCI_SABRE_ICLR_BASE 0x300
-#define OBIO_CIR_BASE   0x300
-#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
+#define PCI_PSYCHO_REGS_REG 2
-static void obio_enable_interrupt(pci_t *, int);
-static void obio_clear_interrupt(pci_t *, int);
+#define PCI_PSYCHO_IMAP_BASE    0x200
+#define PCI_PSYCHO_ICLR_BASE    0x300
-static pci_t *pci_sabre_init(ofw_tree_node_t *);
-static pci_t *pci_psycho_init(ofw_tree_node_t *);
+static pci_t *pci_sabre_init(ofw_tree_node_t *node);
+static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
+static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
+static pci_t *pci_psycho_init(ofw_tree_node_t *node);
+static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
+static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
 /** PCI operations for Sabre model. */
 static pci_operations_t pci_sabre_ops = {
-    .enable_interrupt = obio_enable_interrupt,
-    .clear_interrupt = obio_clear_interrupt
+    .enable_interrupt = pci_sabre_enable_interrupt,
+    .clear_interrupt = pci_sabre_clear_interrupt
 };
 /** PCI operations for Psycho model. */
 static pci_operations_t pci_psycho_ops = {
-    .enable_interrupt = obio_enable_interrupt,
-    .clear_interrupt = obio_clear_interrupt
+    .enable_interrupt = pci_psycho_enable_interrupt,
+    .clear_interrupt = pci_psycho_clear_interrupt
 };
 /** Initialize PCI controller (model Sabre).
  *
- * @param node      OpenFirmware device tree node of the Sabre.
+ * @param node OpenFirmware device tree node of the Sabre.
  *
- * @return      Address of the initialized PCI structure.
+ * @return Address of the initialized PCI structure.
  */
 pci_t *pci_sabre_init(ofw_tree_node_t *node)
 {
 ,12 → 95,11
     ofw_upa_reg_t *reg = prop->value;
     count_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < SABRE_INTERNAL_REG + 1)
+    if (regs < PCI_SABRE_REGS_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
-        &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,14 → 108,8
     pci->model = PCI_SABRE;
     pci->op = &pci_sabre_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
-    /*
-     * Set sysinfo data needed by the uspace OBIO driver.
-     */
-    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
-    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
 ,9 → 116,9
 /** Initialize the Psycho PCI controller.
  *
- * @param node      OpenFirmware device tree node of the Psycho.
+ * @param node OpenFirmware device tree node of the Psycho.
  *
- * @return      Address of the initialized PCI structure.
+ * @return Address of the initialized PCI structure.
  */
 pci_t *pci_psycho_init(ofw_tree_node_t *node)
 {
 ,12 → 135,11
     ofw_upa_reg_t *reg = prop->value;
     count_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < PSYCHO_INTERNAL_REG + 1)
+    if (regs < PCI_PSYCHO_REGS_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
-        &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,27 → 148,31
     pci->model = PCI_PSYCHO;
     pci->op = &pci_psycho_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
-    /*
-     * Set sysinfo data needed by the uspace OBIO driver.
-     */
-    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
-    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
-void obio_enable_interrupt(pci_t *pci, int inr)
+void pci_sabre_enable_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
+    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
 }
-void obio_clear_interrupt(pci_t *pci, int inr)
+void pci_sabre_clear_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
+    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
 }
+void pci_psycho_enable_interrupt(pci_t *pci, int inr)
+{
+    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
+}
+void pci_psycho_clear_interrupt(pci_t *pci, int inr)
+{
+    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
+}
 /** Initialize PCI controller. */
 pci_t *pci_init(ofw_tree_node_t *node)
 {
 ,14 → 215,14
 void pci_enable_interrupt(pci_t *pci, int inr)
 {
+    ASSERT(pci->model);
     ASSERT(pci->op && pci->op->enable_interrupt);
     pci->op->enable_interrupt(pci, inr);
 }
-void pci_clear_interrupt(void *pcip, int inr)
+void pci_clear_interrupt(pci_t *pci, int inr)
 {
-    pci_t *pci = (pci_t *)pcip;
+    ASSERT(pci->model);
     ASSERT(pci->op && pci->op->clear_interrupt);
     pci->op->clear_interrupt(pci, inr);
 }

 /branches/network/kernel/arch/sparc64/src/proc/thread.c
 ,8 → 34,9
 #include <proc/thread.h>
 #include <arch/proc/thread.h>
-#include <mm/slab.h>
-#include <arch/trap/regwin.h>
+#include <mm/frame.h>
+#include <mm/page.h>
+#include <arch/mm/page.h>
 #include <align.h>
 void thr_constructor_arch(thread_t *t)
 ,12 → 50,12
 void thr_destructor_arch(thread_t *t)
 {
     if (t->arch.uspace_window_buffer) {
-        uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
         /*
          * Mind the possible alignment of the userspace window buffer
          * belonging to a killed thread.
          */
-        free((uint8_t *) ALIGN_DOWN(uw_buf, UWB_ALIGNMENT));
+        frame_free(KA2PA(ALIGN_DOWN((uintptr_t)
+            t->arch.uspace_window_buffer, PAGE_SIZE)));
     }
 }
 ,7 → 67,7
          * The thread needs userspace window buffer and the object
          * returned from the slab allocator doesn't have any.
          */
-        t->arch.uspace_window_buffer = malloc(UWB_ASIZE, 0);
+        t->arch.uspace_window_buffer = frame_alloc(ONE_FRAME, FRAME_KA);
     } else {
         uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
 ,7 → 76,7
          * belonging to a killed thread.
          */
         t->arch.uspace_window_buffer = (uint8_t *) ALIGN_DOWN(uw_buf,
-            UWB_ASIZE);
+            PAGE_SIZE);
     }
 }

 /branches/network/kernel/arch/sparc64/src/sparc64.c
 ,6 → 37,7
 #include <config.h>
 #include <arch/trap/trap.h>
 #include <arch/console.h>
+#include <proc/thread.h>
 #include <console/console.h>
 #include <arch/boot/boot.h>
 #include <arch/arch.h>
 ,11 → 47,10
 #include <genarch/ofw/ofw_tree.h>
 #include <userspace.h>
 #include <ddi/irq.h>
-#include <string.h>
 bootinfo_t bootinfo;
-/** Perform sparc64-specific initialization before main_bsp() is called. */
+/** Perform sparc64 specific initialization before main_bsp() is called. */
 void arch_pre_main(void)
 {
     /* Copy init task info. */
 ,8 → 61,6
     for (i = 0; i < bootinfo.taskmap.count; i++) {
         init.tasks[i].addr = (uintptr_t) bootinfo.taskmap.tasks[i].addr;
         init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
-        strncpy(init.tasks[i].name, bootinfo.taskmap.tasks[i].name,
-            CONFIG_TASK_NAME_BUFLEN);
     }
     /* Copy boot allocations info. */
 ,6 → 86,8
          * But we only create 128 buckets.
          */
         irq_init(1 << 11, 128);
+        standalone_sparc64_console_init();
     }
 }
 ,7 → 101,18
 void arch_post_smp_init(void)
 {
-    standalone_sparc64_console_init();
+    static thread_t *t = NULL;
+    if (!t) {
+        /*
+             * Create thread that polls keyboard.
+             */
+        t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
+        if (!t)
+            panic("cannot create kkbdpoll\n");
+        thread_ready(t);
+    }
 }
 /** Calibrate delay loop.
 ,19 → 161,5
     while (1);
 }
-/** Construct function pointer
- *
- * @param fptr   function pointer structure
- * @param addr   function address
- * @param caller calling function address
- *
- * @return address of the function pointer
- *
- */
-void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
-{
-    return addr;
-}
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/ddi/ddi.c
 ,7 → 41,7
  * Interrupts are disabled and task is locked.
  *
  * @param task Task.
- * @param ioaddr Starting I/O space address.
+ * @param ioaddr Startign I/O space address.
  * @param size Size of the enabled I/O range.
  *
  * @return 0 on success or an error code from errno.h.

 /branches/network/kernel/arch/sparc64/src/console.c
 ,8 → 37,14
 #include <arch/drivers/scr.h>
 #include <arch/drivers/kbd.h>
-#include <arch/drivers/sgcn.h>
-#include <genarch/srln/srln.h>
+#ifdef CONFIG_Z8530
+#include <genarch/kbd/z8530.h>
+#endif
+#ifdef CONFIG_NS16550
+#include <genarch/kbd/ns16550.h>
+#endif
 #include <console/chardev.h>
 #include <console/console.h>
 #include <arch/asm.h>
 ,98 → 54,89
 #include <genarch/ofw/ofw_tree.h>
 #include <arch.h>
 #include <panic.h>
-#include <string.h>
 #include <print.h>
 #define KEYBOARD_POLL_PAUSE 50000   /* 50ms */
-/**
- * Initialize kernel console to use framebuffer and keyboard directly.
- * Called on UltraSPARC machines with standard keyboard and framebuffer.
- *
- * @param aliases   the "/aliases" OBP node
- */
-static void standard_console_init(ofw_tree_node_t *aliases)
+/** Initialize kernel console to use framebuffer and keyboard directly. */
+void standalone_sparc64_console_init(void)
 {
-#ifdef CONFIG_FB
-    ofw_tree_property_t *prop_scr = ofw_tree_getprop(aliases, "screen");
-    if (!prop_scr)
-        panic("Cannot find property 'screen'.");
-    if (!prop_scr->value)
-        panic("Cannot find screen alias.");
-    ofw_tree_node_t *screen = ofw_tree_lookup(prop_scr->value);
+    stdin = NULL;
+    ofw_tree_node_t *aliases;
+    ofw_tree_property_t *prop;
+    ofw_tree_node_t *screen;
+    ofw_tree_node_t *keyboard;
+    aliases = ofw_tree_lookup("/aliases");
+    if (!aliases)
+        panic("Can't find /aliases.\n");
+    prop = ofw_tree_getprop(aliases, "screen");
+    if (!prop)
+        panic("Can't find property \"screen\".\n");
+    if (!prop->value)
+        panic("Can't find screen alias.\n");
+    screen = ofw_tree_lookup(prop->value);
     if (!screen)
-        panic("Cannot find %s.", prop_scr->value);
+        panic("Can't find %s\n", prop->value);
     scr_init(screen);
-#endif
-#ifdef CONFIG_SUN_KBD
-    ofw_tree_property_t *prop_kbd = ofw_tree_getprop(aliases, "keyboard");
-    if (!prop_kbd)
-        panic("Cannot find property 'keyboard'.");
-    if (!prop_kbd->value)
-        panic("Cannot find keyboard alias.");
-    ofw_tree_node_t *keyboard = ofw_tree_lookup(prop_kbd->value);
+    prop = ofw_tree_getprop(aliases, "keyboard");
+    if (!prop)
+        panic("Can't find property \"keyboard\".\n");
+    if (!prop->value)
+        panic("Can't find keyboard alias.\n");
+    keyboard = ofw_tree_lookup(prop->value);
     if (!keyboard)
-        panic("Cannot find %s.", prop_kbd->value);
+        panic("Can't find %s\n", prop->value);
     kbd_init(keyboard);
-#endif
 }
-/** Initilize I/O on the Serengeti machine. */
-static void serengeti_init(void)
+/** Kernel thread for polling keyboard.
+ *
+ * @param arg Ignored.
+ */
+void kkbdpoll(void *arg)
 {
-#ifdef CONFIG_SGCN_KBD
-    indev_t *kbrdin;
-    kbrdin = sgcnin_init();
-    if (kbrdin)
-        srlnin_init(kbrdin);
+    thread_detach(THREAD);
+#ifdef CONFIG_Z8530
+    if (kbd_type == KBD_Z8530) {
+        /*
+         * The z8530 driver is interrupt-driven.
+         */
+        return;
+    }
 #endif
-#ifdef CONFIG_SGCN_PRN
-    sgcnout_init();
+    while (1) {
+#ifdef CONFIG_NS16550
+        if (kbd_type == KBD_NS16550)
+            ns16550_poll();
 #endif
-}
-/**
- * Initialize input/output. Auto-detects the type of machine
- * and calls the appropriate I/O init routine.
- */
-void standalone_sparc64_console_init(void)
-{
-    ofw_tree_node_t *aliases;
-    ofw_tree_property_t *prop;
-    aliases = ofw_tree_lookup("/aliases");
-    if (!aliases)
-        panic("Cannot find '/aliases'.");
-    /* "def-cn" = "default console" */
-    prop = ofw_tree_getprop(aliases, "def-cn");
-    if ((!prop) || (!prop->value) || (strcmp(prop->value, "/sgcn") != 0)) {
-        standard_console_init(aliases);
-    } else {
-        serengeti_init();
+        thread_usleep(KEYBOARD_POLL_PAUSE);
     }
 }
 /** Acquire console back for kernel
  *
  */
 void arch_grab_console(void)
 {
-#ifdef CONFIG_FB
-    scr_redraw();
-#endif
     switch (kbd_type) {
-#ifdef CONFIG_SGCN
-    case KBD_SGCN:
-        sgcn_grab();
+#ifdef CONFIG_Z8530
+    case KBD_Z8530:
+        z8530_grab();
         break;
 #endif
+#ifdef CONFIG_NS16550
+    case KBD_NS16550:
+        ns16550_grab();
+        break;
+#endif
     default:
         break;
     }
 ,11 → 148,16
 void arch_release_console(void)
 {
     switch (kbd_type) {
-#ifdef CONFIG_SGCN
-    case KBD_SGCN:
-        sgcn_release();
+#ifdef CONFIG_Z8530
+    case KBD_Z8530:
+        z8530_release();
         break;
 #endif
+#ifdef CONFIG_NS16550
+    case KBD_NS16550:
+        ns16550_release();
+        break;
+#endif
     default:
         break;
     }

 /branches/network/kernel/arch/sparc64/src/start.S
 ,7 → 27,6
 #
 #include <arch/arch.h>
-#include <arch/cpu.h>
 #include <arch/regdef.h>
 #include <arch/boot/boot.h>
 #include <arch/stack.h>
 ,16 → 47,6
 #define BSP_FLAG    1
 /*
- * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
- * a given processor.
- */
-#if defined (US)
-    #define PHYSMEM_ADDR_SIZE   41
-#elif defined (US3)
-    #define PHYSMEM_ADDR_SIZE   43
-#endif
-/*
  * Here is where the kernel is passed control from the boot loader.
  *
  * The registers are expected to be in this state:
 ,13 → 67,11
     and %o0, %l0, %l7           ! l7 <= bootstrap processor?
     andn %o0, %l0, %l6          ! l6 <= start of physical memory
-    ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
+    ! Get bits 40:13 of physmem_base.
     srlx %l6, 13, %l5
+    sllx %l5, 13 + (63 - 40), %l5
+    srlx %l5, 63 - 40, %l5          ! l5 <= physmem_base[40:13]
-    ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
-    sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
-    srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
     /*
      * Setup basic runtime environment.
      */
 ,8 → 83,6
                         ! consistent
     wrpr %g0, NWINDOWS - 1, %cleanwin   ! prevent needless clean_window
                         ! traps for kernel
-    wrpr %g0, 0, %wstate            ! use default spill/fill trap
     wrpr %g0, 0, %tl            ! TL = 0, primary context
                         ! register is used
 ,8 → 244,7
     /*
      * Precompute kernel 8K TLB data template.
-     * %l5 contains starting physical address
-     * bits [(PHYSMEM_ADDR_SIZE - 1):13]
+     * %l5 contains starting physical address bits [40:13]
      */
     sethi %hi(kernel_8k_tlb_data_template), %l4
     ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
 ,32 → 282,15
     nop
-:
-#ifdef CONFIG_SMP
     /*
-     * Determine the width of the MID and save its mask to %g3. The width
-     * is
-     *  * 5 for US and US-IIIi,
-     *  * 10 for US3 except US-IIIi.
-     */
-#if defined(US)
-    mov 0x1f, %g3
-#elif defined(US3)
-    mov 0x3ff, %g3
-    rdpr %ver, %g2
-    sllx %g2, 16, %g2
-    srlx %g2, 48, %g2
-    cmp %g2, IMPL_ULTRASPARCIII_I
-    move %xcc, 0x1f, %g3
-#endif
-    /*
      * Read MID from the processor.
      */
-    ldxa [%g0] ASI_ICBUS_CONFIG, %g1
-    srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
-    and %g1, %g3, %g1
+:
+    ldxa [%g0] ASI_UPA_CONFIG, %g1
+    srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
+    and %g1, UPA_CONFIG_MID_MASK, %g1
+#ifdef CONFIG_SMP
     /*
      * Active loop for APs until the BSP picks them up. A processor cannot
      * leave the loop until the global variable 'waking_up_mid' equals its

 /branches/network/kernel/arch/sparc64/_link.ld.in
 ,8 → 1,8
 /** SPARC64 linker script
  *
  *  It is ELF format, but its only section looks like this:
- *   kernel text
- *   kernel data
+ *  kernel text
+ *  kernel data
  *
  */
 ,7 → 11,7
 ENTRY(kernel_image_start)
 SECTIONS {
-    .image VMA: AT (LMA) {
+    .image VMA: AT (LMA) {
         ktext_start = .;
         *(K_TEXT_START)
         *(.text);
 ,23 → 21,23
         *(K_DATA_START)
         *(.rodata);
         *(.rodata.*);
-        *(.data);                   /* initialized data */
+        *(.data);       /* initialized data */
         *(.sdata);
         *(.sdata2);
         *(.sbss);
         . = ALIGN(8);
         hardcoded_ktext_size = .;
-        QUAD(ktext_end - ktext_start);
+        QUAD(ktext_end - ktext_start);
         hardcoded_kdata_size = .;
         QUAD(kdata_end - kdata_start);
         hardcoded_load_address = .;
         QUAD(VMA);
-        *(.bss);                    /* uninitialized static variables */
-        *(COMMON);                  /* global variables */
+        *(.bss);        /* uninitialized static variables */
+        *(COMMON);      /* global variables */
         symbol_table = .;
-        *(symtab.*);                /* Symbol table, must be LAST symbol!*/
+                *(symtab.*);            /* Symbol table, must be LAST symbol!*/
         kdata_end = .;
     }
 ,5 → 44,5
     /DISCARD/ : {
         *(*);
     }
 }

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Ignore whitespace Rev 4252 → Rev 3386