| /branches/network/kernel/arch/mips32/Makefile.inc |
|---|
| 29,9 → 29,13 |
| ## Toolchain configuration |
| # |
| ifndef CROSS_PREFIX |
| CROSS_PREFIX = /usr/local |
| endif |
| BFD_ARCH = mips |
| TARGET = mipsel-linux-gnu |
| TOOLCHAIN_DIR = /usr/local/mipsel |
| TOOLCHAIN_DIR = $(CROSS_PREFIX)/mipsel |
| KERNEL_LOAD_ADDRESS = 0x80100000 |
| INIT_ADDRESS = 0x81000000 |
| 56,20 → 60,6 |
| ## Accepted MACHINEs |
| # |
| ifeq ($(MACHINE),indy) |
| # GCC 4.0.1 compiled for mipsEL has problems compiling in |
| # BigEndian mode with the swl/swr/lwl/lwr instructions. |
| # We have to compile it with mips-sgi-irix5 to get it right. |
| BFD_NAME = elf32-bigmips |
| BFD = ecoff-bigmips --impure |
| TARGET = mips-sgi-irix5 |
| TOOLCHAIN_DIR = /usr/local/mips/bin |
| KERNEL_LOAD_ADDRESS = 0x88002000 |
| GCC_CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -march=r4600 |
| INIT_ADDRESS = 0 |
| INIT_SIZE = 0 |
| endif |
| ifeq ($(MACHINE),lgxemul) |
| BFD_NAME = elf32-tradlittlemips |
| BFD = binary |
| 79,7 → 69,7 |
| BFD_NAME = elf32-bigmips |
| BFD = ecoff-bigmips |
| TARGET = mips-sgi-irix5 |
| TOOLCHAIN_DIR = /usr/local/mips/bin |
| TOOLCHAIN_DIR = $(CROSS_PREFIX)/mips/bin |
| GCC_CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -mips3 |
| INIT_ADDRESS = 0x81800000 |
| endif |
| 123,7 → 113,6 |
| arch/$(ARCH)/src/mm/as.c \ |
| arch/$(ARCH)/src/fpu_context.c \ |
| arch/$(ARCH)/src/ddi/ddi.c \ |
| arch/$(ARCH)/src/drivers/arc.c \ |
| arch/$(ARCH)/src/drivers/msim.c \ |
| arch/$(ARCH)/src/drivers/serial.c \ |
| arch/$(ARCH)/src/smp/order.c |
| /branches/network/kernel/arch/mips32/src/asm.S |
|---|
| 71,6 → 71,7 |
| and $v0,$v0,$v1 |
| beq $a1,$v0,3f |
| move $t0,$a0 |
| move $t2,$a0 # save dst |
| 0: |
| beq $a2,$zero,2f |
| 86,7 → 87,7 |
| 2: |
| jr $ra |
| move $v0,$a1 |
| move $v0,$t2 |
| 3: |
| addiu $v0,$a0,3 |
| 126,7 → 127,7 |
| sb $a0,0($v1) |
| jr $ra |
| move $v0,$a1 |
| move $v0,$t2 |
| memcpy_from_uspace_failover_address: |
| memcpy_to_uspace_failover_address: |
| /branches/network/kernel/arch/mips32/src/mm/frame.c |
|---|
| 32,27 → 32,238 |
| /** @file |
| */ |
| #include <macros.h> |
| #include <arch/mm/frame.h> |
| #include <arch/mm/tlb.h> |
| #include <interrupt.h> |
| #include <mm/frame.h> |
| #include <mm/asid.h> |
| #include <config.h> |
| #include <arch/drivers/arc.h> |
| #include <arch/drivers/msim.h> |
| #include <arch/drivers/serial.h> |
| #include <print.h> |
| #define ZERO_PAGE_MASK TLB_PAGE_MASK_256K |
| #define ZERO_FRAMES 2048 |
| #define ZERO_PAGE_WIDTH 18 /* 256K */ |
| #define ZERO_PAGE_SIZE (1 << ZERO_PAGE_WIDTH) |
| #define ZERO_PAGE_ASID ASID_INVALID |
| #define ZERO_PAGE_TLBI 0 |
| #define ZERO_PAGE_ADDR 0 |
| #define ZERO_PAGE_OFFSET (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1) |
| #define ZERO_PAGE_VALUE (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET]) |
| #define ZERO_PAGE_VALUE_KSEG1(frame) (((volatile uint32_t *) (0xa0000000 + (frame << ZERO_PAGE_WIDTH)))[ZERO_PAGE_OFFSET]) |
| #define MAX_REGIONS 32 |
| typedef struct { |
| pfn_t start; |
| pfn_t count; |
| } phys_region_t; |
| static count_t phys_regions_count = 0; |
| static phys_region_t phys_regions[MAX_REGIONS]; |
| /** Check whether frame is available |
| * |
| * Returns true if given frame is generally available for use. |
| * Returns false if given frame is used for physical memory |
| * mapped devices and cannot be used. |
| * |
| */ |
| static bool frame_available(pfn_t frame) |
| { |
| #if MACHINE == msim |
| /* MSIM device (dprinter) */ |
| if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) |
| return false; |
| /* MSIM device (dkeyboard) */ |
| if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) |
| return false; |
| #endif |
| #if MACHINE == simics |
| /* Simics device (serial line) */ |
| if (frame == (KA2PA(SERIAL_ADDRESS) >> ZERO_PAGE_WIDTH)) |
| return false; |
| #endif |
| #if (MACHINE == lgxemul) || (MACHINE == bgxemul) |
| /* gxemul devices */ |
| if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
| 0x10000000, MB2SIZE(256))) |
| return false; |
| #endif |
| return true; |
| } |
| /** Check whether frame is safe to write |
| * |
| * Returns true if given frame is safe for read/write test. |
| * Returns false if given frame should not be touched. |
| * |
| */ |
| static bool frame_safe(pfn_t frame) |
| { |
| /* Kernel structures */ |
| if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base)) |
| return false; |
| /* Kernel */ |
| if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
| KA2PA(config.base), config.kernel_size)) |
| return false; |
| /* Kernel stack */ |
| if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
| KA2PA(config.stack_base), config.stack_size)) |
| return false; |
| /* Init tasks */ |
| bool safe = true; |
| count_t i; |
| for (i = 0; i < init.cnt; i++) |
| if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, |
| KA2PA(init.tasks[i].addr), init.tasks[i].size)) { |
| safe = false; |
| break; |
| } |
| return safe; |
| } |
| static void frame_add_region(pfn_t start_frame, pfn_t end_frame) |
| { |
| if (end_frame > start_frame) { |
| /* Convert 1M frames to 16K frames */ |
| pfn_t first = ADDR2PFN(start_frame << ZERO_PAGE_WIDTH); |
| pfn_t count = ADDR2PFN((end_frame - start_frame) << ZERO_PAGE_WIDTH); |
| /* Interrupt vector frame is blacklisted */ |
| pfn_t conf_frame; |
| if (first == 0) |
| conf_frame = 1; |
| else |
| conf_frame = first; |
| zone_create(first, count, conf_frame, 0); |
| if (phys_regions_count < MAX_REGIONS) { |
| phys_regions[phys_regions_count].start = first; |
| phys_regions[phys_regions_count].count = count; |
| phys_regions_count++; |
| } |
| } |
| } |
| /** Create memory zones |
| * |
| * If ARC is known, read information from ARC, otherwise |
| * assume some defaults. |
| * - blacklist first FRAME because there is an exception vector |
| * Walk through available 256 KB chunks of physical |
| * memory and create zones. |
| * |
| * Note: It is assumed that the TLB is not yet being |
| * used in any way, thus there is no interference. |
| * |
| */ |
| void frame_arch_init(void) |
| { |
| if (!arc_frame_init()) { |
| zone_create(0, ADDR2PFN(CONFIG_MEMORY_SIZE), 1, 0); |
| /* |
| * Blacklist interrupt vector |
| */ |
| frame_mark_unavailable(0, 1); |
| ipl_t ipl = interrupts_disable(); |
| /* Clear and initialize TLB */ |
| cp0_pagemask_write(ZERO_PAGE_MASK); |
| cp0_entry_lo0_write(0); |
| cp0_entry_lo1_write(0); |
| cp0_entry_hi_write(0); |
| count_t i; |
| for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
| cp0_index_write(i); |
| tlbwi(); |
| } |
| pfn_t start_frame = 0; |
| pfn_t frame; |
| bool avail = true; |
| /* Walk through all 1 MB frames */ |
| for (frame = 0; frame < ZERO_FRAMES; frame++) { |
| if (!frame_available(frame)) |
| avail = false; |
| else { |
| if (frame_safe(frame)) { |
| entry_lo_t lo0; |
| entry_lo_t lo1; |
| entry_hi_t hi; |
| tlb_prepare_entry_lo(&lo0, false, true, true, false, frame << (ZERO_PAGE_WIDTH - 12)); |
| tlb_prepare_entry_lo(&lo1, false, false, false, false, 0); |
| tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR); |
| cp0_pagemask_write(ZERO_PAGE_MASK); |
| cp0_entry_lo0_write(lo0.value); |
| cp0_entry_lo1_write(lo1.value); |
| cp0_entry_hi_write(hi.value); |
| cp0_index_write(ZERO_PAGE_TLBI); |
| tlbwi(); |
| ZERO_PAGE_VALUE = 0; |
| if (ZERO_PAGE_VALUE != 0) |
| avail = false; |
| else { |
| ZERO_PAGE_VALUE = 0xdeadbeef; |
| if (ZERO_PAGE_VALUE != 0xdeadbeef) |
| avail = false; |
| #if (MACHINE == lgxemul) || (MACHINE == bgxemul) |
| else { |
| ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd; |
| if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd) |
| avail = false; |
| } |
| #endif |
| } |
| } |
| } |
| if (!avail) { |
| frame_add_region(start_frame, frame); |
| start_frame = frame + 1; |
| avail = true; |
| } |
| } |
| frame_add_region(start_frame, frame); |
| /* Blacklist interrupt vector frame */ |
| frame_mark_unavailable(0, 1); |
| /* Cleanup */ |
| cp0_pagemask_write(ZERO_PAGE_MASK); |
| cp0_entry_lo0_write(0); |
| cp0_entry_lo1_write(0); |
| cp0_entry_hi_write(0); |
| cp0_index_write(ZERO_PAGE_TLBI); |
| tlbwi(); |
| interrupts_restore(ipl); |
| } |
| void physmem_print(void) |
| { |
| printf("Base Size\n"); |
| printf("---------- ----------\n"); |
| count_t i; |
| for (i = 0; i < phys_regions_count; i++) { |
| printf("%#010x %10u\n", |
| PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count)); |
| } |
| } |
| /** @} |
| */ |
| /branches/network/kernel/arch/mips32/src/mm/tlb.c |
|---|
| 53,9 → 53,6 |
| static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc); |
| static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn); |
| static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr); |
| /** Initialize TLB |
| * |
| * Initialize TLB. |
| 76,7 → 73,6 |
| cp0_index_write(i); |
| tlbwi(); |
| } |
| /* |
| * The kernel is going to make use of some wired |
| 131,8 → 127,8 |
| */ |
| pte->a = 1; |
| prepare_entry_hi(&hi, asid, badvaddr); |
| prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
| tlb_prepare_entry_hi(&hi, asid, badvaddr); |
| tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
| /* |
| * New entry is to be inserted into TLB |
| 178,7 → 174,7 |
| * Locate the faulting entry in TLB. |
| */ |
| hi.value = cp0_entry_hi_read(); |
| prepare_entry_hi(&hi, hi.asid, badvaddr); |
| tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
| cp0_entry_hi_write(hi.value); |
| tlbp(); |
| index.value = cp0_index_read(); |
| 221,7 → 217,7 |
| */ |
| pte->a = 1; |
| prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
| tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
| /* |
| * The entry is to be updated in TLB. |
| 262,7 → 258,7 |
| * Locate the faulting entry in TLB. |
| */ |
| hi.value = cp0_entry_hi_read(); |
| prepare_entry_hi(&hi, hi.asid, badvaddr); |
| tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
| cp0_entry_hi_write(hi.value); |
| tlbp(); |
| index.value = cp0_index_read(); |
| 312,7 → 308,7 |
| pte->a = 1; |
| pte->d = 1; |
| prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
| tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
| /* |
| * The entry is to be updated in TLB. |
| 445,7 → 441,7 |
| } |
| } |
| void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn) |
| void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn) |
| { |
| lo->value = 0; |
| lo->g = g; |
| 455,7 → 451,7 |
| lo->pfn = pfn; |
| } |
| void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
| void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
| { |
| hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
| hi->asid = asid; |
| 572,7 → 568,7 |
| */ |
| void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
| { |
| int i; |
| unsigned int i; |
| ipl_t ipl; |
| entry_lo_t lo0, lo1; |
| entry_hi_t hi, hi_save; |
| 583,9 → 579,9 |
| hi_save.value = cp0_entry_hi_read(); |
| ipl = interrupts_disable(); |
| for (i = 0; i < cnt+1; i+=2) { |
| for (i = 0; i < cnt + 1; i += 2) { |
| hi.value = 0; |
| prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
| tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
| cp0_entry_hi_write(hi.value); |
| tlbp(); |
| /branches/network/kernel/arch/mips32/src/mm/as.c |
|---|
| 44,7 → 44,7 |
| /** Architecture dependent address space init. */ |
| void as_arch_init(void) |
| { |
| as_operations = &as_pt_operations; |
| as_operations = &as_pt_operations; |
| asid_fifo_init(); |
| } |
| /branches/network/kernel/arch/mips32/src/drivers/arc.c |
|---|
| File deleted |
| /branches/network/kernel/arch/mips32/src/drivers/msim.c |
|---|
| 39,12 → 39,9 |
| #include <arch/cp0.h> |
| #include <console/console.h> |
| #include <sysinfo/sysinfo.h> |
| #include <ddi/ddi.h> |
| /** Address of devices. */ |
| #define MSIM_VIDEORAM 0xB0000000 |
| #define MSIM_KBD_ADDRESS 0xB0000000 |
| #define MSIM_KBD_IRQ 2 |
| static parea_t msim_parea; |
| static chardev_t console; |
| static irq_t msim_irq; |
| 158,6 → 155,16 |
| sysinfo_set_item_val("kbd.devno", NULL, devno); |
| sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ); |
| sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS); |
| msim_parea.pbase = KA2PA(MSIM_VIDEORAM); |
| msim_parea.vbase = MSIM_VIDEORAM; |
| msim_parea.frames = 1; |
| msim_parea.cacheable = false; |
| ddi_parea_register(&msim_parea); |
| sysinfo_set_item_val("fb", NULL, true); |
| sysinfo_set_item_val("fb.kind", NULL, 3); |
| sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(MSIM_VIDEORAM)); |
| } |
| /** @} |
| /branches/network/kernel/arch/mips32/src/console.c |
|---|
| 34,18 → 34,15 |
| #include <console/console.h> |
| #include <arch/console.h> |
| #include <arch/drivers/arc.h> |
| #include <arch/drivers/serial.h> |
| #include <arch/drivers/msim.h> |
| void console_init(devno_t devno) |
| { |
| if (!arc_console()) { |
| if (serial_init()) |
| serial_console(devno); |
| else |
| msim_console(devno); |
| } |
| if (serial_init()) |
| serial_console(devno); |
| else |
| msim_console(devno); |
| } |
| /** Acquire console back for kernel |
| /branches/network/kernel/arch/mips32/src/mips32.c |
|---|
| 48,8 → 48,8 |
| #include <sysinfo/sysinfo.h> |
| #include <arch/interrupt.h> |
| #include <arch/drivers/arc.h> |
| #include <console/chardev.h> |
| #include <arch/barrier.h> |
| #include <arch/debugger.h> |
| #include <genarch/fb/fb.h> |
| #include <genarch/fb/visuals.h> |
| 96,18 → 96,21 |
| /* Initialize dispatch table */ |
| exception_init(); |
| arc_init(); |
| /* Copy the exception vectors to the right places */ |
| memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE); |
| smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE); |
| memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE); |
| smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE); |
| memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE); |
| smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE); |
| /* |
| * Switch to BEV normal level so that exception vectors point to the kernel. |
| * Clear the error level. |
| * Switch to BEV normal level so that exception vectors point to the |
| * kernel. Clear the error level. |
| */ |
| cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
| cp0_status_write(cp0_status_read() & |
| ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit)); |
| /* |
| * Mask all interrupts |
| 122,7 → 125,8 |
| interrupt_init(); |
| console_init(device_assign_devno()); |
| #ifdef CONFIG_FB |
| fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8); // gxemul framebuffer |
| /* GXemul framebuffer */ |
| fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8); |
| #endif |
| sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1); |
| } |
| 143,13 → 147,14 |
| { |
| /* EXL = 1, UM = 1, IE = 1 */ |
| cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | |
| cp0_status_um_bit | cp0_status_ie_enabled_bit)); |
| cp0_status_um_bit | cp0_status_ie_enabled_bit)); |
| cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry); |
| userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE), |
| (uintptr_t) kernel_uarg->uspace_uarg, |
| (uintptr_t) kernel_uarg->uspace_entry); |
| (uintptr_t) kernel_uarg->uspace_uarg, |
| (uintptr_t) kernel_uarg->uspace_entry); |
| while (1); |
| while (1) |
| ; |
| } |
| /** Perform mips32 specific tasks needed before the new task is run. */ |
| 160,7 → 165,8 |
| /** Perform mips32 specific tasks needed before the new thread is scheduled. */ |
| void before_thread_runs_arch(void) |
| { |
| supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
| supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE - |
| SP_DELTA]; |
| } |
| void after_thread_ran_arch(void) |
| 179,10 → 185,10 |
| void arch_reboot(void) |
| { |
| if (!arc_reboot()) |
| ___halt(); |
| ___halt(); |
| while (1); |
| while (1) |
| ; |
| } |
| /** @} |
| /branches/network/kernel/arch/mips32/src/interrupt.c |
|---|
| 38,7 → 38,6 |
| #include <arch.h> |
| #include <arch/cp0.h> |
| #include <time/clock.h> |
| #include <arch/drivers/arc.h> |
| #include <ipc/sysipc.h> |
| #include <ddi/device.h> |
| /branches/network/kernel/arch/mips32/src/start.S |
|---|
| 349,5 → 349,7 |
| userspace_asm: |
| add $sp, $a0, 0 |
| add $v0, $a1, 0 |
| add $t9, $a2, 0 # Set up correct entry into PIC code |
| add $t9, $a2, 0 # Set up correct entry into PIC code |
| xor $a0, $a0, $a0 # $a0 is defined to hold pcb_ptr |
| # set it to 0 |
| eret |
| /branches/network/kernel/arch/mips32/src/debugger.c |
|---|
| 33,6 → 33,7 |
| */ |
| #include <arch/debugger.h> |
| #include <arch/barrier.h> |
| #include <memstr.h> |
| #include <console/kconsole.h> |
| #include <console/cmd.h> |
| 72,7 → 73,8 |
| }; |
| static cmd_info_t addbkpt_info = { |
| .name = "addbkpt", |
| .description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch insts unsupported.", |
| .description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch " |
| "insts unsupported.", |
| .func = cmd_add_breakpoint, |
| .argc = 1, |
| .argv = &add_argv |
| 84,7 → 86,8 |
| }; |
| static cmd_info_t addbkpte_info = { |
| .name = "addbkpte", |
| .description = "addebkpte <&symbol> <&func> - new bkpoint. Call func(or Nothing if 0).", |
| .description = "addebkpte <&symbol> <&func> - new bkpoint. Call " |
| "func(or Nothing if 0).", |
| .func = cmd_add_breakpoint, |
| .argc = 2, |
| .argv = adde_argv |
| 93,7 → 96,7 |
| static struct { |
| uint32_t andmask; |
| uint32_t value; |
| }jmpinstr[] = { |
| } jmpinstr[] = { |
| {0xf3ff0000, 0x41000000}, /* BCzF */ |
| {0xf3ff0000, 0x41020000}, /* BCzFL */ |
| {0xf3ff0000, 0x41010000}, /* BCzT */ |
| 117,7 → 120,7 |
| {0xfc000000, 0x08000000}, /* J */ |
| {0xfc000000, 0x0c000000}, /* JAL */ |
| {0xfc1f07ff, 0x00000009}, /* JALR */ |
| {0,0} /* EndOfTable */ |
| {0, 0} /* EndOfTable */ |
| }; |
| /** Test, if the given instruction is a jump or branch instruction |
| 129,7 → 132,7 |
| { |
| int i; |
| for (i=0;jmpinstr[i].andmask;i++) { |
| for (i = 0; jmpinstr[i].andmask; i++) { |
| if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value) |
| return true; |
| } |
| 152,14 → 155,16 |
| spinlock_lock(&bkpoint_lock); |
| /* Check, that the breakpoints do not conflict */ |
| for (i=0; i<BKPOINTS_MAX; i++) { |
| for (i = 0; i < BKPOINTS_MAX; i++) { |
| if (breakpoints[i].address == (uintptr_t)argv->intval) { |
| printf("Duplicate breakpoint %d.\n", i); |
| spinlock_unlock(&bkpoints_lock); |
| return 0; |
| } else if (breakpoints[i].address == (uintptr_t)argv->intval + sizeof(unative_t) || \ |
| breakpoints[i].address == (uintptr_t)argv->intval - sizeof(unative_t)) { |
| printf("Adjacent breakpoints not supported, conflict with %d.\n", i); |
| } else if (breakpoints[i].address == (uintptr_t)argv->intval + |
| sizeof(unative_t) || breakpoints[i].address == |
| (uintptr_t)argv->intval - sizeof(unative_t)) { |
| printf("Adjacent breakpoints not supported, conflict " |
| "with %d.\n", i); |
| spinlock_unlock(&bkpoints_lock); |
| return 0; |
| } |
| 166,7 → 171,7 |
| } |
| for (i=0; i<BKPOINTS_MAX; i++) |
| for (i = 0; i < BKPOINTS_MAX; i++) |
| if (!breakpoints[i].address) { |
| cur = &breakpoints[i]; |
| break; |
| 185,7 → 190,7 |
| cur->flags = 0; |
| } else { /* We are add extended */ |
| cur->flags = BKPOINT_FUNCCALL; |
| cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval; |
| cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval; |
| } |
| if (is_jump(cur->instruction)) |
| cur->flags |= BKPOINT_ONESHOT; |
| 193,6 → 198,7 |
| /* Set breakpoint */ |
| *((unative_t *)cur->address) = 0x0d; |
| smc_coherence(cur->address); |
| spinlock_unlock(&bkpoint_lock); |
| interrupts_restore(ipl); |
| 200,8 → 206,6 |
| return 1; |
| } |
| /** Remove breakpoint from table */ |
| int cmd_del_breakpoint(cmd_arg_t *argv) |
| { |
| 208,7 → 212,7 |
| bpinfo_t *cur; |
| ipl_t ipl; |
| if (argv->intval < 0 || argv->intval > BKPOINTS_MAX) { |
| if (argv->intval > BKPOINTS_MAX) { |
| printf("Invalid breakpoint number.\n"); |
| return 0; |
| } |
| 229,7 → 233,9 |
| return 0; |
| } |
| ((uint32_t *)cur->address)[0] = cur->instruction; |
| smc_coherence(((uint32_t *)cur->address)[0]); |
| ((uint32_t *)cur->address)[1] = cur->nextinstruction; |
| smc_coherence(((uint32_t *)cur->address)[1]); |
| cur->address = NULL; |
| 252,11 → 258,11 |
| symbol = get_symtab_entry(breakpoints[i].address); |
| printf("%-2u %-5d %#10zx %-6s %-7s %-8s %s\n", i, |
| breakpoints[i].counter, breakpoints[i].address, |
| ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" : "false"), |
| ((breakpoints[i].flags & BKPOINT_ONESHOT) ? "true" : "false"), |
| ((breakpoints[i].flags & BKPOINT_FUNCCALL) ? "true" : "false"), |
| symbol); |
| breakpoints[i].counter, breakpoints[i].address, |
| ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" : |
| "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT) |
| ? "true" : "false"), ((breakpoints[i].flags & |
| BKPOINT_FUNCCALL) ? "true" : "false"), symbol); |
| } |
| return 1; |
| } |
| 266,7 → 272,7 |
| { |
| int i; |
| for (i=0; i<BKPOINTS_MAX; i++) |
| for (i = 0; i < BKPOINTS_MAX; i++) |
| breakpoints[i].address = NULL; |
| cmd_initialize(&bkpts_info); |
| 305,16 → 311,16 |
| panic("Breakpoint in branch delay slot not supported.\n"); |
| spinlock_lock(&bkpoint_lock); |
| for (i=0; i<BKPOINTS_MAX; i++) { |
| for (i = 0; i < BKPOINTS_MAX; i++) { |
| /* Normal breakpoint */ |
| if (fireaddr == breakpoints[i].address \ |
| && !(breakpoints[i].flags & BKPOINT_REINST)) { |
| if (fireaddr == breakpoints[i].address && |
| !(breakpoints[i].flags & BKPOINT_REINST)) { |
| cur = &breakpoints[i]; |
| break; |
| } |
| /* Reinst only breakpoint */ |
| if ((breakpoints[i].flags & BKPOINT_REINST) \ |
| && (fireaddr ==breakpoints[i].address+sizeof(unative_t))) { |
| if ((breakpoints[i].flags & BKPOINT_REINST) && |
| (fireaddr == breakpoints[i].address + sizeof(unative_t))) { |
| cur = &breakpoints[i]; |
| break; |
| } |
| 323,8 → 329,10 |
| if (cur->flags & BKPOINT_REINST) { |
| /* Set breakpoint on first instruction */ |
| ((uint32_t *)cur->address)[0] = 0x0d; |
| smc_coherence(((uint32_t *)cur->address)[0]); |
| /* Return back the second */ |
| ((uint32_t *)cur->address)[1] = cur->nextinstruction; |
| smc_coherence(((uint32_t *)cur->address)[1]); |
| cur->flags &= ~BKPOINT_REINST; |
| spinlock_unlock(&bkpoint_lock); |
| return; |
| 333,11 → 341,12 |
| printf("Warning: breakpoint recursion\n"); |
| if (!(cur->flags & BKPOINT_FUNCCALL)) |
| printf("***Breakpoint %d: %p in %s.\n", i, |
| fireaddr, get_symtab_entry(istate->epc)); |
| printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, |
| get_symtab_entry(istate->epc)); |
| /* Return first instruction back */ |
| ((uint32_t *)cur->address)[0] = cur->instruction; |
| smc_coherence(cur->address); |
| if (! (cur->flags & BKPOINT_ONESHOT)) { |
| /* Set Breakpoint on next instruction */ |
| /branches/network/kernel/arch/mips32/src/exception.c |
|---|
| 161,7 → 161,7 |
| * Spurious interrupt. |
| */ |
| #ifdef CONFIG_DEBUG |
| printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
| printf("cpu%u: spurious interrupt (inum=%d)\n", CPU->id, i); |
| #endif |
| } |
| } |
| /branches/network/kernel/arch/mips32/src/context.S |
|---|
| 26,7 → 26,6 |
| # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| #include <arch/asm/regname.h> |
| #include <arch/context_offset.h> |
| .text |
| 38,41 → 37,9 |
| .global context_save_arch |
| .global context_restore_arch |
| .macro CONTEXT_STORE r |
| sw $s0,OFFSET_S0(\r) |
| sw $s1,OFFSET_S1(\r) |
| sw $s2,OFFSET_S2(\r) |
| sw $s3,OFFSET_S3(\r) |
| sw $s4,OFFSET_S4(\r) |
| sw $s5,OFFSET_S5(\r) |
| sw $s6,OFFSET_S6(\r) |
| sw $s7,OFFSET_S7(\r) |
| sw $s8,OFFSET_S8(\r) |
| sw $gp,OFFSET_GP(\r) |
| sw $ra,OFFSET_PC(\r) |
| sw $sp,OFFSET_SP(\r) |
| .endm |
| .macro CONTEXT_LOAD r |
| lw $s0,OFFSET_S0(\r) |
| lw $s1,OFFSET_S1(\r) |
| lw $s2,OFFSET_S2(\r) |
| lw $s3,OFFSET_S3(\r) |
| lw $s4,OFFSET_S4(\r) |
| lw $s5,OFFSET_S5(\r) |
| lw $s6,OFFSET_S6(\r) |
| lw $s7,OFFSET_S7(\r) |
| lw $s8,OFFSET_S8(\r) |
| lw $gp,OFFSET_GP(\r) |
| lw $ra,OFFSET_PC(\r) |
| lw $sp,OFFSET_SP(\r) |
| .endm |
| context_save_arch: |
| CONTEXT_STORE $a0 |
| CONTEXT_SAVE_ARCH_CORE $a0 |
| # context_save returns 1 |
| j $31 |
| 79,7 → 46,7 |
| li $2, 1 |
| context_restore_arch: |
| CONTEXT_LOAD $a0 |
| CONTEXT_RESTORE_ARCH_CORE $a0 |
| # context_restore returns 0 |
| j $31 |
| /branches/network/kernel/arch/mips32/src/cpu/cpu.c |
|---|
| 104,22 → 104,20 |
| void cpu_print_report(cpu_t *m) |
| { |
| struct data_t *data; |
| int i; |
| unsigned int i; |
| if (m->arch.imp_num & 0x80) { |
| /* Count records */ |
| for (i=0;imp_data80[i].vendor;i++) |
| ; |
| for (i = 0; imp_data80[i].vendor; i++); |
| if ((m->arch.imp_num & 0x7f) >= i) { |
| printf("imp=%d\n",m->arch.imp_num); |
| printf("imp=%d\n", m->arch.imp_num); |
| return; |
| } |
| data = &imp_data80[m->arch.imp_num & 0x7f]; |
| } else { |
| for (i=0;imp_data[i].vendor;i++) |
| ; |
| for (i = 0; imp_data[i].vendor; i++); |
| if (m->arch.imp_num >= i) { |
| printf("imp=%d\n",m->arch.imp_num); |
| printf("imp=%d\n", m->arch.imp_num); |
| return; |
| } |
| data = &imp_data[m->arch.imp_num]; |
| 127,7 → 125,7 |
| printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", |
| m->id, data->vendor, data->model, m->arch.rev_num >> 4, |
| m->arch.rev_num & 0xf, m->arch.imp_num); |
| m->arch.rev_num & 0xf, m->arch.imp_num); |
| } |
| /** @} |
| /branches/network/kernel/arch/mips32/include/drivers/arc.h |
|---|
| File deleted |
| /branches/network/kernel/arch/mips32/include/drivers/serial.h |
|---|
| 37,6 → 37,8 |
| #include <console/chardev.h> |
| #define SERIAL_ADDRESS 0x98000000 |
| #define SERIAL_MAX 4 |
| #define SERIAL_COM1 0x3f8 |
| #define SERIAL_COM1_IRQ 4 |
| 43,16 → 45,19 |
| #define SERIAL_COM2 0x2f8 |
| #define SERIAL_COM2_IRQ 3 |
| #define P_WRITEB(where,what) (*((volatile char *) (0xB8000000+where))=what) |
| #define P_READB(where) (*((volatile char *)(0xB8000000+where))) |
| #define P_WRITEB(where, what) (*((volatile char *) (SERIAL_ADDRESS + where)) = what) |
| #define P_READB(where) (*((volatile char *) (SERIAL_ADDRESS + where))) |
| #define SERIAL_READ(x) P_READB(x) |
| #define SERIAL_WRITE(x,c) P_WRITEB(x,c) |
| #define SERIAL_READ(x) P_READB(x) |
| #define SERIAL_WRITE(x, c) P_WRITEB(x, c) |
| /* Interrupt enable register */ |
| #define SERIAL_READ_IER(x) (P_READB((x) + 1)) |
| #define SERIAL_WRITE_IER(x,c) (P_WRITEB((x)+1,c)) |
| #define SERIAL_WRITE_IER(x,c) (P_WRITEB((x) + 1, c)) |
| /* Interrupt identification register */ |
| #define SERIAL_READ_IIR(x) (P_READB((x) + 2)) |
| /* Line status register */ |
| #define SERIAL_READ_LSR(x) (P_READB((x) + 5)) |
| #define TRANSMIT_EMPTY_BIT 5 |
| /branches/network/kernel/arch/mips32/include/drivers/msim.h |
|---|
| 35,6 → 35,11 |
| #ifndef KERN_mips32_MSIM_H_ |
| #define KERN_mips32_MSIM_H_ |
| /** Address of devices. */ |
| #define MSIM_VIDEORAM 0x90000000 |
| #define MSIM_KBD_ADDRESS 0x90000000 |
| #define MSIM_KBD_IRQ 2 |
| #include <console/chardev.h> |
| void msim_console(devno_t devno); |
| /branches/network/kernel/arch/mips32/include/mm/page.h |
|---|
| 40,8 → 40,6 |
| #define PAGE_WIDTH FRAME_WIDTH |
| #define PAGE_SIZE FRAME_SIZE |
| #define PAGE_COLOR_BITS 0 /* dummy */ |
| #ifndef __ASM__ |
| # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
| # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
| /branches/network/kernel/arch/mips32/include/mm/tlb.h |
|---|
| 35,6 → 35,9 |
| #ifndef KERN_mips32_TLB_H_ |
| #define KERN_mips32_TLB_H_ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/mm/asid.h> |
| #include <arch/exception.h> |
| #ifdef TLBCNT |
| 46,7 → 49,13 |
| #define TLB_WIRED 1 |
| #define TLB_KSTACK_WIRED_INDEX 0 |
| #define TLB_PAGE_MASK_16K (0x3<<13) |
| #define TLB_PAGE_MASK_4K (0x000 << 13) |
| #define TLB_PAGE_MASK_16K (0x003 << 13) |
| #define TLB_PAGE_MASK_64K (0x00f << 13) |
| #define TLB_PAGE_MASK_256K (0x03f << 13) |
| #define TLB_PAGE_MASK_1M (0x0ff << 13) |
| #define TLB_PAGE_MASK_4M (0x3ff << 13) |
| #define TLB_PAGE_MASK_16M (0xfff << 13) |
| #define PAGE_UNCACHED 2 |
| #define PAGE_CACHEABLE_EXC_WRITE 5 |
| 159,6 → 168,8 |
| extern void tlb_invalid(istate_t *istate); |
| extern void tlb_refill(istate_t *istate); |
| extern void tlb_modified(istate_t *istate); |
| extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn); |
| extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr); |
| #endif |
| /branches/network/kernel/arch/mips32/include/mm/as.h |
|---|
| 38,7 → 38,7 |
| #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 |
| #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0x9fffffff |
| #define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 |
| #define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff |
| /branches/network/kernel/arch/mips32/include/atomic.h |
|---|
| 58,13 → 58,13 |
| asm volatile ( |
| "1:\n" |
| " ll %0, %1\n" |
| " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " move %2, %0\n" |
| " sc %0, %1\n" |
| " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
| " nop\n" |
| : "=r" (tmp), "=m" (val->count), "=r" (v) |
| : "i" (i), "i" (0) |
| : "=&r" (tmp), "+m" (val->count), "=&r" (v) |
| : "r" (i), "i" (0) |
| ); |
| return v; |
| /branches/network/kernel/arch/mips32/include/barrier.h |
|---|
| 45,6 → 45,9 |
| #define read_barrier() asm volatile ("" ::: "memory") |
| #define write_barrier() asm volatile ("" ::: "memory") |
| #define smc_coherence(a) |
| #define smc_coherence_block(a, l) |
| #endif |
| /** @} |
| /branches/network/kernel/arch/mips32/include/memstr.h |
|---|
| 37,10 → 37,10 |
| #define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
| extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); |
| extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); |
| extern void memsetw(void *dst, size_t cnt, uint16_t x); |
| extern void memsetb(void *dst, size_t cnt, uint8_t x); |
| extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); |
| extern int memcmp(const void *a, const void *b, size_t cnt); |
| #endif |
| /branches/network/kernel/arch/mips32/include/types.h |
|---|
| 35,10 → 35,6 |
| #ifndef KERN_mips32_TYPES_H_ |
| #define KERN_mips32_TYPES_H_ |
| #define NULL 0 |
| #define false 0 |
| #define true 1 |
| typedef signed char int8_t; |
| typedef signed short int16_t; |
| typedef signed long int32_t; |
| 61,14 → 57,29 |
| typedef uint32_t unative_t; |
| typedef int32_t native_t; |
| typedef uint8_t bool; |
| typedef uint64_t thread_id_t; |
| typedef uint64_t task_id_t; |
| typedef uint32_t context_id_t; |
| #define PRIp "x" /**< Format for uintptr_t. */ |
| #define PRIs "u" /**< Format for size_t. */ |
| #define PRIc "u" /**< Format for count_t. */ |
| #define PRIi "u" /**< Format for index_t. */ |
| typedef int32_t inr_t; |
| typedef int32_t devno_t; |
| #define PRId8 "d" /**< Format for int8_t. */ |
| #define PRId16 "d" /**< Format for int16_t. */ |
| #define PRId32 "ld" /**< Format for int32_t. */ |
| #define PRId64 "lld" /**< Format for int64_t. */ |
| #define PRIdn "d" /**< Format for native_t. */ |
| #define PRIu8 "u" /**< Format for uint8_t. */ |
| #define PRIu16 "u" /**< Format for uint16_t. */ |
| #define PRIu32 "u" /**< Format for uint32_t. */ |
| #define PRIu64 "llu" /**< Format for uint64_t. */ |
| #define PRIun "u" /**< Format for unative_t. */ |
| #define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */ |
| #define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */ |
| #define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */ |
| #define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */ |
| #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ |
| /** Page Table Entry. */ |
| typedef struct { |
| unsigned g : 1; /**< Global bit. */ |
| /branches/network/kernel/arch/mips32/include/byteorder.h |
|---|
| 35,24 → 35,10 |
| #ifndef KERN_mips32_BYTEORDER_H_ |
| #define KERN_mips32_BYTEORDER_H_ |
| #include <byteorder.h> |
| #ifdef BIG_ENDIAN |
| #define uint32_t_le2host(n) uint32_t_byteorder_swap(n) |
| #define uint64_t_le2host(n) uint64_t_byteorder_swap(n) |
| #define uint32_t_be2host(n) (n) |
| #define uint64_t_be2host(n) (n) |
| #define ARCH_IS_BIG_ENDIAN |
| #else |
| #define uint32_t_le2host(n) (n) |
| #define uint64_t_le2host(n) (n) |
| #define uint32_t_be2host(n) uint32_t_byteorder_swap(n) |
| #define uint64_t_be2host(n) uint64_t_byteorder_swap(n) |
| #define ARCH_IS_LITTLE_ENDIAN |
| #endif |
| #endif |
| /branches/network/kernel/arch/mips32/include/context_offset.h |
|---|
| 42,6 → 42,24 |
| #define OFFSET_S8 0x28 |
| #define OFFSET_GP 0x2c |
| #ifdef KERNEL |
| # define OFFSET_IPL 0x30 |
| #else |
| # define OFFSET_TLS 0x30 |
| # define OFFSET_F20 0x34 |
| # define OFFSET_F21 0x38 |
| # define OFFSET_F22 0x3c |
| # define OFFSET_F23 0x40 |
| # define OFFSET_F24 0x44 |
| # define OFFSET_F25 0x48 |
| # define OFFSET_F26 0x4c |
| # define OFFSET_F27 0x50 |
| # define OFFSET_F28 0x54 |
| # define OFFSET_F29 0x58 |
| # define OFFSET_F30 0x5c |
| #endif /* KERNEL */ |
| /* istate_t */ |
| #define EOFFSET_AT 0x0 |
| #define EOFFSET_V0 0x4 |
| 79,4 → 97,122 |
| #define EOFFSET_K1 0x84 |
| #define REGISTER_SPACE 136 |
| #ifdef __ASM__ |
| #include <arch/asm/regname.h> |
| # ctx: address of the structure with saved context |
| .macro CONTEXT_SAVE_ARCH_CORE ctx:req |
| sw $s0,OFFSET_S0(\ctx) |
| sw $s1,OFFSET_S1(\ctx) |
| sw $s2,OFFSET_S2(\ctx) |
| sw $s3,OFFSET_S3(\ctx) |
| sw $s4,OFFSET_S4(\ctx) |
| sw $s5,OFFSET_S5(\ctx) |
| sw $s6,OFFSET_S6(\ctx) |
| sw $s7,OFFSET_S7(\ctx) |
| sw $s8,OFFSET_S8(\ctx) |
| sw $gp,OFFSET_GP(\ctx) |
| #ifndef KERNEL |
| sw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| mfc1 $t0,$20 |
| sw $t0, OFFSET_F20(\ctx) |
| mfc1 $t0,$21 |
| sw $t0, OFFSET_F21(\ctx) |
| mfc1 $t0,$22 |
| sw $t0, OFFSET_F22(\ctx) |
| mfc1 $t0,$23 |
| sw $t0, OFFSET_F23(\ctx) |
| mfc1 $t0,$24 |
| sw $t0, OFFSET_F24(\ctx) |
| mfc1 $t0,$25 |
| sw $t0, OFFSET_F25(\ctx) |
| mfc1 $t0,$26 |
| sw $t0, OFFSET_F26(\ctx) |
| mfc1 $t0,$27 |
| sw $t0, OFFSET_F27(\ctx) |
| mfc1 $t0,$28 |
| sw $t0, OFFSET_F28(\ctx) |
| mfc1 $t0,$29 |
| sw $t0, OFFSET_F29(\ctx) |
| mfc1 $t0,$30 |
| sw $t0, OFFSET_F30(\ctx) |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* KERNEL */ |
| sw $ra,OFFSET_PC(\ctx) |
| sw $sp,OFFSET_SP(\ctx) |
| .endm |
| # ctx: address of the structure with saved context |
| .macro CONTEXT_RESTORE_ARCH_CORE ctx:req |
| lw $s0,OFFSET_S0(\ctx) |
| lw $s1,OFFSET_S1(\ctx) |
| lw $s2,OFFSET_S2(\ctx) |
| lw $s3,OFFSET_S3(\ctx) |
| lw $s4,OFFSET_S4(\ctx) |
| lw $s5,OFFSET_S5(\ctx) |
| lw $s6,OFFSET_S6(\ctx) |
| lw $s7,OFFSET_S7(\ctx) |
| lw $s8,OFFSET_S8(\ctx) |
| lw $gp,OFFSET_GP(\ctx) |
| #ifndef KERNEL |
| lw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| lw $t0, OFFSET_F20(\ctx) |
| mtc1 $t0,$20 |
| lw $t0, OFFSET_F21(\ctx) |
| mtc1 $t0,$21 |
| lw $t0, OFFSET_F22(\ctx) |
| mtc1 $t0,$22 |
| lw $t0, OFFSET_F23(\ctx) |
| mtc1 $t0,$23 |
| lw $t0, OFFSET_F24(\ctx) |
| mtc1 $t0,$24 |
| lw $t0, OFFSET_F25(\ctx) |
| mtc1 $t0,$25 |
| lw $t0, OFFSET_F26(\ctx) |
| mtc1 $t0,$26 |
| lw $t0, OFFSET_F27(\ctx) |
| mtc1 $t0,$27 |
| lw $t0, OFFSET_F28(\ctx) |
| mtc1 $t0,$28 |
| lw $t0, OFFSET_F29(\ctx) |
| mtc1 $t0,$29 |
| lw $t0, OFFSET_F30(\ctx) |
| mtc1 $t0,$30 |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* KERNEL */ |
| lw $ra,OFFSET_PC(\ctx) |
| lw $sp,OFFSET_SP(\ctx) |
| .endm |
| #endif |
| #endif |