| /branches/network/kernel/arch/mips32/include/drivers/arc.h |
|---|
| File deleted |
| /branches/network/kernel/arch/mips32/include/drivers/serial.h |
|---|
| 37,6 → 37,8 |
| #include <console/chardev.h> |
| #define SERIAL_ADDRESS 0x98000000 |
| #define SERIAL_MAX 4 |
| #define SERIAL_COM1 0x3f8 |
| #define SERIAL_COM1_IRQ 4 |
| 43,16 → 45,19 |
| #define SERIAL_COM2 0x2f8 |
| #define SERIAL_COM2_IRQ 3 |
| #define P_WRITEB(where,what) (*((volatile char *) (0xB8000000+where))=what) |
| #define P_READB(where) (*((volatile char *)(0xB8000000+where))) |
| #define P_WRITEB(where, what) (*((volatile char *) (SERIAL_ADDRESS + where)) = what) |
| #define P_READB(where) (*((volatile char *) (SERIAL_ADDRESS + where))) |
| #define SERIAL_READ(x) P_READB(x) |
| #define SERIAL_WRITE(x,c) P_WRITEB(x,c) |
| #define SERIAL_READ(x) P_READB(x) |
| #define SERIAL_WRITE(x, c) P_WRITEB(x, c) |
| /* Interrupt enable register */ |
| #define SERIAL_READ_IER(x) (P_READB((x) + 1)) |
| #define SERIAL_WRITE_IER(x,c) (P_WRITEB((x)+1,c)) |
| #define SERIAL_WRITE_IER(x,c) (P_WRITEB((x) + 1, c)) |
| /* Interrupt identification register */ |
| #define SERIAL_READ_IIR(x) (P_READB((x) + 2)) |
| /* Line status register */ |
| #define SERIAL_READ_LSR(x) (P_READB((x) + 5)) |
| #define TRANSMIT_EMPTY_BIT 5 |
| /branches/network/kernel/arch/mips32/include/drivers/msim.h |
|---|
| 35,6 → 35,11 |
| #ifndef KERN_mips32_MSIM_H_ |
| #define KERN_mips32_MSIM_H_ |
| /** Address of devices. */ |
| #define MSIM_VIDEORAM 0x90000000 |
| #define MSIM_KBD_ADDRESS 0x90000000 |
| #define MSIM_KBD_IRQ 2 |
| #include <console/chardev.h> |
| void msim_console(devno_t devno); |
| /branches/network/kernel/arch/mips32/include/mm/page.h |
|---|
| 40,8 → 40,6 |
| #define PAGE_WIDTH FRAME_WIDTH |
| #define PAGE_SIZE FRAME_SIZE |
| #define PAGE_COLOR_BITS 0 /* dummy */ |
| #ifndef __ASM__ |
| # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
| # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
| /branches/network/kernel/arch/mips32/include/mm/tlb.h |
|---|
| 35,6 → 35,9 |
| #ifndef KERN_mips32_TLB_H_ |
| #define KERN_mips32_TLB_H_ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/mm/asid.h> |
| #include <arch/exception.h> |
| #ifdef TLBCNT |
| 46,7 → 49,13 |
| #define TLB_WIRED 1 |
| #define TLB_KSTACK_WIRED_INDEX 0 |
| #define TLB_PAGE_MASK_16K (0x3<<13) |
| #define TLB_PAGE_MASK_4K (0x000 << 13) |
| #define TLB_PAGE_MASK_16K (0x003 << 13) |
| #define TLB_PAGE_MASK_64K (0x00f << 13) |
| #define TLB_PAGE_MASK_256K (0x03f << 13) |
| #define TLB_PAGE_MASK_1M (0x0ff << 13) |
| #define TLB_PAGE_MASK_4M (0x3ff << 13) |
| #define TLB_PAGE_MASK_16M (0xfff << 13) |
| #define PAGE_UNCACHED 2 |
| #define PAGE_CACHEABLE_EXC_WRITE 5 |
| 159,6 → 168,8 |
| extern void tlb_invalid(istate_t *istate); |
| extern void tlb_refill(istate_t *istate); |
| extern void tlb_modified(istate_t *istate); |
| extern void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn); |
| extern void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr); |
| #endif |
| /branches/network/kernel/arch/mips32/include/mm/as.h |
|---|
| 38,7 → 38,7 |
| #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 |
| #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0x9fffffff |
| #define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 |
| #define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff |
| /branches/network/kernel/arch/mips32/include/atomic.h |
|---|
| 58,13 → 58,13 |
| asm volatile ( |
| "1:\n" |
| " ll %0, %1\n" |
| " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " addu %0, %0, %3\n" /* same as addi, but never traps on overflow */ |
| " move %2, %0\n" |
| " sc %0, %1\n" |
| " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
| " nop\n" |
| : "=r" (tmp), "=m" (val->count), "=r" (v) |
| : "i" (i), "i" (0) |
| : "=&r" (tmp), "+m" (val->count), "=&r" (v) |
| : "r" (i), "i" (0) |
| ); |
| return v; |
| /branches/network/kernel/arch/mips32/include/barrier.h |
|---|
| 45,6 → 45,9 |
| #define read_barrier() asm volatile ("" ::: "memory") |
| #define write_barrier() asm volatile ("" ::: "memory") |
| #define smc_coherence(a) |
| #define smc_coherence_block(a, l) |
| #endif |
| /** @} |
| /branches/network/kernel/arch/mips32/include/memstr.h |
|---|
| 37,10 → 37,10 |
| #define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
| extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); |
| extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); |
| extern void memsetw(void *dst, size_t cnt, uint16_t x); |
| extern void memsetb(void *dst, size_t cnt, uint8_t x); |
| extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); |
| extern int memcmp(const void *a, const void *b, size_t cnt); |
| #endif |
| /branches/network/kernel/arch/mips32/include/types.h |
|---|
| 35,10 → 35,6 |
| #ifndef KERN_mips32_TYPES_H_ |
| #define KERN_mips32_TYPES_H_ |
| #define NULL 0 |
| #define false 0 |
| #define true 1 |
| typedef signed char int8_t; |
| typedef signed short int16_t; |
| typedef signed long int32_t; |
| 61,14 → 57,29 |
| typedef uint32_t unative_t; |
| typedef int32_t native_t; |
| typedef uint8_t bool; |
| typedef uint64_t thread_id_t; |
| typedef uint64_t task_id_t; |
| typedef uint32_t context_id_t; |
| #define PRIp "x" /**< Format for uintptr_t. */ |
| #define PRIs "u" /**< Format for size_t. */ |
| #define PRIc "u" /**< Format for count_t. */ |
| #define PRIi "u" /**< Format for index_t. */ |
| typedef int32_t inr_t; |
| typedef int32_t devno_t; |
| #define PRId8 "d" /**< Format for int8_t. */ |
| #define PRId16 "d" /**< Format for int16_t. */ |
| #define PRId32 "ld" /**< Format for int32_t. */ |
| #define PRId64 "lld" /**< Format for int64_t. */ |
| #define PRIdn "d" /**< Format for native_t. */ |
| #define PRIu8 "u" /**< Format for uint8_t. */ |
| #define PRIu16 "u" /**< Format for uint16_t. */ |
| #define PRIu32 "u" /**< Format for uint32_t. */ |
| #define PRIu64 "llu" /**< Format for uint64_t. */ |
| #define PRIun "u" /**< Format for unative_t. */ |
| #define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */ |
| #define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */ |
| #define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */ |
| #define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */ |
| #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ |
| /** Page Table Entry. */ |
| typedef struct { |
| unsigned g : 1; /**< Global bit. */ |
| /branches/network/kernel/arch/mips32/include/byteorder.h |
|---|
| 35,24 → 35,10 |
| #ifndef KERN_mips32_BYTEORDER_H_ |
| #define KERN_mips32_BYTEORDER_H_ |
| #include <byteorder.h> |
| #ifdef BIG_ENDIAN |
| #define uint32_t_le2host(n) uint32_t_byteorder_swap(n) |
| #define uint64_t_le2host(n) uint64_t_byteorder_swap(n) |
| #define uint32_t_be2host(n) (n) |
| #define uint64_t_be2host(n) (n) |
| #define ARCH_IS_BIG_ENDIAN |
| #else |
| #define uint32_t_le2host(n) (n) |
| #define uint64_t_le2host(n) (n) |
| #define uint32_t_be2host(n) uint32_t_byteorder_swap(n) |
| #define uint64_t_be2host(n) uint64_t_byteorder_swap(n) |
| #define ARCH_IS_LITTLE_ENDIAN |
| #endif |
| #endif |
| /branches/network/kernel/arch/mips32/include/context_offset.h |
|---|
| 42,6 → 42,24 |
| #define OFFSET_S8 0x28 |
| #define OFFSET_GP 0x2c |
| #ifdef KERNEL |
| # define OFFSET_IPL 0x30 |
| #else |
| # define OFFSET_TLS 0x30 |
| # define OFFSET_F20 0x34 |
| # define OFFSET_F21 0x38 |
| # define OFFSET_F22 0x3c |
| # define OFFSET_F23 0x40 |
| # define OFFSET_F24 0x44 |
| # define OFFSET_F25 0x48 |
| # define OFFSET_F26 0x4c |
| # define OFFSET_F27 0x50 |
| # define OFFSET_F28 0x54 |
| # define OFFSET_F29 0x58 |
| # define OFFSET_F30 0x5c |
| #endif /* KERNEL */ |
| /* istate_t */ |
| #define EOFFSET_AT 0x0 |
| #define EOFFSET_V0 0x4 |
| 79,4 → 97,122 |
| #define EOFFSET_K1 0x84 |
| #define REGISTER_SPACE 136 |
| #ifdef __ASM__ |
| #include <arch/asm/regname.h> |
| # ctx: address of the structure with saved context |
| .macro CONTEXT_SAVE_ARCH_CORE ctx:req |
| sw $s0,OFFSET_S0(\ctx) |
| sw $s1,OFFSET_S1(\ctx) |
| sw $s2,OFFSET_S2(\ctx) |
| sw $s3,OFFSET_S3(\ctx) |
| sw $s4,OFFSET_S4(\ctx) |
| sw $s5,OFFSET_S5(\ctx) |
| sw $s6,OFFSET_S6(\ctx) |
| sw $s7,OFFSET_S7(\ctx) |
| sw $s8,OFFSET_S8(\ctx) |
| sw $gp,OFFSET_GP(\ctx) |
| #ifndef KERNEL |
| sw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| mfc1 $t0,$20 |
| sw $t0, OFFSET_F20(\ctx) |
| mfc1 $t0,$21 |
| sw $t0, OFFSET_F21(\ctx) |
| mfc1 $t0,$22 |
| sw $t0, OFFSET_F22(\ctx) |
| mfc1 $t0,$23 |
| sw $t0, OFFSET_F23(\ctx) |
| mfc1 $t0,$24 |
| sw $t0, OFFSET_F24(\ctx) |
| mfc1 $t0,$25 |
| sw $t0, OFFSET_F25(\ctx) |
| mfc1 $t0,$26 |
| sw $t0, OFFSET_F26(\ctx) |
| mfc1 $t0,$27 |
| sw $t0, OFFSET_F27(\ctx) |
| mfc1 $t0,$28 |
| sw $t0, OFFSET_F28(\ctx) |
| mfc1 $t0,$29 |
| sw $t0, OFFSET_F29(\ctx) |
| mfc1 $t0,$30 |
| sw $t0, OFFSET_F30(\ctx) |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* KERNEL */ |
| sw $ra,OFFSET_PC(\ctx) |
| sw $sp,OFFSET_SP(\ctx) |
| .endm |
| # ctx: address of the structure with saved context |
| .macro CONTEXT_RESTORE_ARCH_CORE ctx:req |
| lw $s0,OFFSET_S0(\ctx) |
| lw $s1,OFFSET_S1(\ctx) |
| lw $s2,OFFSET_S2(\ctx) |
| lw $s3,OFFSET_S3(\ctx) |
| lw $s4,OFFSET_S4(\ctx) |
| lw $s5,OFFSET_S5(\ctx) |
| lw $s6,OFFSET_S6(\ctx) |
| lw $s7,OFFSET_S7(\ctx) |
| lw $s8,OFFSET_S8(\ctx) |
| lw $gp,OFFSET_GP(\ctx) |
| #ifndef KERNEL |
| lw $k1,OFFSET_TLS(\ctx) |
| # ifdef CONFIG_MIPS_FPU |
| lw $t0, OFFSET_F20(\ctx) |
| mtc1 $t0,$20 |
| lw $t0, OFFSET_F21(\ctx) |
| mtc1 $t0,$21 |
| lw $t0, OFFSET_F22(\ctx) |
| mtc1 $t0,$22 |
| lw $t0, OFFSET_F23(\ctx) |
| mtc1 $t0,$23 |
| lw $t0, OFFSET_F24(\ctx) |
| mtc1 $t0,$24 |
| lw $t0, OFFSET_F25(\ctx) |
| mtc1 $t0,$25 |
| lw $t0, OFFSET_F26(\ctx) |
| mtc1 $t0,$26 |
| lw $t0, OFFSET_F27(\ctx) |
| mtc1 $t0,$27 |
| lw $t0, OFFSET_F28(\ctx) |
| mtc1 $t0,$28 |
| lw $t0, OFFSET_F29(\ctx) |
| mtc1 $t0,$29 |
| lw $t0, OFFSET_F30(\ctx) |
| mtc1 $t0,$30 |
| # endif /* CONFIG_MIPS_FPU */ |
| #endif /* KERNEL */ |
| lw $ra,OFFSET_PC(\ctx) |
| lw $sp,OFFSET_SP(\ctx) |
| .endm |
| #endif |
| #endif |