| 34,7 → 34,6 |
|---|
| */ |
| #include <panic.h> |
| #include <arch/exception.h> |
| #include <arch/debug/print.h> |
| #include <arch/mm/page_fault.h> |
| #include <mm/as.h> |
| #include <genarch/mm/page_pt.h> |
| 49,12 → 48,13 |
|---|
| static inline fault_status_t read_fault_status_register(void) |
| { |
| fault_status_union_t fsu; |
| |
| |
| /* fault status is stored in CP15 register 5 */ |
| asm volatile ( |
| "mrc p15, 0, %0, c5, c0, 0" |
| : "=r"(fsu.dummy) |
| "mrc p15, 0, %[dummy], c5, c0, 0" |
| : [dummy] "=r" (fsu.dummy) |
| ); |
| |
| return fsu.fs; |
| } |
| |
| 61,17 → 61,18 |
|---|
| /** Returns FAR (fault address register) content. |
| * |
| * @return FAR (fault address register) content (address that caused a page |
| * fault) |
| * fault) |
| */ |
| static inline uintptr_t read_fault_address_register(void) |
| { |
| uintptr_t ret; |
| |
| |
| /* fault adress is stored in CP15 register 6 */ |
| asm volatile ( |
| "mrc p15, 0, %0, c6, c0, 0" |
| : "=r"(ret) |
| "mrc p15, 0, %[ret], c6, c0, 0" |
| : [ret] "=r" (ret) |
| ); |
| |
| return ret; |
| } |
| |
| 80,29 → 81,26 |
|---|
| * @param instr Instruction |
| * |
| * @return true when instruction is load/store, false otherwise |
| * |
| */ |
| static inline bool is_load_store_instruction(instruction_t instr) |
| { |
| /* load store immediate offset */ |
| if (instr.type == 0x2) { |
| if (instr.type == 0x2) |
| return true; |
| } |
| |
| |
| /* load store register offset */ |
| if (instr.type == 0x3 && instr.bit4 == 0) { |
| if ((instr.type == 0x3) && (instr.bit4 == 0)) |
| return true; |
| } |
| |
| |
| /* load store multiple */ |
| if (instr.type == 0x4) { |
| if (instr.type == 0x4) |
| return true; |
| } |
| |
| |
| /* oprocessor load/store */ |
| if (instr.type == 0x6) { |
| if (instr.type == 0x6) |
| return true; |
| } |
| |
| |
| return false; |
| } |
| |
| 115,12 → 113,11 |
|---|
| static inline bool is_swap_instruction(instruction_t instr) |
| { |
| /* swap, swapb instruction */ |
| if (instr.type == 0x0 && |
| (instr.opcode == 0x8 || instr.opcode == 0xa) && |
| instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
| if ((instr.type == 0x0) && |
| ((instr.opcode == 0x8) || (instr.opcode == 0xa)) && |
| (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1)) |
| return true; |
| } |
| |
| |
| return false; |
| } |
| |
| 142,8 → 139,8 |
|---|
| |
| /* undefined instructions */ |
| if (instr.condition == 0xf) { |
| panic("page_fault - instruction doesn't access memory " |
| "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
| panic("page_fault - instruction does not access memory " |
| "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
| return PF_ACCESS_EXEC; |
| } |
| |
| 162,7 → 159,7 |
|---|
| } |
| |
| panic("page_fault - instruction doesn't access memory " |
| "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
| "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
| |
| return PF_ACCESS_EXEC; |
| } |
| 184,12 → 181,12 |
|---|
| |
| if (ret == AS_PF_FAULT) { |
| print_istate(istate); |
| dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
| printf("page fault - pc: %x, va: %x, status: %x(%x), " |
| "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
| access); |
| |
| fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
| panic("page fault\n"); |
| |
| fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
| panic("Page fault."); |
| } |
| } |
| |
| 203,9 → 200,9 |
|---|
| int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
| |
| if (ret == AS_PF_FAULT) { |
| dprintf("prefetch_abort\n"); |
| printf("prefetch_abort\n"); |
| print_istate(istate); |
| panic("page fault - prefetch_abort at address: %x\n", |
| panic("page fault - prefetch_abort at address: %x.", |
| istate->pc); |
| } |
| } |