WebSVN – HelenOS – Path Comparison – / – /branches/network/kernel/arch/ Rev 4152 and /branches/network/kernel/arch/ Rev 4153

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/branches/network/kernel/arch/ia32xen/include/barrier.h
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/branches/network/kernel/arch/ia32xen/include/debug.h
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/branches/network/kernel/arch/ia32xen/include/cpu.h
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/branches/network/kernel/arch/ia32xen/include/context_offset.h
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/branches/network/kernel/arch/ia32xen/include/interrupt.h
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/branches/network/kernel/arch/ia32xen/include/fpu_context.h
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/branches/network/kernel/arch/ia32xen/include/cycle.h
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/branches/network/kernel/arch/ia32xen/include/smp
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/branches/network/kernel/arch/ia32xen/include/arg.h
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/branches/network/kernel/arch/ia32xen/include/atomic.h
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/branches/network/kernel/arch/ia32xen/include/faddr.h
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/branches/network/kernel/arch/ia32xen/include/context.h
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/branches/network/kernel/arch/ia32xen/src/context.S
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 /branches/network/kernel/arch/sparc64/_link.ld.in
 ,8 → 1,8
 /** SPARC64 linker script
  *
  *  It is ELF format, but its only section looks like this:
- *  kernel text
- *  kernel data
+ *   kernel text
+ *   kernel data
  *
  */
 ,7 → 11,7
 ENTRY(kernel_image_start)
 SECTIONS {
-    .image VMA: AT (LMA) {
+    .image VMA: AT (LMA) {
         ktext_start = .;
         *(K_TEXT_START)
         *(.text);
 ,23 → 21,23
         *(K_DATA_START)
         *(.rodata);
         *(.rodata.*);
-        *(.data);       /* initialized data */
+        *(.data);                   /* initialized data */
         *(.sdata);
         *(.sdata2);
         *(.sbss);
         . = ALIGN(8);
         hardcoded_ktext_size = .;
-        QUAD(ktext_end - ktext_start);
+        QUAD(ktext_end - ktext_start);
         hardcoded_kdata_size = .;
         QUAD(kdata_end - kdata_start);
         hardcoded_load_address = .;
         QUAD(VMA);
-        *(.bss);        /* uninitialized static variables */
-        *(COMMON);      /* global variables */
+        *(.bss);                    /* uninitialized static variables */
+        *(COMMON);                  /* global variables */
         symbol_table = .;
-                *(symtab.*);            /* Symbol table, must be LAST symbol!*/
+        *(symtab.*);                /* Symbol table, must be LAST symbol!*/
         kdata_end = .;
     }
 ,5 → 44,5
     /DISCARD/ : {
         *(*);
     }
 }

 /branches/network/kernel/arch/sparc64/include/regdef.h
 ,8 → 55,11
 #define WSTATE_NORMAL(n)    (n)
 #define WSTATE_OTHER(n)     ((n) << 3)
-#define UPA_CONFIG_MID_SHIFT    17
-#define UPA_CONFIG_MID_MASK     0x1f
+/*
+ * The following definitions concern the UPA_CONFIG register on US and the
+ * FIREPLANE_CONFIG register on US3.
+ */
+#define ICBUS_CONFIG_MID_SHIFT    17
 #endif

 /branches/network/kernel/arch/sparc64/include/cpu_node.h
 ,0 → 1,59
+/*
+ * Copyright (c) 2005 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_sparc64_CPU_NODE_H_
+#define KERN_sparc64_CPU_NODE_H_
+#include <genarch/ofw/ofw_tree.h>
+/** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp").
+ *
+ *  Depending on the machine type (and possibly the OFW version), CPUs can be
+ *  at "/" or at "/ssm@0,0".
+ */
+static inline ofw_tree_node_t *cpus_parent(void)
+{
+    ofw_tree_node_t *parent;
+    parent = ofw_tree_find_child(ofw_tree_lookup("/"), "ssm@0,0");
+    if (parent == NULL)
+        parent = ofw_tree_lookup("/");
+    return parent;
+}
+#endif
+/** @}
+ */

/branches/network/kernel/arch/sparc64/include/fpu_context.h
37,7 → 37,6

#include <arch/types.h>

#define ARCH_HAS_FPU
#define FPU_CONTEXT_ALIGN 8

typedef struct {

 /branches/network/kernel/arch/sparc64/include/types.h
 ,6 → 57,9
 typedef uint64_t unative_t;
 typedef int64_t native_t;
+typedef struct {
+} fncptr_t;
 /**< Formats for uintptr_t, size_t, count_t and index_t */
 #define PRIp "llx"
 #define PRIs "llu"

 /branches/network/kernel/arch/sparc64/include/boot/boot.h
 ,9 → 48,12
 #define TASKMAP_MAX_RECORDS 32
 #define MEMMAP_MAX_RECORDS  32
+#define BOOTINFO_TASK_NAME_BUFLEN 32
 typedef struct {
     void * addr;
     uint32_t size;
+    char name[BOOTINFO_TASK_NAME_BUFLEN];
 } utask_t;
 typedef struct {

 /branches/network/kernel/arch/sparc64/include/arch.h
 ,10 → 41,16
 #define ASI_AIUS        0x11    /** Access to secondary context with user privileges. */
 #define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
 #define ASI_DCACHE_TAG      0x47    /** ASI D-Cache Tag. */
-#define ASI_UPA_CONFIG      0x4a    /** ASI of the UPA_CONFIG register. */
+#define ASI_ICBUS_CONFIG        0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
 #define NWINDOWS        8   /** Number of register window sets. */
+#ifndef __ASM__
+extern void arch_pre_main(void);
+#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/asm.h
 ,7 → 42,56
 #include <arch/register.h>
 #include <config.h>
 #include <arch/stack.h>
+#include <arch/barrier.h>
+static inline void pio_write_8(ioport8_t *port, uint8_t v)
+{
+    *port = v;
+    memory_barrier();
+}
+static inline void pio_write_16(ioport16_t *port, uint16_t v)
+{
+    *port = v;
+    memory_barrier();
+}
+static inline void pio_write_32(ioport32_t *port, uint32_t v)
+{
+    *port = v;
+    memory_barrier();
+}
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
+    uint8_t rv;
+    rv = *port;
+    memory_barrier();
+    return rv;
+}
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    uint16_t rv;
+    rv = *port;
+    memory_barrier();
+    return rv;
+}
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    uint32_t rv;
+    rv = *port;
+    memory_barrier();
+    return rv;
+}
 /** Read Processor State register.
  *
  * @return Value of PSTATE register.
 ,6 → 136,28
     asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
 }
+/** Read STICK_compare Register.
+ *
+ * @return Value of STICK_compare register.
+ */
+static inline uint64_t stick_compare_read(void)
+{
+    uint64_t v;
+    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
+    return v;
+}
+/** Write STICK_compare Register.
+ *
+ * @param v New value of STICK_comapre register.
+ */
+static inline void stick_compare_write(uint64_t v)
+{
+    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
+}
 /** Read TICK Register.
  *
  * @return Value of TICK register.
 ,15 → 429,6
     asm volatile ("wrpr %g0, %g0, %tl\n");
 }
-/** Read UPA_CONFIG register.
- *
- * @return Value of the UPA_CONFIG register.
- */
-static inline uint64_t upa_config_read(void)
-{
-    return asi_u64_read(ASI_UPA_CONFIG, 0);
-}
 extern void cpu_halt(void);
 extern void cpu_sleep(void);
 extern void asm_delay_loop(const uint32_t usec);

 /branches/network/kernel/arch/sparc64/include/trap/syscall.h
 ,26 → 31,14
  */
 /**
  * @file
- * @brief This file contains the trap_instruction handler.
- *
- * The trap_instruction trap is used to implement syscalls.
+ * @brief
  */
 #ifndef KERN_sparc64_SYSCALL_TRAP_H_
 #define KERN_sparc64_SYSCALL_TRAP_H_
-#define TT_TRAP_INSTRUCTION(n)      (0x100 + (n))
-#define TT_TRAP_INSTRUCTION_LAST    TT_TRAP_INSTRUCTION(127)
+#define TT_TRAP_INSTRUCTION_0       0x100
-#ifdef __ASM__
-.macro TRAP_INSTRUCTION n
-    ba trap_instruction_handler
-    mov TT_TRAP_INSTRUCTION(\n) - TT_TRAP_INSTRUCTION(0), %g2
-.endm
-#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/trap/regwin.h
 ,6 → 39,7
 #include <arch/stack.h>
 #include <arch/arch.h>
+#include <align.h>
 #define TT_CLEAN_WINDOW         0x24
 #define TT_SPILL_0_NORMAL       0x80    /* kernel spills */
 ,6 → 73,11
 #define I6_OFFSET   112
 #define I7_OFFSET   120
+/* Uspace Window Buffer constants. */
+#define UWB_SIZE    ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE)
+#define UWB_ALIGNMENT   1024
+#define UWB_ASIZE   ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT)
 #ifdef __ASM__
 /*

 /branches/network/kernel/arch/sparc64/include/trap/interrupt.h
 ,21 → 49,43
 /* Interrupt ASI registers. */
-#define ASI_UDB_INTR_W          0x77
+#define ASI_INTR_W          0x77
 #define ASI_INTR_DISPATCH_STATUS    0x48
-#define ASI_UDB_INTR_R          0x7f
+#define ASI_INTR_R          0x7f
 #define ASI_INTR_RECEIVE        0x49
-/* VA's used with ASI_UDB_INTR_W register. */
+/* VA's used with ASI_INTR_W register. */
+#if defined (US)
 #define ASI_UDB_INTR_W_DATA_0   0x40
 #define ASI_UDB_INTR_W_DATA_1   0x50
 #define ASI_UDB_INTR_W_DATA_2   0x60
-#define ASI_UDB_INTR_W_DISPATCH 0x70
+#elif defined (US3)
+#define VA_INTR_W_DATA_0    0x40
+#define VA_INTR_W_DATA_1    0x48
+#define VA_INTR_W_DATA_2    0x50
+#define VA_INTR_W_DATA_3    0x58
+#define VA_INTR_W_DATA_4    0x60
+#define VA_INTR_W_DATA_5    0x68
+#define VA_INTR_W_DATA_6    0x80
+#define VA_INTR_W_DATA_7    0x88
+#endif
+#define VA_INTR_W_DISPATCH  0x70
-/* VA's used with ASI_UDB_INTR_R register. */
+/* VA's used with ASI_INTR_R register. */
+#if defined(US)
 #define ASI_UDB_INTR_R_DATA_0   0x40
 #define ASI_UDB_INTR_R_DATA_1   0x50
 #define ASI_UDB_INTR_R_DATA_2   0x60
+#elif defined (US3)
+#define VA_INTR_R_DATA_0    0x40
+#define VA_INTR_R_DATA_1    0x48
+#define VA_INTR_R_DATA_2    0x50
+#define VA_INTR_R_DATA_3    0x58
+#define VA_INTR_R_DATA_4    0x60
+#define VA_INTR_R_DATA_5    0x68
+#define VA_INTR_R_DATA_6    0x80
+#define VA_INTR_R_DATA_7    0x88
+#endif
 /* Shifts in the Interrupt Vector Dispatch virtual address. */
 #define INTR_VEC_DISPATCH_MID_SHIFT 14

 /branches/network/kernel/arch/sparc64/include/mm/frame.h
 ,8 → 59,13
 union frame_address {
     uintptr_t address;
     struct {
+#if defined (US)
         unsigned : 23;
         uint64_t pfn : 28;      /**< Physical Frame Number. */
+#elif defined (US3)
+        unsigned : 21;
+        uint64_t pfn : 30;      /**< Physical Frame Number. */
+#endif
         unsigned offset : 13;       /**< Offset. */
     } __attribute__ ((packed));
 };

 /branches/network/kernel/arch/sparc64/include/mm/tte.h
 ,6 → 50,7
 #include <arch/types.h>
+/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
 #define VA_TAG_PAGE_SHIFT   22
 /** Translation Table Entry - Tag. */
 ,8 → 76,13
         unsigned nfo : 1;   /**< No-Fault-Only. */
         unsigned ie : 1;    /**< Invert Endianness. */
         unsigned soft2 : 9; /**< Software defined field. */
+#if defined (US)
         unsigned diag : 9;  /**< Diagnostic data. */
         unsigned pfn : 28;  /**< Physical Address bits, bits 40:13. */
+#elif defined (US3)
+        unsigned : 7;       /**< Reserved. */
+        unsigned pfn : 30;  /**< Physical Address bits, bits 42:13 */
+#endif
         unsigned soft : 6;  /**< Software defined field. */
         unsigned l : 1;     /**< Lock. */
         unsigned cp : 1;    /**< Cacheable in physically indexed cache. */

 /branches/network/kernel/arch/sparc64/include/mm/cache_spec.h
 ,19 → 38,20
 /*
  * The following macros are valid for the following processors:
  *
- *  UltraSPARC, UltraSPARC II, UltraSPARC IIi
+ *  UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III,
+ *  UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+
  *
  * Should we support other UltraSPARC processors, we need to make sure that
  * the macros are defined correctly for them.
  */
+#if defined (US)
 #define DCACHE_SIZE     (16 * 1024)
+#elif defined (US3)
+#define DCACHE_SIZE     (64 * 1024)
+#endif
 #define DCACHE_LINE_SIZE    32
-#define ICACHE_SIZE     (16 * 1024)
-#define ICACHE_WAYS     2
-#define ICACHE_LINE_SIZE    32
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/mm/mmu.h
 ,8 → 35,10
 #ifndef KERN_sparc64_MMU_H_
 #define KERN_sparc64_MMU_H_
+#if defined(US)
 /* LSU Control Register ASI. */
 #define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
+#endif
 /* I-MMU ASIs. */
 #define ASI_IMMU            0x50
 ,7 → 54,12
 #define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
 #define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
 #define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
+#if defined (US3)
+#define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
+#define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
+#endif
 /* D-MMU ASIs. */
 #define ASI_DMMU            0x58
 #define ASI_DMMU_TSB_8KB_PTR_REG    0x59
 ,6 → 80,11
 #define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
 #define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
 #define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
+#if defined (US3)
+#define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
+#define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
+#define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
+#endif
 #ifndef __ASM__
 ,6 → 92,7
 #include <arch/barrier.h>
 #include <arch/types.h>
+#if defined(US)
 /** LSU Control Register. */
 typedef union {
     uint64_t value;
 ,6 → 113,7
     } __attribute__ ((packed));
 } lsu_cr_reg_t;
+#endif /* US */
 #endif /* !def __ASM__ */

 /branches/network/kernel/arch/sparc64/include/mm/tlb.h
 ,9 → 35,17
 #ifndef KERN_sparc64_TLB_H_
 #define KERN_sparc64_TLB_H_
+#if defined (US)
 #define ITLB_ENTRY_COUNT        64
 #define DTLB_ENTRY_COUNT        64
+#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
+#endif
+/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
+#if defined (US3)
+#define DTLB_MAX_LOCKED_ENTRIES     16
+#endif
 #define MEM_CONTEXT_KERNEL      0
 #define MEM_CONTEXT_TEMP        1
 ,6 → 61,9
 /* TLB Demap Operation types. */
 #define TLB_DEMAP_PAGE      0
 #define TLB_DEMAP_CONTEXT   1
+#if defined (US3)
+#define TLB_DEMAP_ALL       2
+#endif
 #define TLB_DEMAP_TYPE_SHIFT    6
 ,6 → 72,18
 #define TLB_DEMAP_SECONDARY 1
 #define TLB_DEMAP_NUCLEUS   2
+/* There are more TLBs in one MMU in US3, their codes are defined here. */
+#if defined (US3)
+/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
+#define TLB_DSMALL  0
+#define TLB_DBIG_0  2
+#define TLB_DBIG_1  3
+/* I-MMU: one small (16-entry) TLB and one big TLB */
+#define TLB_ISMALL  0
+#define TLB_IBIG    2
+#endif
 #define TLB_DEMAP_CONTEXT_SHIFT 4
 /* TLB Tag Access shifts */
 ,6 → 99,8
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <arch/types.h>
+#include <arch/register.h>
+#include <arch/cpu.h>
 union tlb_context_reg {
     uint64_t v;
 ,6 → 115,9
 typedef tte_data_t tlb_data_t;
 /** I-/D-TLB Data Access Address in Alternate Space. */
+#if defined (US)
 union tlb_data_access_addr {
     uint64_t value;
     struct {
 ,9 → 126,54
         unsigned : 3;
     } __attribute__ ((packed));
 };
-typedef union tlb_data_access_addr tlb_data_access_addr_t;
-typedef union tlb_data_access_addr tlb_tag_read_addr_t;
+typedef union tlb_data_access_addr dtlb_data_access_addr_t;
+typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
+typedef union tlb_data_access_addr itlb_data_access_addr_t;
+typedef union tlb_data_access_addr itlb_tag_read_addr_t;
+#elif defined (US3)
+/*
+ * In US3, I-MMU and D-MMU have different formats of the data
+ * access register virtual address. In the corresponding
+ * structures the member variable for the entry number is
+ * called "local_tlb_entry" - it contrasts with the "tlb_entry"
+ * for the US data access register VA structure. The rationale
+ * behind this is to prevent careless mistakes in the code
+ * caused by setting only the entry number and not the TLB
+ * number in the US3 code (when taking the code from US).
+ */
+union dtlb_data_access_addr {
+    uint64_t value;
+    struct {
+        uint64_t : 45;
+        unsigned : 1;
+        unsigned tlb_number : 2;
+        unsigned : 4;
+        unsigned local_tlb_entry : 9;
+        unsigned : 3;
+    } __attribute__ ((packed));
+};
+typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
+typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
+union itlb_data_access_addr {
+    uint64_t value;
+    struct {
+        uint64_t : 45;
+        unsigned : 1;
+        unsigned tlb_number : 2;
+        unsigned : 6;
+        unsigned local_tlb_entry : 7;
+        unsigned : 3;
+    } __attribute__ ((packed));
+};
+typedef union itlb_data_access_addr itlb_data_access_addr_t;
+typedef union itlb_data_access_addr itlb_tag_read_addr_t;
+#endif
 /** I-/D-TLB Tag Read Register. */
 union tlb_tag_read_reg {
     uint64_t value;
 ,8 → 191,13
     uint64_t value;
     struct {
         uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
+#if defined (US)
         unsigned : 6;       /**< Ignored. */
         unsigned type : 1;  /**< The type of demap operation. */
+#elif defined (US3)
+        unsigned : 5;       /**< Ignored. */
+        unsigned type: 2;   /**< The type of demap operation. */
+#endif
         unsigned context : 2;   /**< Context register selection. */
         unsigned : 4;       /**< Zero. */
     } __attribute__ ((packed));
 ,10 → 208,19
 union tlb_sfsr_reg {
     uint64_t value;
     struct {
+#if defined (US)
         unsigned long : 40; /**< Implementation dependent. */
         unsigned asi : 8;   /**< ASI. */
         unsigned : 2;
         unsigned ft : 7;    /**< Fault type. */
+#elif defined (US3)
+        unsigned long : 39; /**< Implementation dependent. */
+        unsigned nf : 1;    /**< Non-faulting load. */
+        unsigned asi : 8;   /**< ASI. */
+        unsigned tm : 1;    /**< I-TLB miss. */
+        unsigned : 3;       /**< Reserved. */
+        unsigned ft : 5;    /**< Fault type. */
+#endif
         unsigned e : 1;     /**< Side-effect bit. */
         unsigned ct : 2;    /**< Context Register selection. */
         unsigned pr : 1;    /**< Privilege bit. */
 ,9 → 231,53
 };
 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
+#if defined (US3)
+/*
+ * Functions for determining the number of entries in TLBs. They either return
+ * a constant value or a value based on the CPU autodetection.
+ */
+/**
+ * Determine the number of entries in the DMMU's small TLB.
+ */
+static inline uint16_t tlb_dsmall_size(void)
+{
+    return 16;
+}
+/**
+ * Determine the number of entries in each DMMU's big TLB.
+ */
+static inline uint16_t tlb_dbig_size(void)
+{
+    return 512;
+}
+/**
+ * Determine the number of entries in the IMMU's small TLB.
+ */
+static inline uint16_t tlb_ismall_size(void)
+{
+    return 16;
+}
+/**
+ * Determine the number of entries in the IMMU's big TLB.
+ */
+static inline uint16_t tlb_ibig_size(void)
+{
+    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
+        return 512;
+    else
+        return 128;
+}
+#endif
 /** Read MMU Primary Context Register.
  *
- * @return Current value of Primary Context Register.
+ * @return      Current value of Primary Context Register.
  */
 static inline uint64_t mmu_primary_context_read(void)
 {
 ,7 → 286,7
 /** Write MMU Primary Context Register.
  *
- * @param v New value of Primary Context Register.
+ * @param v     New value of Primary Context Register.
  */
 static inline void mmu_primary_context_write(uint64_t v)
 {
 ,7 → 296,7
 /** Read MMU Secondary Context Register.
  *
- * @return Current value of Secondary Context Register.
+ * @return      Current value of Secondary Context Register.
  */
 static inline uint64_t mmu_secondary_context_read(void)
 {
 ,7 → 305,7
 /** Write MMU Primary Context Register.
  *
- * @param v New value of Primary Context Register.
+ * @param v     New value of Primary Context Register.
  */
 static inline void mmu_secondary_context_write(uint64_t v)
 {
 ,15 → 313,18
     flush_pipeline();
 }
+#if defined (US)
 /** Read IMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
  *
- * @return Current value of specified IMMU TLB Data Access Register.
+ * @return      Current value of specified IMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t itlb_data_access_read(index_t entry)
 {
-    tlb_data_access_addr_t reg;
+    itlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,12 → 333,12
 /** Write IMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- * @param value Value to be written.
+ * @param entry     TLB Entry index.
+ * @param value     Value to be written.
  */
 static inline void itlb_data_access_write(index_t entry, uint64_t value)
 {
-    tlb_data_access_addr_t reg;
+    itlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,13 → 348,14
 /** Read DMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
  *
- * @return Current value of specified DMMU TLB Data Access Register.
+ * @return      Current value of specified DMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t dtlb_data_access_read(index_t entry)
 {
-    tlb_data_access_addr_t reg;
+    dtlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,12 → 364,12
 /** Write DMMU TLB Data Access Register.
  *
- * @param entry TLB Entry index.
- * @param value Value to be written.
+ * @param entry     TLB Entry index.
+ * @param value     Value to be written.
  */
 static inline void dtlb_data_access_write(index_t entry, uint64_t value)
 {
-    tlb_data_access_addr_t reg;
+    dtlb_data_access_addr_t reg;
     reg.value = 0;
     reg.tlb_entry = entry;
 ,13 → 379,13
 /** Read IMMU TLB Tag Read Register.
  *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
  *
- * @return Current value of specified IMMU TLB Tag Read Register.
+ * @return      Current value of specified IMMU TLB Tag Read Register.
  */
 static inline uint64_t itlb_tag_read_read(index_t entry)
 {
-    tlb_tag_read_addr_t tag;
+    itlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
 ,13 → 394,13
 /** Read DMMU TLB Tag Read Register.
  *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
  *
- * @return Current value of specified DMMU TLB Tag Read Register.
+ * @return      Current value of specified DMMU TLB Tag Read Register.
  */
 static inline uint64_t dtlb_tag_read_read(index_t entry)
 {
-    tlb_tag_read_addr_t tag;
+    dtlb_tag_read_addr_t tag;
     tag.value = 0;
     tag.tlb_entry = entry;
 ,9 → 407,120
     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
 }
+#elif defined (US3)
+/** Read IMMU TLB Data Access Register.
+ *
+ * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param entry     TLB Entry index.
+ *
+ * @return      Current value of specified IMMU TLB Data Access
+ *          Register.
+ */
+static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
+{
+    itlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
+}
+/** Write IMMU TLB Data Access Register.
+ * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param entry     TLB Entry index.
+ * @param value     Value to be written.
+ */
+static inline void itlb_data_access_write(int tlb, index_t entry,
+    uint64_t value)
+{
+    itlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
+    flush_pipeline();
+}
+/** Read DMMU TLB Data Access Register.
+ *
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
+ * @param entry     TLB Entry index.
+ *
+ * @return      Current value of specified DMMU TLB Data Access
+ *          Register.
+ */
+static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
+{
+    dtlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
+}
+/** Write DMMU TLB Data Access Register.
+ *
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
+ * @param entry     TLB Entry index.
+ * @param value     Value to be written.
+ */
+static inline void dtlb_data_access_write(int tlb, index_t entry,
+    uint64_t value)
+{
+    dtlb_data_access_addr_t reg;
+    reg.value = 0;
+    reg.tlb_number = tlb;
+    reg.local_tlb_entry = entry;
+    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
+    membar();
+}
+/** Read IMMU TLB Tag Read Register.
+ *
+ * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param entry     TLB Entry index.
+ *
+ * @return      Current value of specified IMMU TLB Tag Read Register.
+ */
+static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
+{
+    itlb_tag_read_addr_t tag;
+    tag.value = 0;
+    tag.tlb_number = tlb;
+    tag.local_tlb_entry = entry;
+    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
+}
+/** Read DMMU TLB Tag Read Register.
+ *
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
+ * @param entry     TLB Entry index.
+ *
+ * @return      Current value of specified DMMU TLB Tag Read Register.
+ */
+static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
+{
+    dtlb_tag_read_addr_t tag;
+    tag.value = 0;
+    tag.tlb_number = tlb;
+    tag.local_tlb_entry = entry;
+    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
+}
+#endif
 /** Write IMMU TLB Tag Access Register.
  *
- * @param v Value to be written.
+ * @param v     Value to be written.
  */
 static inline void itlb_tag_access_write(uint64_t v)
 {
 ,7 → 530,7
 /** Read IMMU TLB Tag Access Register.
  *
- * @return Current value of IMMU TLB Tag Access Register.
+ * @return      Current value of IMMU TLB Tag Access Register.
  */
 static inline uint64_t itlb_tag_access_read(void)
 {
 ,7 → 539,7
 /** Write DMMU TLB Tag Access Register.
  *
- * @param v Value to be written.
+ * @param v     Value to be written.
  */
 static inline void dtlb_tag_access_write(uint64_t v)
 {
 ,7 → 549,7
 /** Read DMMU TLB Tag Access Register.
  *
- * @return Current value of DMMU TLB Tag Access Register.
+ * @return      Current value of DMMU TLB Tag Access Register.
  */
 static inline uint64_t dtlb_tag_access_read(void)
 {
 ,7 → 559,7
 /** Write IMMU TLB Data in Register.
  *
- * @param v Value to be written.
+ * @param v     Value to be written.
  */
 static inline void itlb_data_in_write(uint64_t v)
 {
 ,7 → 569,7
 /** Write DMMU TLB Data in Register.
  *
- * @param v Value to be written.
+ * @param v     Value to be written.
  */
 static inline void dtlb_data_in_write(uint64_t v)
 {
 ,7 → 579,7
 /** Read ITLB Synchronous Fault Status Register.
  *
- * @return Current content of I-SFSR register.
+ * @return      Current content of I-SFSR register.
  */
 static inline uint64_t itlb_sfsr_read(void)
 {
 ,7 → 588,7
 /** Write ITLB Synchronous Fault Status Register.
  *
- * @param v New value of I-SFSR register.
+ * @param v     New value of I-SFSR register.
  */
 static inline void itlb_sfsr_write(uint64_t v)
 {
 ,7 → 598,7
 /** Read DTLB Synchronous Fault Status Register.
  *
- * @return Current content of D-SFSR register.
+ * @return      Current content of D-SFSR register.
  */
 static inline uint64_t dtlb_sfsr_read(void)
 {
 ,7 → 607,7
 /** Write DTLB Synchronous Fault Status Register.
  *
- * @param v New value of D-SFSR register.
+ * @param v     New value of D-SFSR register.
  */
 static inline void dtlb_sfsr_write(uint64_t v)
 {
 ,7 → 617,7
 /** Read DTLB Synchronous Fault Address Register.
  *
- * @return Current content of D-SFAR register.
+ * @return      Current content of D-SFAR register.
  */
 static inline uint64_t dtlb_sfar_read(void)
 {
 ,10 → 626,11
 /** Perform IMMU TLB Demap Operation.
  *
- * @param type Selects between context and page demap.
+ * @param type      Selects between context and page demap (and entire MMU
+ *          demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- *  demap.
- * @param page Address which is on the page to be demapped.
+ *          demap.
+ * @param page      Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 ,18 → 644,19
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
-                             * address within the
-                             * ASI */
+    /* da.value is the address within the ASI */
+    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
     flush_pipeline();
 }
 /** Perform DMMU TLB Demap Operation.
  *
- * @param type Selects between context and page demap.
+ * @param type      Selects between context and page demap (and entire MMU
+ *          demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- *   demap.
- * @param page Address which is on the page to be demapped.
+ *          demap.
+ * @param page      Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 ,17 → 670,17
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
-                             * address within the
-                             * ASI */
+    /* da.value is the address within the ASI */
+    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
     membar();
 }
-extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
-extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
-extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
+extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
+extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
+extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
-extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
+extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 extern void dump_sfsr_and_sfar(void);

 /branches/network/kernel/arch/sparc64/include/mm/cache.h
 ,15 → 38,6
 #include <mm/page.h>
 #include <mm/frame.h>
-#define dcache_flush_page(p) \
-    dcache_flush_color(PAGE_COLOR((p)))
-#define dcache_flush_frame(p, f) \
-    dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f)));
-extern void dcache_flush(void);
-extern void dcache_flush_color(int c);
-extern void dcache_flush_tag(int c, pfn_t tag);
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/mm/tsb.h
 ,6 → 107,55
     asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
 }
+#if defined (US3)
+/** Write DTSB Primary Extension register.
+ *
+ * @param v New content of the DTSB Primary Extension register.
+ */
+static inline void dtsb_primary_extension_write(uint64_t v)
+{
+    asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
+}
+/** Write DTSB Secondary Extension register.
+ *
+ * @param v New content of the DTSB Secondary Extension register.
+ */
+static inline void dtsb_secondary_extension_write(uint64_t v)
+{
+    asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
+}
+/** Write DTSB Nucleus Extension register.
+ *
+ * @param v New content of the DTSB Nucleus Extension register.
+ */
+static inline void dtsb_nucleus_extension_write(uint64_t v)
+{
+    asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
+}
+/** Write ITSB Primary Extension register.
+ *
+ * @param v New content of the ITSB Primary Extension register.
+ */
+static inline void itsb_primary_extension_write(uint64_t v)
+{
+    asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
+}
+/** Write ITSB Nucleus Extension register.
+ *
+ * @param v New content of the ITSB Nucleus Extension register.
+ */
+static inline void itsb_nucleus_extension_write(uint64_t v)
+{
+    asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
+}
+#endif
 /* Forward declarations. */
 struct as;
 struct pte;

 /branches/network/kernel/arch/sparc64/include/register.h
 ,23 → 117,6
 };
 typedef union fprs_reg fprs_reg_t;
-/** UPA_CONFIG register.
- *
- * Note that format of this register differs significantly from
- * processor version to version. The format defined here
- * is the common subset for all supported processor versions.
- */
-union upa_config {
-    uint64_t value;
-    struct {
-        uint64_t : 34;
-        unsigned pcon : 8;  /**< Processor configuration. */
-        unsigned mid : 5;   /**< Module (processor) ID register. */
-        unsigned pcap : 17; /**< Processor capabilities. */
-    } __attribute__ ((packed));
-};
-typedef union upa_config upa_config_t;
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/barrier.h
 ,6 → 82,8
     asm volatile ("membar #Sync\n");
 }
+#if defined (US)
 #define smc_coherence(a)    \
 {               \
     write_barrier();    \
 ,6 → 99,22
         flush((void *)(a) + i);         \
 }
+#elif defined (US3)
+#define smc_coherence(a)    \
+{               \
+    write_barrier();    \
+    flush_pipeline();   \
+}
+#define smc_coherence_block(a, l)   \
+{                   \
+    write_barrier();        \
+    flush_pipeline();       \
+}
+#endif  /* defined(US3) */
 #endif
 /** @}

 /branches/network/kernel/arch/sparc64/include/cpu.h
 ,15 → 35,6
 #ifndef KERN_sparc64_CPU_H_
 #define KERN_sparc64_CPU_H_
-#include <arch/types.h>
-#include <typedefs.h>
-#include <arch/register.h>
-#include <arch/asm.h>
-#ifdef CONFIG_SMP
-#include <arch/mm/cache.h>
-#endif
 #define MANUF_FUJITSU       0x04
 #define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
 #define MANUF_SUN       0x3e
 ,14 → 43,29
 #define IMPL_ULTRASPARCII   0x11
 #define IMPL_ULTRASPARCII_I 0x12
 #define IMPL_ULTRASPARCII_E 0x13
-#define IMPL_ULTRASPARCIII  0x15
+#define IMPL_ULTRASPARCIII  0x14
+#define IMPL_ULTRASPARCIII_PLUS 0x15
+#define IMPL_ULTRASPARCIII_I    0x16
+#define IMPL_ULTRASPARCIV   0x18
 #define IMPL_ULTRASPARCIV_PLUS  0x19
 #define IMPL_SPARC64V       0x5
+#ifndef __ASM__
+#include <arch/types.h>
+#include <typedefs.h>
+#include <arch/register.h>
+#include <arch/regdef.h>
+#include <arch/asm.h>
+#ifdef CONFIG_SMP
+#include <arch/mm/cache.h>
+#endif
 typedef struct {
     uint32_t mid;           /**< Processor ID as read from
-                         UPA_CONFIG. */
+                         UPA_CONFIG/FIREPLANE_CONFIG. */
     ver_reg_t ver;
     uint32_t clock_frequency;   /**< Processor frequency in Hz. */
     uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
 ,8 → 72,28
                          generated when the TICK register
                          matches this value. */
 } cpu_arch_t;
+/**
+ * Reads the module ID (agent ID/CPUID) of the current CPU.
+ */
+static inline uint32_t read_mid(void)
+{
+    uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
+    icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
+#if defined (US)
+    return icbus_config & 0x1f;
+#elif defined (US3)
+    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
+        return icbus_config & 0x1f;
+    else
+        return icbus_config & 0x3ff;
 #endif
+}
+#endif
+#endif
 /** @}
  */

 /branches/network/kernel/arch/sparc64/include/drivers/sgcn.h
 ,0 → 1,127
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_sparc64_SGCN_H_
+#define KERN_sparc64_SGCN_H_
+#include <arch/types.h>
+#include <console/chardev.h>
+/* number of bytes in the TOC magic, including the terminating '\0' */
+#define TOC_MAGIC_BYTES     8
+/* number of bytes in the TOC key, including the terminating '\0' */
+#define TOC_KEY_SIZE        8
+/* maximum number of entries in the SRAM table of contents */
+#define MAX_TOC_ENTRIES     32
+/* number of bytes in the SGCN buffer magic, including the terminating '\0' */
+#define SGCN_MAGIC_BYTES    4
+/**
+ * Entry in the SRAM table of contents. Describes one segment of the SRAM
+ * which serves a particular purpose (e.g. OBP serial console, Solaris serial
+ * console, Solaris mailbox,...).
+ */
+typedef struct {
+    /** key (e.g. "OBPCONS", "SOLCONS", "SOLMBOX",...) */
+    char key[TOC_KEY_SIZE];
+    /** size of the segment in bytes */
+    uint32_t size;
+    /** offset of the segment within SRAM */
+    uint32_t offset;
+} __attribute ((packed)) toc_entry_t;
+/**
+ * SRAM table of contents. Describes all segments within the SRAM.
+ */
+typedef struct {
+    /** hard-wired to "TOCSRAM" */
+    char magic[TOC_MAGIC_BYTES];
+    /** we don't need this */
+    char unused[8];
+    /** TOC entries */
+    toc_entry_t keys[MAX_TOC_ENTRIES];
+} __attribute__ ((packed)) iosram_toc_t;
+/**
+ * SGCN buffer header. It is placed at the very beginning of the SGCN
+ * buffer.
+ */
+typedef struct {
+    /** hard-wired to "CON" */
+    char magic[SGCN_MAGIC_BYTES];
+    /** we don't need this */
+    char unused[8];
+    /** offset within the SGCN buffer of the input buffer start */
+    uint32_t in_begin;
+    /** offset within the SGCN buffer of the input buffer end */
+    uint32_t in_end;
+    /** offset within the SGCN buffer of the input buffer read pointer */
+    uint32_t in_rdptr;
+    /** offset within the SGCN buffer of the input buffer write pointer */
+    uint32_t in_wrptr;
+    /** offset within the SGCN buffer of the output buffer start */
+    uint32_t out_begin;
+    /** offset within the SGCN buffer of the output buffer end */
+    uint32_t out_end;
+    /** offset within the SGCN buffer of the output buffer read pointer */
+    uint32_t out_rdptr;
+    /** offset within the SGCN buffer of the output buffer write pointer */
+    uint32_t out_wrptr;
+} __attribute__ ((packed)) sgcn_buffer_header_t;
+void sgcn_grab(void);
+void sgcn_release(void);
+indev_t *sgcnin_init(void);
+void sgcnout_init(void);
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/sparc64/include/drivers/pci.h
 ,8 → 51,8
 };
 struct pci_operations {
-    void (* enable_interrupt)(pci_t *pci, int inr);
-    void (* clear_interrupt)(pci_t *pci, int inr);
+    void (* enable_interrupt)(pci_t *, int);
+    void (* clear_interrupt)(pci_t *, int);
 };
 struct pci {
 ,9 → 61,9
     volatile uint64_t *reg;     /**< Registers including interrupt registers. */
 };
-extern pci_t *pci_init(ofw_tree_node_t *node);
-extern void pci_enable_interrupt(pci_t *pci, int inr);
-extern void pci_clear_interrupt(pci_t *pci, int inr);
+extern pci_t *pci_init(ofw_tree_node_t *);
+extern void pci_enable_interrupt(pci_t *, int);
+extern void pci_clear_interrupt(void *, int);
 #endif

 /branches/network/kernel/arch/sparc64/include/drivers/fhc.h
 ,9 → 44,9
 extern fhc_t *central_fhc;
-extern fhc_t *fhc_init(ofw_tree_node_t *node);
-extern void fhc_enable_interrupt(fhc_t *fhc, int inr);
-extern void fhc_clear_interrupt(fhc_t *fhc, int inr);
+extern fhc_t *fhc_init(ofw_tree_node_t *);
+extern void fhc_enable_interrupt(fhc_t *, int);
+extern void fhc_clear_interrupt(void *, int);
 #endif

 /branches/network/kernel/arch/sparc64/include/drivers/kbd.h
 ,7 → 41,8
 typedef enum {
     KBD_UNKNOWN,
     KBD_Z8530,
-    KBD_NS16550
+    KBD_NS16550,
+    KBD_SGCN
 } kbd_type_t;
 extern kbd_type_t kbd_type;

 /branches/network/kernel/arch/sparc64/include/drivers/scr.h
 ,12 → 42,14
     SCR_UNKNOWN,
     SCR_ATYFB,
     SCR_FFB,
-    SCR_CGSIX
+    SCR_CGSIX,
+    SCR_XVR
 } scr_type_t;
 extern scr_type_t scr_type;
 extern void scr_init(ofw_tree_node_t *node);
+extern void scr_redraw(void);
 #endif

 /branches/network/kernel/arch/sparc64/include/cpu_family.h
 ,0 → 1,83
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_sparc64_CPU_FAMILY_H_
+#define KERN_sparc64_CPU_FAMILY_H_
+#include <arch.h>
+#include <cpu.h>
+#include <arch/register.h>
+#include <arch/asm.h>
+/**
+ * Find the processor (sub)family.
+ *
+ * @return  true iff the CPU belongs to the US family
+ */
+static inline bool is_us(void)
+{
+    int impl = ((ver_reg_t) ver_read()).impl;
+    return (impl == IMPL_ULTRASPARCI) || (impl == IMPL_ULTRASPARCII) ||
+           (impl == IMPL_ULTRASPARCII_I) ||  (impl == IMPL_ULTRASPARCII_E);
+}
+/**
+ * Find the processor (sub)family.
+ *
+ * @return  true iff the CPU belongs to the US-III subfamily
+ */
+static inline bool is_us_iii(void)
+{
+    int impl = ((ver_reg_t) ver_read()).impl;
+    return (impl == IMPL_ULTRASPARCIII) ||
+           (impl == IMPL_ULTRASPARCIII_PLUS) ||
+           (impl == IMPL_ULTRASPARCIII_I);
+}
+/**
+ * Find the processor (sub)family.
+ *
+ * @return  true iff the CPU belongs to the US-IV subfamily
+ */
+static inline bool is_us_iv(void)
+{
+    int impl = ((ver_reg_t) ver_read()).impl;
+    return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS);
+}
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/sparc64/Makefile.inc
 ,10 → 29,6
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf64-sparc
 BFD_ARCH = sparc
 BFD = binary
 ,80 → 42,55
 DEFS += -D__64_BITS__
-## Own configuration directives
-#
+ifeq ($(PROCESSOR),us)
+    DEFS += -DUS
+endif
-## Compile with page hash table support.
-#
+ifeq ($(PROCESSOR),us3)
+    DEFS += -DUS3
+endif
-CONFIG_PAGE_HT = y
-DEFS += -DCONFIG_PAGE_HT
+ARCH_SOURCES = \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/panic.S \
+    arch/$(KARCH)/src/console.c \
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/fpu_context.c \
+    arch/$(KARCH)/src/dummy.s \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/cache.S \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/sparc64.c \
+    arch/$(KARCH)/src/start.S \
+    arch/$(KARCH)/src/proc/scheduler.c \
+    arch/$(KARCH)/src/proc/thread.c \
+    arch/$(KARCH)/src/trap/mmu.S \
+    arch/$(KARCH)/src/trap/trap_table.S \
+    arch/$(KARCH)/src/trap/trap.c \
+    arch/$(KARCH)/src/trap/exception.c \
+    arch/$(KARCH)/src/trap/interrupt.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/drivers/tick.c \
+    arch/$(KARCH)/src/drivers/kbd.c \
+    arch/$(KARCH)/src/drivers/sgcn.c \
+    arch/$(KARCH)/src/drivers/pci.c \
+    arch/$(KARCH)/src/drivers/fhc.c
-## Compile with support for address space identifiers.
-#
-CONFIG_ASID = y
-CONFIG_ASID_FIFO = y
-## Compile with support for framebuffer.
-#
-CONFIG_FB = y
-## Compile with support for Sun keyboard.
-#
-CONFIG_SUN_KBD = y
-## Compile with support for OpenFirmware device tree.
-#
-CONFIG_OFW_TREE = y
-ifeq ($(CONFIG_SMP),y)
-    DEFS += -DCONFIG_SMP
+ifeq ($(CONFIG_FB),y)
+    ARCH_SOURCES += \
+        arch/$(KARCH)/src/drivers/scr.c
 endif
-ARCH_SOURCES = \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/panic.S \
-    arch/$(ARCH)/src/console.c \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/fpu_context.c \
-    arch/$(ARCH)/src/dummy.s \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/cache.S \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/sparc64.c \
-    arch/$(ARCH)/src/start.S \
-    arch/$(ARCH)/src/proc/scheduler.c \
-    arch/$(ARCH)/src/proc/thread.c \
-    arch/$(ARCH)/src/trap/mmu.S \
-    arch/$(ARCH)/src/trap/trap_table.S \
-    arch/$(ARCH)/src/trap/trap.c \
-    arch/$(ARCH)/src/trap/exception.c \
-    arch/$(ARCH)/src/trap/interrupt.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/tick.c \
-    arch/$(ARCH)/src/drivers/kbd.c \
-    arch/$(ARCH)/src/drivers/scr.c \
-    arch/$(ARCH)/src/drivers/pci.c
 ifeq ($(CONFIG_SMP),y)
-ARCH_SOURCES += \
-    arch/$(ARCH)/src/smp/ipi.c \
-    arch/$(ARCH)/src/smp/smp.c
+    ARCH_SOURCES += \
+        arch/$(KARCH)/src/smp/ipi.c \
+        arch/$(KARCH)/src/smp/smp.c
 endif
 ifeq ($(CONFIG_TSB),y)
-ARCH_SOURCES += \
-    arch/$(ARCH)/src/mm/tsb.c
+    ARCH_SOURCES += \
+        arch/$(KARCH)/src/mm/tsb.c
 endif
-ifdef CONFIG_Z8530
-ARCH_SOURCES += \
-    arch/$(ARCH)/src/drivers/fhc.c
-endif

 /branches/network/kernel/arch/sparc64/src/smp/smp.c
 ,6 → 35,7
 #include <smp/smp.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <cpu.h>
+#include <arch/cpu_family.h>
 #include <arch/cpu.h>
 #include <arch.h>
 #include <config.h>
 ,6 → 44,7
 #include <synch/synch.h>
 #include <synch/waitq.h>
 #include <print.h>
+#include <arch/cpu_node.h>
 /**
  * This global variable is used to pick-up application processors
 ,15 → 63,55
     ofw_tree_node_t *node;
     count_t cnt = 0;
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    while (node) {
-        cnt++;
-        node = ofw_tree_find_peer_by_device_type(node, "cpu");
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        while (node) {
+            cnt++;
+            node = ofw_tree_find_peer_by_device_type(node, "cpu");
+        }
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            cnt += 2;
+            node = ofw_tree_find_peer_by_name(node, "cmp");
+        }
     }
     config.cpu_count = max(1, cnt);
 }
+/**
+ * Wakes up the CPU which is represented by the "node" OFW tree node.
+ * If "node" represents the current CPU, calling the function has
+ * no effect.
+ */
+static void wakeup_cpu(ofw_tree_node_t *node)
+{
+    uint32_t mid;
+    ofw_tree_property_t *prop;
+    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
+    prop = ofw_tree_getprop(node, "upa-portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "cpuid");
+    if (!prop || prop->value == NULL)
+        return;
+    mid = *((uint32_t *) prop->value);
+    if (CPU->arch.mid == mid)
+        return;
+    waking_up_mid = mid;
+    if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) ==
+        ESYNCH_TIMEOUT)
+        printf("%s: waiting for processor (mid = %" PRIu32
+            ") timed out\n", __func__, mid);
+}
 /** Wake application processors up. */
 void kmp(void *arg)
 {
 ,31 → 118,18
     ofw_tree_node_t *node;
     int i;
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    for (i = 0; node; node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++) {
-        uint32_t mid;
-        ofw_tree_property_t *prop;
-        prop = ofw_tree_getprop(node, "upa-portid");
-        if (!prop || !prop->value)
-            continue;
-        mid = *((uint32_t *) prop->value);
-        if (CPU->arch.mid == mid) {
-            /*
-             * Skip the current CPU.
-             */
-            continue;
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        for (i = 0; node;
+                     node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++)
+            wakeup_cpu(node);
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            wakeup_cpu(ofw_tree_find_child(node, "cpu@0"));
+            wakeup_cpu(ofw_tree_find_child(node, "cpu@1"));
+            node = ofw_tree_find_peer_by_name(node, "cmp");
         }
-        /*
-         * Processor with ID == mid can proceed with its initialization.
-         */
-        waking_up_mid = mid;
-        if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT)
-            printf("%s: waiting for processor (mid = %" PRIu32 ") timed out\n",
-                __func__, mid);
     }
 }

 /branches/network/kernel/arch/sparc64/src/smp/ipi.c
 ,6 → 46,33
 #include <time/delay.h>
 #include <panic.h>
+/** Set the contents of the outgoing interrupt vector data.
+ *
+ * The first data item (data 0) will be set to the value of func, the
+ * rest of the vector will contain zeros.
+ *
+ * This is a helper function used from within the cross_call function.
+ *
+ * @param func value the first data item of the vector will be set to
+ */
+static inline void set_intr_w_data(void (* func)(void))
+{
+#if defined (US)
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
+#elif defined (US3)
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
+#endif
+}
 /** Invoke function on another processor.
  *
  * Currently, only functions without arguments are supported.
 ,16 → 98,15
     status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
     if (status & INTR_DISPATCH_STATUS_BUSY)
-        panic("Interrupt Dispatch Status busy bit set\n");
+        panic("Interrupt Dispatch Status busy bit set.");
+    ASSERT(!(pstate_read() & PSTATE_IE_BIT));
     do {
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0,
-            (uintptr_t) func);
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
-        asi_u64_write(ASI_UDB_INTR_W,
+        set_intr_w_data(func);
+        asi_u64_write(ASI_INTR_W,
             (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
-            ASI_UDB_INTR_W_DISPATCH, 0);
+            VA_INTR_W_DISPATCH, 0);
         membar();
 ,7 → 151,7
         func = tlb_shootdown_ipi_recv;
         break;
     default:
-        panic("Unknown IPI (%d).\n", ipi);
+        panic("Unknown IPI (%d).", ipi);
         break;
     }

 /branches/network/kernel/arch/sparc64/src/ddi/ddi.c
 ,7 → 41,7
  * Interrupts are disabled and task is locked.
  *
  * @param task Task.
- * @param ioaddr Startign I/O space address.
+ * @param ioaddr Starting I/O space address.
  * @param size Size of the enabled I/O range.
  *
  * @return 0 on success or an error code from errno.h.

 /branches/network/kernel/arch/sparc64/src/console.c
 ,14 → 37,8
 #include <arch/drivers/scr.h>
 #include <arch/drivers/kbd.h>
-#ifdef CONFIG_Z8530
-#include <genarch/kbd/z8530.h>
-#endif
-#ifdef CONFIG_NS16550
-#include <genarch/kbd/ns16550.h>
-#endif
+#include <arch/drivers/sgcn.h>
+#include <genarch/srln/srln.h>
 #include <console/chardev.h>
 #include <console/console.h>
 #include <arch/asm.h>
 ,89 → 48,98
 #include <genarch/ofw/ofw_tree.h>
 #include <arch.h>
 #include <panic.h>
+#include <string.h>
 #include <print.h>
 #define KEYBOARD_POLL_PAUSE 50000   /* 50ms */
-/** Initialize kernel console to use framebuffer and keyboard directly. */
-void standalone_sparc64_console_init(void)
+/**
+ * Initialize kernel console to use framebuffer and keyboard directly.
+ * Called on UltraSPARC machines with standard keyboard and framebuffer.
+ *
+ * @param aliases   the "/aliases" OBP node
+ */
+static void standard_console_init(ofw_tree_node_t *aliases)
 {
-    stdin = NULL;
-    ofw_tree_node_t *aliases;
-    ofw_tree_property_t *prop;
-    ofw_tree_node_t *screen;
-    ofw_tree_node_t *keyboard;
+#ifdef CONFIG_FB
+    ofw_tree_property_t *prop_scr = ofw_tree_getprop(aliases, "screen");
+    if (!prop_scr)
+        panic("Cannot find property 'screen'.");
+    if (!prop_scr->value)
+        panic("Cannot find screen alias.");
+    ofw_tree_node_t *screen = ofw_tree_lookup(prop_scr->value);
+    if (!screen)
+        panic("Cannot find %s.", prop_scr->value);
-    aliases = ofw_tree_lookup("/aliases");
-    if (!aliases)
-        panic("Can't find /aliases.\n");
-    prop = ofw_tree_getprop(aliases, "screen");
-    if (!prop)
-        panic("Can't find property \"screen\".\n");
-    if (!prop->value)
-        panic("Can't find screen alias.\n");
-    screen = ofw_tree_lookup(prop->value);
-    if (!screen)
-        panic("Can't find %s\n", prop->value);
     scr_init(screen);
+#endif
-    prop = ofw_tree_getprop(aliases, "keyboard");
-    if (!prop)
-        panic("Can't find property \"keyboard\".\n");
-    if (!prop->value)
-        panic("Can't find keyboard alias.\n");
-    keyboard = ofw_tree_lookup(prop->value);
+#ifdef CONFIG_SUN_KBD
+    ofw_tree_property_t *prop_kbd = ofw_tree_getprop(aliases, "keyboard");
+    if (!prop_kbd)
+        panic("Cannot find property 'keyboard'.");
+    if (!prop_kbd->value)
+        panic("Cannot find keyboard alias.");
+    ofw_tree_node_t *keyboard = ofw_tree_lookup(prop_kbd->value);
     if (!keyboard)
-        panic("Can't find %s\n", prop->value);
+        panic("Cannot find %s.", prop_kbd->value);
     kbd_init(keyboard);
+#endif
 }
-/** Kernel thread for polling keyboard.
- *
- * @param arg Ignored.
- */
-void kkbdpoll(void *arg)
+/** Initilize I/O on the Serengeti machine. */
+static void serengeti_init(void)
 {
-    thread_detach(THREAD);
-#ifdef CONFIG_Z8530
-    if (kbd_type == KBD_Z8530) {
-        /*
-         * The z8530 driver is interrupt-driven.
-         */
-        return;
-    }
+#ifdef CONFIG_SGCN_KBD
+    indev_t *kbrdin;
+    kbrdin = sgcnin_init();
+    if (kbrdin)
+        srlnin_init(kbrdin);
 #endif
+#ifdef CONFIG_SGCN_PRN
+    sgcnout_init();
+#endif
+}
-    while (1) {
-#ifdef CONFIG_NS16550
-        if (kbd_type == KBD_NS16550)
-            ns16550_poll();
-#endif
-        thread_usleep(KEYBOARD_POLL_PAUSE);
+/**
+ * Initialize input/output. Auto-detects the type of machine
+ * and calls the appropriate I/O init routine.
+ */
+void standalone_sparc64_console_init(void)
+{
+    ofw_tree_node_t *aliases;
+    ofw_tree_property_t *prop;
+    aliases = ofw_tree_lookup("/aliases");
+    if (!aliases)
+        panic("Cannot find '/aliases'.");
+    /* "def-cn" = "default console" */
+    prop = ofw_tree_getprop(aliases, "def-cn");
+    if ((!prop) || (!prop->value) || (strcmp(prop->value, "/sgcn") != 0)) {
+        standard_console_init(aliases);
+    } else {
+        serengeti_init();
     }
 }
 /** Acquire console back for kernel
  *
  */
 void arch_grab_console(void)
 {
+#ifdef CONFIG_FB
+    scr_redraw();
+#endif
     switch (kbd_type) {
-#ifdef CONFIG_Z8530
-    case KBD_Z8530:
-        z8530_grab();
+#ifdef CONFIG_SGCN
+    case KBD_SGCN:
+        sgcn_grab();
         break;
 #endif
-#ifdef CONFIG_NS16550
-    case KBD_NS16550:
-        ns16550_grab();
-        break;
-#endif
     default:
         break;
     }
 ,16 → 151,11
 void arch_release_console(void)
 {
     switch (kbd_type) {
-#ifdef CONFIG_Z8530
-    case KBD_Z8530:
-        z8530_release();
+#ifdef CONFIG_SGCN
+    case KBD_SGCN:
+        sgcn_release();
         break;
 #endif
-#ifdef CONFIG_NS16550
-    case KBD_NS16550:
-        ns16550_release();
-        break;
-#endif
     default:
         break;
     }

 /branches/network/kernel/arch/sparc64/src/proc/thread.c
 ,9 → 34,8
 #include <proc/thread.h>
 #include <arch/proc/thread.h>
-#include <mm/frame.h>
-#include <mm/page.h>
-#include <arch/mm/page.h>
+#include <mm/slab.h>
+#include <arch/trap/regwin.h>
 #include <align.h>
 void thr_constructor_arch(thread_t *t)
 ,12 → 49,12
 void thr_destructor_arch(thread_t *t)
 {
     if (t->arch.uspace_window_buffer) {
+        uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
         /*
          * Mind the possible alignment of the userspace window buffer
          * belonging to a killed thread.
          */
-        frame_free(KA2PA(ALIGN_DOWN((uintptr_t)
-            t->arch.uspace_window_buffer, PAGE_SIZE)));
+        free((uint8_t *) ALIGN_DOWN(uw_buf, UWB_ALIGNMENT));
     }
 }
 ,7 → 66,7
          * The thread needs userspace window buffer and the object
          * returned from the slab allocator doesn't have any.
          */
-        t->arch.uspace_window_buffer = frame_alloc(ONE_FRAME, FRAME_KA);
+        t->arch.uspace_window_buffer = malloc(UWB_ASIZE, 0);
     } else {
         uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
 ,7 → 75,7
          * belonging to a killed thread.
          */
         t->arch.uspace_window_buffer = (uint8_t *) ALIGN_DOWN(uw_buf,
-            PAGE_SIZE);
+            UWB_ASIZE);
     }
 }

 /branches/network/kernel/arch/sparc64/src/sparc64.c
 ,7 → 37,6
 #include <config.h>
 #include <arch/trap/trap.h>
 #include <arch/console.h>
-#include <proc/thread.h>
 #include <console/console.h>
 #include <arch/boot/boot.h>
 #include <arch/arch.h>
 ,10 → 46,11
 #include <genarch/ofw/ofw_tree.h>
 #include <userspace.h>
 #include <ddi/irq.h>
+#include <string.h>
 bootinfo_t bootinfo;
-/** Perform sparc64 specific initialization before main_bsp() is called. */
+/** Perform sparc64-specific initialization before main_bsp() is called. */
 void arch_pre_main(void)
 {
     /* Copy init task info. */
 ,6 → 61,8
     for (i = 0; i < bootinfo.taskmap.count; i++) {
         init.tasks[i].addr = (uintptr_t) bootinfo.taskmap.tasks[i].addr;
         init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
+        strncpy(init.tasks[i].name, bootinfo.taskmap.tasks[i].name,
+            CONFIG_TASK_NAME_BUFLEN);
     }
     /* Copy boot allocations info. */
 ,8 → 88,6
          * But we only create 128 buckets.
          */
         irq_init(1 << 11, 128);
-        standalone_sparc64_console_init();
     }
 }
 ,18 → 101,7
 void arch_post_smp_init(void)
 {
-    static thread_t *t = NULL;
-    if (!t) {
-        /*
-             * Create thread that polls keyboard.
-             */
-        t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
-        if (!t)
-            panic("cannot create kkbdpoll\n");
-        thread_ready(t);
-    }
+    standalone_sparc64_console_init();
 }
 /** Calibrate delay loop.
 ,5 → 150,19
     while (1);
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/trap/exception.c
 ,62 → 40,67
 #include <arch/asm.h>
 #include <arch/register.h>
 #include <debug.h>
+#include <print.h>
 #include <symtab.h>
-#include <print.h>
 void dump_istate(istate_t *istate)
 {
+    char *tpcs, *tnpcs;
+    tpcs = symtab_fmt_name_lookup(istate->tpc);
+    tnpcs = symtab_fmt_name_lookup(istate->tnpc);
     printf("TSTATE=%#" PRIx64 "\n", istate->tstate);
-    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, get_symtab_entry(istate->tpc));
-    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, get_symtab_entry(istate->tnpc));
+    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, tpcs);
+    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, tnpcs);
 }
 /** Handle instruction_access_exception. (0x8) */
 void instruction_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle instruction_access_error. (0xa) */
 void instruction_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle illegal_instruction. (0x10) */
 void illegal_instruction(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle privileged_opcode. (0x11) */
 void privileged_opcode(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle unimplemented_LDD. (0x12) */
 void unimplemented_LDD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle unimplemented_STD. (0x13) */
 void unimplemented_STD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle fp_disabled. (0x20) */
 ,9 → 118,9
 #ifdef CONFIG_FPU_LAZY
     scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 #endif
 }
 ,98 → 127,98
 /** Handle fp_exception_ieee_754. (0x21) */
 void fp_exception_ieee_754(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle fp_exception_other. (0x22) */
 void fp_exception_other(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle tag_overflow. (0x23) */
 void tag_overflow(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle division_by_zero. (0x28) */
 void division_by_zero(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle data_access_exception. (0x30) */
 void data_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
     dump_sfsr_and_sfar();
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle data_access_error. (0x32) */
 void data_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle mem_address_not_aligned. (0x34) */
 void mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle LDDF_mem_address_not_aligned. (0x35) */
 void LDDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle STDF_mem_address_not_aligned. (0x36) */
 void STDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle privileged_action. (0x37) */
 void privileged_action(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle LDQF_mem_address_not_aligned. (0x38) */
 void LDQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle STQF_mem_address_not_aligned. (0x39) */
 void STQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/trap/interrupt.c
 ,11 → 67,19
  */
 void interrupt(int n, istate_t *istate)
 {
+    uint64_t status;
     uint64_t intrcv;
     uint64_t data0;
+    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
+    if (status & (!INTR_DISPATCH_STATUS_BUSY))
+        panic("Interrupt Dispatch Status busy bit not set.");
     intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
-    data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#if defined (US)
+    data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#elif defined (US3)
+    data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
+#endif
     irq_t *irq = irq_dispatch_and_lock(data0);
     if (irq) {
 ,7 → 86,13
         /*
          * The IRQ handler was found.
          */
-        irq->handler(irq, irq->arg);
+        irq->handler(irq);
+        /*
+         * See if there is a clear-interrupt-routine and call it.
+         */
+        if (irq->cir) {
+            irq->cir(irq->cir_arg, irq->inr);
+        }
         spinlock_unlock(&irq->lock);
     } else if (data0 > config.base) {
         /*
 ,7 → 112,7
          */
 #ifdef CONFIG_DEBUG
         printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64
-            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
+            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
 #endif
     }

 /branches/network/kernel/arch/sparc64/src/trap/trap_table.S
 ,198 → 329,22
 fill_1_normal_tl0:
     FILL_NORMAL_HANDLER_USERSPACE
-/* TT = 0x100, TL = 0, trap_instruction_0 */
-.org trap_table + TT_TRAP_INSTRUCTION(0)*ENTRY_SIZE
-.global trap_instruction_0_tl0
-trap_instruction_0_tl0:
-    TRAP_INSTRUCTION 0
+/* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */
+.irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\
+, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\
+, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\
+, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\
+, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\
+, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\
+, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\
+.org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE
+.global trap_instruction_\cur\()_tl0
+trap_instruction_\cur\()_tl0:
+    ba trap_instruction_handler
+    mov \cur, %g2
+.endr
-/* TT = 0x101, TL = 0, trap_instruction_1 */
-.org trap_table + TT_TRAP_INSTRUCTION(1)*ENTRY_SIZE
-.global trap_instruction_1_tl0
-trap_instruction_1_tl0:
-    TRAP_INSTRUCTION 1
-/* TT = 0x102, TL = 0, trap_instruction_2 */
-.org trap_table + TT_TRAP_INSTRUCTION(2)*ENTRY_SIZE
-.global trap_instruction_2_tl0
-trap_instruction_2_tl0:
-    TRAP_INSTRUCTION 2
-/* TT = 0x103, TL = 0, trap_instruction_3 */
-.org trap_table + TT_TRAP_INSTRUCTION(3)*ENTRY_SIZE
-.global trap_instruction_3_tl0
-trap_instruction_3_tl0:
-    TRAP_INSTRUCTION 3
-/* TT = 0x104, TL = 0, trap_instruction_4 */
-.org trap_table + TT_TRAP_INSTRUCTION(4)*ENTRY_SIZE
-.global trap_instruction_4_tl0
-trap_instruction_4_tl0:
-    TRAP_INSTRUCTION 4
-/* TT = 0x105, TL = 0, trap_instruction_5 */
-.org trap_table + TT_TRAP_INSTRUCTION(5)*ENTRY_SIZE
-.global trap_instruction_5_tl0
-trap_instruction_5_tl0:
-    TRAP_INSTRUCTION 5
-/* TT = 0x106, TL = 0, trap_instruction_6 */
-.org trap_table + TT_TRAP_INSTRUCTION(6)*ENTRY_SIZE
-.global trap_instruction_6_tl0
-trap_instruction_6_tl0:
-    TRAP_INSTRUCTION 6
-/* TT = 0x107, TL = 0, trap_instruction_7 */
-.org trap_table + TT_TRAP_INSTRUCTION(7)*ENTRY_SIZE
-.global trap_instruction_7_tl0
-trap_instruction_7_tl0:
-    TRAP_INSTRUCTION 7
-/* TT = 0x108, TL = 0, trap_instruction_8 */
-.org trap_table + TT_TRAP_INSTRUCTION(8)*ENTRY_SIZE
-.global trap_instruction_8_tl0
-trap_instruction_8_tl0:
-    TRAP_INSTRUCTION 8
-/* TT = 0x109, TL = 0, trap_instruction_9 */
-.org trap_table + TT_TRAP_INSTRUCTION(9)*ENTRY_SIZE
-.global trap_instruction_9_tl0
-trap_instruction_9_tl0:
-    TRAP_INSTRUCTION 9
-/* TT = 0x10a, TL = 0, trap_instruction_10 */
-.org trap_table + TT_TRAP_INSTRUCTION(10)*ENTRY_SIZE
-.global trap_instruction_10_tl0
-trap_instruction_10_tl0:
-    TRAP_INSTRUCTION 10
-/* TT = 0x10b, TL = 0, trap_instruction_11 */
-.org trap_table + TT_TRAP_INSTRUCTION(11)*ENTRY_SIZE
-.global trap_instruction_11_tl0
-trap_instruction_11_tl0:
-    TRAP_INSTRUCTION 11
-/* TT = 0x10c, TL = 0, trap_instruction_12 */
-.org trap_table + TT_TRAP_INSTRUCTION(12)*ENTRY_SIZE
-.global trap_instruction_12_tl0
-trap_instruction_12_tl0:
-    TRAP_INSTRUCTION 12
-/* TT = 0x10d, TL = 0, trap_instruction_13 */
-.org trap_table + TT_TRAP_INSTRUCTION(13)*ENTRY_SIZE
-.global trap_instruction_13_tl0
-trap_instruction_13_tl0:
-    TRAP_INSTRUCTION 13
-/* TT = 0x10e, TL = 0, trap_instruction_14 */
-.org trap_table + TT_TRAP_INSTRUCTION(14)*ENTRY_SIZE
-.global trap_instruction_14_tl0
-trap_instruction_14_tl0:
-    TRAP_INSTRUCTION 14
-/* TT = 0x10f, TL = 0, trap_instruction_15 */
-.org trap_table + TT_TRAP_INSTRUCTION(15)*ENTRY_SIZE
-.global trap_instruction_15_tl0
-trap_instruction_15_tl0:
-    TRAP_INSTRUCTION 15
-/* TT = 0x110, TL = 0, trap_instruction_16 */
-.org trap_table + TT_TRAP_INSTRUCTION(16)*ENTRY_SIZE
-.global trap_instruction_16_tl0
-trap_instruction_16_tl0:
-    TRAP_INSTRUCTION 16
-/* TT = 0x111, TL = 0, trap_instruction_17 */
-.org trap_table + TT_TRAP_INSTRUCTION(17)*ENTRY_SIZE
-.global trap_instruction_17_tl0
-trap_instruction_17_tl0:
-    TRAP_INSTRUCTION 17
-/* TT = 0x112, TL = 0, trap_instruction_18 */
-.org trap_table + TT_TRAP_INSTRUCTION(18)*ENTRY_SIZE
-.global trap_instruction_18_tl0
-trap_instruction_18_tl0:
-    TRAP_INSTRUCTION 18
-/* TT = 0x113, TL = 0, trap_instruction_19 */
-.org trap_table + TT_TRAP_INSTRUCTION(19)*ENTRY_SIZE
-.global trap_instruction_19_tl0
-trap_instruction_19_tl0:
-    TRAP_INSTRUCTION 19
-/* TT = 0x114, TL = 0, trap_instruction_20 */
-.org trap_table + TT_TRAP_INSTRUCTION(20)*ENTRY_SIZE
-.global trap_instruction_20_tl0
-trap_instruction_20_tl0:
-    TRAP_INSTRUCTION 20
-/* TT = 0x115, TL = 0, trap_instruction_21 */
-.org trap_table + TT_TRAP_INSTRUCTION(21)*ENTRY_SIZE
-.global trap_instruction_21_tl0
-trap_instruction_21_tl0:
-    TRAP_INSTRUCTION 21
-/* TT = 0x116, TL = 0, trap_instruction_22 */
-.org trap_table + TT_TRAP_INSTRUCTION(22)*ENTRY_SIZE
-.global trap_instruction_22_tl0
-trap_instruction_22_tl0:
-    TRAP_INSTRUCTION 22
-/* TT = 0x117, TL = 0, trap_instruction_23 */
-.org trap_table + TT_TRAP_INSTRUCTION(23)*ENTRY_SIZE
-.global trap_instruction_23_tl0
-trap_instruction_23_tl0:
-    TRAP_INSTRUCTION 23
-/* TT = 0x118, TL = 0, trap_instruction_24 */
-.org trap_table + TT_TRAP_INSTRUCTION(24)*ENTRY_SIZE
-.global trap_instruction_24_tl0
-trap_instruction_24_tl0:
-    TRAP_INSTRUCTION 24
-/* TT = 0x119, TL = 0, trap_instruction_25 */
-.org trap_table + TT_TRAP_INSTRUCTION(25)*ENTRY_SIZE
-.global trap_instruction_25_tl0
-trap_instruction_25_tl0:
-    TRAP_INSTRUCTION 25
-/* TT = 0x11a, TL = 0, trap_instruction_26 */
-.org trap_table + TT_TRAP_INSTRUCTION(26)*ENTRY_SIZE
-.global trap_instruction_26_tl0
-trap_instruction_26_tl0:
-    TRAP_INSTRUCTION 26
-/* TT = 0x11b, TL = 0, trap_instruction_27 */
-.org trap_table + TT_TRAP_INSTRUCTION(27)*ENTRY_SIZE
-.global trap_instruction_27_tl0
-trap_instruction_27_tl0:
-    TRAP_INSTRUCTION 27
-/* TT = 0x11c, TL = 0, trap_instruction_28 */
-.org trap_table + TT_TRAP_INSTRUCTION(28)*ENTRY_SIZE
-.global trap_instruction_28_tl0
-trap_instruction_28_tl0:
-    TRAP_INSTRUCTION 28
-/* TT = 0x11d, TL = 0, trap_instruction_29 */
-.org trap_table + TT_TRAP_INSTRUCTION(29)*ENTRY_SIZE
-.global trap_instruction_29_tl0
-trap_instruction_29_tl0:
-    TRAP_INSTRUCTION 29
-/* TT = 0x11e, TL = 0, trap_instruction_30 */
-.org trap_table + TT_TRAP_INSTRUCTION(30)*ENTRY_SIZE
-.global trap_instruction_30_tl0
-trap_instruction_30_tl0:
-    TRAP_INSTRUCTION 30
-/* TT = 0x11f, TL = 0, trap_instruction_31 */
-.org trap_table + TT_TRAP_INSTRUCTION(31)*ENTRY_SIZE
-.global trap_instruction_31_tl0
-trap_instruction_31_tl0:
-    TRAP_INSTRUCTION 31
 /*
  * Handlers for TL>0.
  */
 ,10 → 606,10
     add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
 .else
     /*
-     * Call the higher-level syscall handler.
+     * Call the higher-level syscall handler and enable interrupts.
      */
     call syscall_handler
-    nop
+    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT | PSTATE_IE_BIT, %pstate
     mov %o0, %i0                ! copy the value returned by the syscall
 .endif
 ,9 → 748,8
      * Fill all windows stored in the buffer.
      */
     clr %g4
-    set PAGE_SIZE - 1, %g5
-:  andcc %g7, %g5, %g0         ! PAGE_SIZE alignment check
-    bz 0f                   ! %g7 is page-aligned, no more windows to refill
+:  andcc %g7, UWB_ALIGNMENT - 1, %g0   ! alignment check
+    bz 0f                   ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill
     nop
     add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7

 /branches/network/kernel/arch/sparc64/src/cpu/cpu.c
 ,12 → 32,46
 /** @file
  */
+#include <arch/cpu_family.h>
 #include <cpu.h>
 #include <arch.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <arch/drivers/tick.h>
 #include <print.h>
+#include <arch/cpu_node.h>
+/**
+ * Finds out the clock frequency of the current CPU.
+ *
+ * @param node  node representing the current CPU in the OFW tree
+ * @return  clock frequency if "node" is the current CPU and no error
+ *      occurs, -1 if "node" is not the current CPU or on error
+ */
+static int find_cpu_frequency(ofw_tree_node_t *node)
+{
+    ofw_tree_property_t *prop;
+    uint32_t mid;
+    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
+    prop = ofw_tree_getprop(node, "upa-portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "cpuid");
+    if (prop && prop->value) {
+        mid = *((uint32_t *) prop->value);
+        if (mid == CPU->arch.mid) {
+            prop = ofw_tree_getprop(node, "clock-frequency");
+            if (prop && prop->value) {
+                return *((uint32_t *) prop->value);
+            }
+        }
+    }
+    return -1;
+}
 /** Perform sparc64 specific initialization of the processor structure for the
  * current processor.
  */
 ,34 → 78,37
 void cpu_arch_init(void)
 {
     ofw_tree_node_t *node;
-    uint32_t mid;
     uint32_t clock_frequency = 0;
-    upa_config_t upa_config;
-    upa_config.value = upa_config_read();
-    CPU->arch.mid = upa_config.mid;
+    CPU->arch.mid = read_mid();
     /*
      * Detect processor frequency.
      */
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    while (node) {
-        ofw_tree_property_t *prop;
-        prop = ofw_tree_getprop(node, "upa-portid");
-        if (prop && prop->value) {
-            mid = *((uint32_t *) prop->value);
-            if (mid == CPU->arch.mid) {
-                prop = ofw_tree_getprop(node,
-                    "clock-frequency");
-                if (prop && prop->value)
-                    clock_frequency = *((uint32_t *)
-                        prop->value);
-            }
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        while (node) {
+            int f = find_cpu_frequency(node);
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            node = ofw_tree_find_peer_by_device_type(node, "cpu");
         }
-        node = ofw_tree_find_peer_by_device_type(node, "cpu");
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            int f;
+            f = find_cpu_frequency(
+                ofw_tree_find_child(node, "cpu@0"));
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            f = find_cpu_frequency(
+                ofw_tree_find_child(node, "cpu@1"));
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            node = ofw_tree_find_peer_by_name(node, "cmp");
+        }
     }
     CPU->arch.clock_frequency = clock_frequency;
     tick_init();
 }
 ,6 → 161,15
     case IMPL_ULTRASPARCIII:
         impl = "UltraSPARC III";
         break;
+    case IMPL_ULTRASPARCIII_PLUS:
+        impl = "UltraSPARC III+";
+        break;
+    case IMPL_ULTRASPARCIII_I:
+        impl = "UltraSPARC IIIi";
+        break;
+    case IMPL_ULTRASPARCIV:
+        impl = "UltraSPARC IV";
+        break;
     case IMPL_ULTRASPARCIV_PLUS:
         impl = "UltraSPARC IV+";
         break;

 /branches/network/kernel/arch/sparc64/src/mm/tlb.c
 ,14 → 54,13
 #include <arch/mm/tsb.h>
 #endif
-static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
-static void itlb_pte_copy(pte_t *t, index_t index);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
-    const char *str);
-static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str);
-static void do_fast_data_access_protection_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str);
+static void dtlb_pte_copy(pte_t *, index_t, bool);
+static void itlb_pte_copy(pte_t *, index_t);
+static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
+static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
+    const char *);
+static void do_fast_data_access_protection_fault(istate_t *,
+    tlb_tag_access_reg_t, const char *);
 char *context_encoding[] = {
     "Primary",
 ,11 → 85,11
 /** Insert privileged mapping into DMMU TLB.
  *
- * @param page Virtual page address.
- * @param frame Physical frame address.
- * @param pagesize Page size.
- * @param locked True for permanent mappings, false otherwise.
- * @param cacheable True if the mapping is cacheable, false otherwise.
+ * @param page      Virtual page address.
+ * @param frame     Physical frame address.
+ * @param pagesize  Page size.
+ * @param locked    True for permanent mappings, false otherwise.
+ * @param cacheable True if the mapping is cacheable, false otherwise.
  */
 void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
     bool locked, bool cacheable)
 ,7 → 102,7
     pg.address = page;
     fr.address = frame;
-    tag.value = ASID_KERNEL;
+    tag.context = ASID_KERNEL;
     tag.vpn = pg.vpn;
     dtlb_tag_access_write(tag.value);
 ,10 → 125,10
 /** Copy PTE to TLB.
  *
- * @param t     Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
- * @param ro    If true, the entry will be created read-only, regardless of its
- *      w field.
+ * @param t         Page Table Entry to be copied.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param ro        If true, the entry will be created read-only, regardless
+ *          of its w field.
  */
 void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
 {
 ,8 → 164,8
 /** Copy PTE to ITLB.
  *
- * @param t     Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param t     Page Table Entry to be copied.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
  */
 void itlb_pte_copy(pte_t *t, index_t index)
 {
 ,10 → 234,11
  * Note that some faults (e.g. kernel faults) were already resolved by the
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param tag Content of the TLB Tag Access register as it existed when the
- *    trap happened. This is to prevent confusion created by clobbered
- *    Tag Access register during a nested DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param tag       Content of the TLB Tag Access register as it existed
+ *          when the trap happened. This is to prevent confusion
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
 {
 ,10 → 287,11
 /** DTLB protection fault handler.
  *
- * @param tag Content of the TLB Tag Access register as it existed when the
- *    trap happened. This is to prevent confusion created by clobbered
- *    Tag Access register during a nested DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param tag       Content of the TLB Tag Access register as it existed
+ *          when the trap happened. This is to prevent confusion
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
 {
 ,6 → 332,26
     }
 }
+/** Print TLB entry (for debugging purposes).
+ *
+ * The diag field has been left out in order to make this function more generic
+ * (there is no diag field in US3 architeture).
+ *
+ * @param i     TLB entry number
+ * @param t     TLB entry tag
+ * @param d     TLB entry data
+ */
+static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
+{
+    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
+        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
+        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
+        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
+        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+}
+#if defined (US)
 /** Print contents of both TLBs. */
 void tlb_print(void)
 {
 ,12 → 363,7
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         t.value = itlb_tag_read_read(i);
-        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
-            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+        print_tlb_entry(i, t, d);
     }
     printf("D-TLB contents:\n");
 ,22 → 370,63
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         t.value = dtlb_tag_read_read(i);
-        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
-            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+        print_tlb_entry(i, t, d);
     }
+}
+#elif defined (US3)
+/** Print contents of all TLBs. */
+void tlb_print(void)
+{
+    int i;
+    tlb_data_t d;
+    tlb_tag_read_reg_t t;
+    printf("TLB_ISMALL contents:\n");
+    for (i = 0; i < tlb_ismall_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_ISMALL, i);
+        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_IBIG contents:\n");
+    for (i = 0; i < tlb_ibig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_IBIG, i);
+        t.value = dtlb_tag_read_read(TLB_IBIG, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DSMALL contents:\n");
+    for (i = 0; i < tlb_dsmall_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DSMALL, i);
+        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DBIG_1 contents:\n");
+    for (i = 0; i < tlb_dbig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
+        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DBIG_2 contents:\n");
+    for (i = 0; i < tlb_dbig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
+        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
+        print_tlb_entry(i, t, d);
+    }
 }
+#endif
 void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
     const char *str)
 {
-    fault_if_from_uspace(istate, "%s\n", str);
+    fault_if_from_uspace(istate, "%s.", str);
     dump_istate(istate);
-    panic("%s\n", str);
+    panic("%s.", str);
 }
 void do_fast_data_access_mmu_miss_fault(istate_t *istate,
 ,12 → 436,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
             tag.context);
     }
     dump_istate(istate);
-    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
-    panic("%s\n", str);
+    printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
+    panic("%s.", str);
 }
 void do_fast_data_access_protection_fault(istate_t *istate,
 ,12 → 452,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
             tag.context);
     }
     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
     dump_istate(istate);
-    panic("%s\n", str);
+    panic("%s.", str);
 }
 void dump_sfsr_and_sfar(void)
 ,30 → 468,71
     sfsr.value = dtlb_sfsr_read();
     sfar = dtlb_sfar_read();
+#if defined (US)
     printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
         "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
         sfsr.ow, sfsr.fv);
+#elif defined (US3)
+    printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
+        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
+        sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
+#endif
     printf("DTLB SFAR: address=%p\n", sfar);
     dtlb_sfsr_write(0);
 }
+#if defined (US3)
+/** Invalidates given TLB entry if and only if it is non-locked or global.
+ *
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1,
+ *          TLB_ISMALL, TLB_IBIG).
+ * @param entry     Entry index within the given TLB.
+ */
+static void tlb_invalidate_entry(int tlb, index_t entry)
+{
+    tlb_data_t d;
+    tlb_tag_read_reg_t t;
+    if (tlb == TLB_DSMALL || tlb == TLB_DBIG_0 || tlb == TLB_DBIG_1) {
+        d.value = dtlb_data_access_read(tlb, entry);
+        if (!d.l || d.g) {
+            t.value = dtlb_tag_read_read(tlb, entry);
+            d.v = false;
+            dtlb_tag_access_write(t.value);
+            dtlb_data_access_write(tlb, entry, d.value);
+        }
+    } else if (tlb == TLB_ISMALL || tlb == TLB_IBIG) {
+        d.value = itlb_data_access_read(tlb, entry);
+        if (!d.l || d.g) {
+            t.value = itlb_tag_read_read(tlb, entry);
+            d.v = false;
+            itlb_tag_access_write(t.value);
+            itlb_data_access_write(tlb, entry, d.value);
+        }
+    }
+}
+#endif
 /** Invalidate all unlocked ITLB and DTLB entries. */
 void tlb_invalidate_all(void)
 {
     int i;
-    tlb_data_t d;
-    tlb_tag_read_reg_t t;
     /*
      * Walk all ITLB and DTLB entries and remove all unlocked mappings.
      *
      * The kernel doesn't use global mappings so any locked global mappings
-     * found  must have been created by someone else. Their only purpose now
+     * found must have been created by someone else. Their only purpose now
      * is to collide with proper mappings. Invalidate immediately. It should
      * be safe to invalidate them as late as now.
      */
+#if defined (US)
+    tlb_data_t d;
+    tlb_tag_read_reg_t t;
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         if (!d.l || d.g) {
 ,7 → 542,7
             itlb_data_access_write(i, d.value);
         }
     }
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         if (!d.l || d.g) {
 ,7 → 552,21
             dtlb_data_access_write(i, d.value);
         }
     }
+#elif defined (US3)
+    for (i = 0; i < tlb_ismall_size(); i++)
+        tlb_invalidate_entry(TLB_ISMALL, i);
+    for (i = 0; i < tlb_ibig_size(); i++)
+        tlb_invalidate_entry(TLB_IBIG, i);
+    for (i = 0; i < tlb_dsmall_size(); i++)
+        tlb_invalidate_entry(TLB_DSMALL, i);
+    for (i = 0; i < tlb_dbig_size(); i++)
+        tlb_invalidate_entry(TLB_DBIG_0, i);
+    for (i = 0; i < tlb_dbig_size(); i++)
+        tlb_invalidate_entry(TLB_DBIG_1, i);
+#endif
 }
 /** Invalidate all ITLB and DTLB entries that belong to specified ASID
 ,9 → 596,9
 /** Invalidate all ITLB and DTLB entries for specified page range in specified
  * address space.
  *
- * @param asid Address Space ID.
- * @param page First page which to sweep out from ITLB and DTLB.
- * @param cnt Number of ITLB and DTLB entries to invalidate.
+ * @param asid      Address Space ID.
+ * @param page      First page which to sweep out from ITLB and DTLB.
+ * @param cnt       Number of ITLB and DTLB entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 {

 /branches/network/kernel/arch/sparc64/src/mm/as.c
 ,7 → 164,25
     itsb_base_write(tsb_base.value);
     tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
     dtsb_base_write(tsb_base.value);
+#if defined (US3)
+    /*
+     * Clear the extension registers.
+     * In HelenOS, primary and secondary context registers contain
+     * equal values and kernel misses (context 0, ie. the nucleus context)
+     * are excluded from the TSB miss handler, so it makes no sense
+     * to have separate TSBs for primary, secondary and nucleus contexts.
+     * Clearing the extension registers will ensure that the value of the
+     * TSB Base register will be used as an address of TSB, making the code
+     * compatible with the US port.
+     */
+    itsb_primary_extension_write(0);
+    itsb_nucleus_extension_write(0);
+    dtsb_primary_extension_write(0);
+    dtsb_secondary_extension_write(0);
+    dtsb_nucleus_extension_write(0);
 #endif
+#endif
 }
 /** Perform sparc64-specific tasks when an address space is removed from the

 /branches/network/kernel/arch/sparc64/src/mm/cache.S
 ,45 → 47,3
     retl
     ! beware SF Erratum #51, do not put the MEMBAR here
     nop
-/** Flush only D-cache lines of one virtual color.
- *
- * @param o0    Virtual color to be flushed.
- */
-.global dcache_flush_color
-dcache_flush_color:
-    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
-    set DCACHE_SIZE / 2, %g2
-    sllx %g2, %o0, %g2
-    sub %g2, DCACHE_LINE_SIZE, %g2
-:  stxa %g0, [%g2] ASI_DCACHE_TAG
-    membar #Sync
-    subcc %g1, 1, %g1
-    bnz,pt %xcc, 0b
-    sub %g2, DCACHE_LINE_SIZE, %g2
-    retl
-    nop
-/** Flush only D-cache lines of one virtual color and one tag.
- *
- * @param o0    Virtual color to lookup the tag.
- * @param o1    Tag of the cachelines to be flushed.
- */
-.global dcache_flush_tag
-dcache_flush_tag:
-    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
-    set DCACHE_SIZE / 2, %g2
-    sllx %g2, %o0, %g2
-    sub %g2, DCACHE_LINE_SIZE, %g2
-:  ldxa [%g2] ASI_DCACHE_TAG, %g3
-    srlx %g3, DCACHE_TAG_SHIFT, %g3
-    cmp %g3, %o1
-    bnz 1f
-    nop
-    stxa %g0, [%g2] ASI_DCACHE_TAG
-    membar #Sync
-:  subcc %g1, 1, %g1
-    bnz,pt %xcc, 0b
-    sub %g2, DCACHE_LINE_SIZE, %g2
-    retl
-    nop

 /branches/network/kernel/arch/sparc64/src/mm/tsb.c
 ,9 → 112,9
     tsb->data.value = 0;
     tsb->data.size = PAGESIZE_8K;
     tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-    tsb->data.cp = t->c;
-    tsb->data.p = t->k;     /* p as privileged */
-    tsb->data.v = t->p;
+    tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
+    tsb->data.p = t->k; /* p as privileged, k as kernel */
+    tsb->data.v = t->p; /* v as valid, p as present */
     write_barrier();
 ,3 → 173,4
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,7 → 79,6
          */
         frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1);
     }
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/mm/page.c
 ,5 → 1,5
 /*
- * Copyright (c) 2005 Jakub Jermar
+ * Copyright (c) 2009 Jakub Jermar
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,126 → 42,27
 #include <align.h>
 #include <config.h>
-#ifdef CONFIG_SMP
-/** Entries locked in DTLB of BSP.
- *
- * Application processors need to have the same locked entries in their DTLBs as
- * the bootstrap processor.
- */
-static struct {
-    uintptr_t virt_page;
-    uintptr_t phys_page;
-    int pagesize_code;
-} bsp_locked_dtlb_entry[DTLB_ENTRY_COUNT];
-/** Number of entries in bsp_locked_dtlb_entry array. */
-static count_t bsp_locked_dtlb_entries = 0;
-#endif /* CONFIG_SMP */
 /** Perform sparc64 specific initialization of paging. */
 void page_arch_init(void)
 {
-    if (config.cpu_active == 1) {
+    if (config.cpu_active == 1)
         page_mapping_operations = &ht_mapping_operations;
-    } else {
-#ifdef CONFIG_SMP
-        unsigned int i;
-        /*
-         * Copy locked DTLB entries from the BSP.
-         */
-        for (i = 0; i < bsp_locked_dtlb_entries; i++) {
-            dtlb_insert_mapping(bsp_locked_dtlb_entry[i].virt_page,
-                bsp_locked_dtlb_entry[i].phys_page,
-                bsp_locked_dtlb_entry[i].pagesize_code, true,
-                false);
-        }
-#endif
-    }
 }
 /** Map memory-mapped device into virtual memory.
  *
- * So far, only DTLB is used to map devices into memory. Chances are that there
- * will be only a limited amount of devices that the kernel itself needs to
- * lock in DTLB.
+ * We are currently using identity mapping for mapping device registers.
  *
- * @param physaddr Physical address of the page where the device is located.
- *  Must be at least page-aligned.
- * @param size Size of the device's registers. Must not exceed 4M and must
- *  include extra space caused by the alignment.
+ * @param physaddr  Physical address of the page where the device is
+ *          located.
+ * @param size      Size of the device's registers. This argument is
+ *          ignored.
  *
- * @return Virtual address of the page where the device is mapped.
+ * @return      Virtual address of the page where the device is mapped.
  */
 uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
-    unsigned int order;
-    unsigned int i;
-    ASSERT(config.cpu_active == 1);
-    struct {
-        int pagesize_code;
-        size_t increment;
-        count_t count;
-    } sizemap[] = {
-        { PAGESIZE_8K, 0, 1 },              /* 8K */
-        { PAGESIZE_8K, MMU_PAGE_SIZE, 2 },      /* 16K */
-        { PAGESIZE_8K, MMU_PAGE_SIZE, 4 },      /* 32K */
-        { PAGESIZE_64K, 0, 1},              /* 64K */
-        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 2 },     /* 128K */
-        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 4 },     /* 256K */
-        { PAGESIZE_512K, 0, 1 },            /* 512K */
-        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 2 },   /* 1M */
-        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 4 },   /* 2M */
-        { PAGESIZE_4M, 0, 1 },              /* 4M */
-        { PAGESIZE_4M, 512 * MMU_PAGE_SIZE, 2 }     /* 8M */
-    };
-    ASSERT(ALIGN_UP(physaddr, MMU_PAGE_SIZE) == physaddr);
-    ASSERT(size <= 8 * 1024 * 1024);
-    if (size <= MMU_FRAME_SIZE)
-        order = 0;
-    else
-        order = (fnzb64(size - 1) + 1) - MMU_FRAME_WIDTH;
-    /*
-     * Use virtual addresses that are beyond the limit of physical memory.
-     * Thus, the physical address space will not be wasted by holes created
-     * by frame_alloc().
-     */
-    ASSERT(PA2KA(last_frame));
-    uintptr_t virtaddr = ALIGN_UP(PA2KA(last_frame),
-<< (order + FRAME_WIDTH));
-    last_frame = ALIGN_UP(KA2PA(virtaddr) + size,
-<< (order + FRAME_WIDTH));
-    for (i = 0; i < sizemap[order].count; i++) {
-        /*
-         * First, insert the mapping into DTLB.
-         */
-        dtlb_insert_mapping(virtaddr + i * sizemap[order].increment,
-            physaddr + i * sizemap[order].increment,
-            sizemap[order].pagesize_code, true, false);
-#ifdef CONFIG_SMP
-        /*
-         * Second, save the information about the mapping for APs.
-         */
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].virt_page =
-            virtaddr + i * sizemap[order].increment;
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].phys_page =
-            physaddr + i * sizemap[order].increment;
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].pagesize_code =
-            sizemap[order].pagesize_code;
-        bsp_locked_dtlb_entries++;
-#endif
-    }
-    return virtaddr;
+    return PA2KA(physaddr);
 }
 /** @}

 /branches/network/kernel/arch/sparc64/src/drivers/fhc.c
 ,6 → 45,7
 #include <mm/slab.h>
 #include <arch/types.h>
 #include <genarch/ofw/ofw_tree.h>
+#include <sysinfo/sysinfo.h>
 fhc_t *central_fhc = NULL;
 ,6 → 87,13
     fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
+    /*
+     * Set sysinfo data needed by the uspace FHC driver.
+     */
+    sysinfo_set_item_val("fhc.uart.size", NULL, reg->size);
+    sysinfo_set_item_val("fhc.uart.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.fhc", NULL, 1);
     return fhc;
 }
 ,13 → 104,14
         fhc->uart_imap[FHC_UART_IMAP] |= IMAP_V_MASK;
         break;
     default:
-        panic("Unexpected INR (%d)\n", inr);
+        panic("Unexpected INR (%d).", inr);
         break;
     }
 }
-void fhc_clear_interrupt(fhc_t *fhc, int inr)
+void fhc_clear_interrupt(void *fhcp, int inr)
 {
+    fhc_t *fhc = (fhc_t *)fhcp;
     ASSERT(fhc->uart_imap);
     switch (inr) {
 ,7 → 119,7
         fhc->uart_imap[FHC_UART_ICLR] = 0;
         break;
     default:
-        panic("Unexpected INR (%d)\n", inr);
+        panic("Unexpected INR (%d).", inr);
         break;
     }
 }

 /branches/network/kernel/arch/sparc64/src/drivers/kbd.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64
+/** @addtogroup sparc64
  * @{
  */
 /** @file
 ,22 → 34,30
 #include <arch/drivers/kbd.h>
 #include <genarch/ofw/ofw_tree.h>
+#ifdef CONFIG_SUN_KBD
+#include <genarch/kbrd/kbrd.h>
+#endif
 #ifdef CONFIG_Z8530
-#include <genarch/kbd/z8530.h>
+#include <genarch/drivers/z8530/z8530.h>
 #endif
 #ifdef CONFIG_NS16550
-#include <genarch/kbd/ns16550.h>
+#include <genarch/drivers/ns16550/ns16550.h>
 #endif
-#include <ddi/device.h>
+#include <console/console.h>
 #include <ddi/irq.h>
 #include <arch/mm/page.h>
 #include <arch/types.h>
 #include <align.h>
-#include <func.h>
+#include <string.h>
 #include <print.h>
+#include <sysinfo/sysinfo.h>
 kbd_type_t kbd_type = KBD_UNKNOWN;
+#ifdef CONFIG_SUN_KBD
 /** Initialize keyboard.
  *
  * Traverse OpenFirmware device tree in order to find necessary
 ,7 → 71,16
     uintptr_t aligned_addr;
     ofw_tree_property_t *prop;
     const char *name;
+    cir_t cir;
+    void *cir_arg;
+#ifdef CONFIG_NS16550
+    ns16550_t *ns16550;
+#endif
+#ifdef CONFIG_Z8530
+    z8530_t *z8530;
+#endif
     name = ofw_tree_node_name(node);
     /*
 ,30 → 101,32
      */
     uint32_t interrupts;
     prop = ofw_tree_getprop(node, "interrupts");
-    if (!prop || !prop->value)
-        panic("Can't find \"interrupts\" property.\n");
+    if ((!prop) || (!prop->value))
+        panic("Cannot find 'interrupt' property.");
     interrupts = *((uint32_t *) prop->value);
     /*
      * Read 'reg' property.
      */
     prop = ofw_tree_getprop(node, "reg");
-    if (!prop || !prop->value)
-        panic("Can't find \"reg\" property.\n");
+    if ((!prop) || (!prop->value))
+        panic("Cannot find 'reg' property.");
     uintptr_t pa;
     size_t size;
     inr_t inr;
-    devno_t devno = device_assign_devno();
     switch (kbd_type) {
     case KBD_Z8530:
         size = ((ofw_fhc_reg_t *) prop->value)->size;
-        if (!ofw_fhc_apply_ranges(node->parent, ((ofw_fhc_reg_t *) prop->value) , &pa)) {
+        if (!ofw_fhc_apply_ranges(node->parent,
+            ((ofw_fhc_reg_t *) prop->value), &pa)) {
             printf("Failed to determine keyboard address.\n");
             return;
         }
-        if (!ofw_fhc_map_interrupt(node->parent, ((ofw_fhc_reg_t *) prop->value), interrupts, &inr)) {
+        if (!ofw_fhc_map_interrupt(node->parent,
+            ((ofw_fhc_reg_t *) prop->value), interrupts, &inr, &cir,
+            &cir_arg)) {
             printf("Failed to determine keyboard interrupt.\n");
             return;
         }
 ,18 → 134,20
     case KBD_NS16550:
         size = ((ofw_ebus_reg_t *) prop->value)->size;
-        if (!ofw_ebus_apply_ranges(node->parent, ((ofw_ebus_reg_t *) prop->value) , &pa)) {
+        if (!ofw_ebus_apply_ranges(node->parent,
+            ((ofw_ebus_reg_t *) prop->value), &pa)) {
             printf("Failed to determine keyboard address.\n");
             return;
         }
-        if (!ofw_ebus_map_interrupt(node->parent, ((ofw_ebus_reg_t *) prop->value), interrupts, &inr)) {
+        if (!ofw_ebus_map_interrupt(node->parent,
+            ((ofw_ebus_reg_t *) prop->value), interrupts, &inr, &cir,
+            &cir_arg)) {
             printf("Failed to determine keyboard interrupt.\n");
             return;
         };
         break;
     default:
-        panic("Unexpected type.\n");
+        panic("Unexpected keyboard type.");
     }
     /*
 ,23 → 158,57
      */
     aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
     offset = pa - aligned_addr;
-    uintptr_t vaddr = hw_map(aligned_addr, offset + size) + offset;
     switch (kbd_type) {
 #ifdef CONFIG_Z8530
     case KBD_Z8530:
-        z8530_init(devno, inr, vaddr);
+        z8530 = (z8530_t *) hw_map(aligned_addr, offset + size) +
+            offset;
+        indev_t *kbrdin_z8530 = z8530_init(z8530, inr, cir, cir_arg);
+        if (kbrdin_z8530)
+            kbrd_init(kbrdin_z8530);
+        /*
+         * This is the necessary evil until the userspace drivers are
+         * entirely self-sufficient.
+         */
+        sysinfo_set_item_val("kbd", NULL, true);
+        sysinfo_set_item_val("kbd.type", NULL, KBD_Z8530);
+        sysinfo_set_item_val("kbd.inr", NULL, inr);
+        sysinfo_set_item_val("kbd.address.kernel", NULL,
+            (uintptr_t) z8530);
+        sysinfo_set_item_val("kbd.address.physical", NULL, pa);
         break;
 #endif
 #ifdef CONFIG_NS16550
     case KBD_NS16550:
-        ns16550_init(devno, inr, vaddr);
+        ns16550 = (ns16550_t *) hw_map(aligned_addr, offset + size) +
+            offset;
+        indev_t *kbrdin_ns16550 = ns16550_init(ns16550, inr, cir, cir_arg);
+        if (kbrdin_ns16550)
+            kbrd_init(kbrdin_ns16550);
+        /*
+         * This is the necessary evil until the userspace driver is
+         * entirely self-sufficient.
+         */
+        sysinfo_set_item_val("kbd", NULL, true);
+        sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
+        sysinfo_set_item_val("kbd.inr", NULL, inr);
+        sysinfo_set_item_val("kbd.address.kernel", NULL,
+            (uintptr_t) ns16550);
+        sysinfo_set_item_val("kbd.address.physical", NULL, pa);
         break;
 #endif
     default:
-        printf("Kernel is not compiled with the necessary keyboard driver this machine requires.\n");
+        printf("Kernel is not compiled with the necessary keyboard "
+            "driver this machine requires.\n");
     }
 }
+#endif
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/drivers/scr.c
 ,7 → 37,7
 #include <genarch/fb/fb.h>
 #include <genarch/fb/visuals.h>
 #include <arch/types.h>
-#include <func.h>
+#include <string.h>
 #include <align.h>
 #include <print.h>
 ,6 → 55,10
 void scr_init(ofw_tree_node_t *node)
 {
     ofw_tree_property_t *prop;
+    ofw_pci_reg_t *pci_reg;
+    ofw_pci_reg_t pci_abs_reg;
+    ofw_upa_reg_t *upa_reg;
+    ofw_sbus_reg_t *sbus_reg;
     const char *name;
     name = ofw_tree_node_name(node);
 ,6 → 65,8
     if (strcmp(name, "SUNW,m64B") == 0)
         scr_type = SCR_ATYFB;
+    else if (strcmp(name, "SUNW,XVR-100") == 0)
+        scr_type = SCR_XVR;
     else if (strcmp(name, "SUNW,ffb") == 0)
         scr_type = SCR_FFB;
     else if (strcmp(name, "cgsix") == 0)
 ,11 → 73,12
         scr_type = SCR_CGSIX;
     if (scr_type == SCR_UNKNOWN) {
-        printf("Unknown keyboard device.\n");
+        printf("Unknown screen device.\n");
         return;
     }
     uintptr_t fb_addr;
+    unsigned int fb_offset = 0;
     uint32_t fb_width = 0;
     uint32_t fb_height = 0;
     uint32_t fb_depth = 0;
 ,7 → 104,7
     prop = ofw_tree_getprop(node, "reg");
     if (!prop)
-        panic("Can't find \"reg\" property.\n");
+        panic("Cannot find 'reg' property.");
     switch (scr_type) {
     case SCR_ATYFB:
 ,15 → 113,15
             return;
         }
-        ofw_pci_reg_t *fb_reg = &((ofw_pci_reg_t *) prop->value)[1];
-        ofw_pci_reg_t abs_reg;
+        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
-        if (!ofw_pci_reg_absolutize(node, fb_reg, &abs_reg)) {
+        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
             printf("Failed to absolutize fb register.\n");
             return;
         }
-        if (!ofw_pci_apply_ranges(node->parent, &abs_reg , &fb_addr)) {
+        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
+            &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,12 → 149,56
         }
         break;
+    case SCR_XVR:
+        if (prop->size / sizeof(ofw_pci_reg_t) < 2) {
+            printf("Too few screen registers.\n");
+            return;
+        }
+        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
+        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
+            printf("Failed to absolutize fb register.\n");
+            return;
+        }
+        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
+            &fb_addr)) {
+            printf("Failed to determine screen address.\n");
+            return;
+        }
+        fb_offset = 4 * 0x2000;
+        switch (fb_depth) {
+        case 8:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_INDIRECT_8;
+            break;
+        case 16:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_RGB_5_6_5;
+            break;
+        case 24:
+            fb_scanline = fb_linebytes * 4;
+            visual = VISUAL_RGB_8_8_8_0;
+            break;
+        case 32:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_RGB_0_8_8_8;
+            break;
+        default:
+            printf("Unsupported bits per pixel.\n");
+            return;
+        }
+        break;
     case SCR_FFB:
         fb_scanline = 8192;
         visual = VISUAL_BGR_0_8_8_8;
-        ofw_upa_reg_t *reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
-        if (!ofw_upa_apply_ranges(node->parent, reg, &fb_addr)) {
+        upa_reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
+        if (!ofw_upa_apply_ranges(node->parent, upa_reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,8 → 215,8
             return;
         }
-        ofw_sbus_reg_t *cg6_reg = &((ofw_sbus_reg_t *) prop->value)[0];
-        if (!ofw_sbus_apply_ranges(node->parent, cg6_reg, &fb_addr)) {
+        sbus_reg = &((ofw_sbus_reg_t *) prop->value)[0];
+        if (!ofw_sbus_apply_ranges(node->parent, sbus_reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,11 → 223,24
         break;
     default:
-        panic("Unexpected type.\n");
+        panic("Unexpected type.");
     }
-    fb_init(fb_addr, fb_width, fb_height, fb_scanline, visual);
+    fb_properties_t props = {
+        .addr = fb_addr,
+        .offset = fb_offset,
+        .x = fb_width,
+        .y = fb_height,
+        .scan = fb_scanline,
+        .visual = visual,
+    };
+    fb_init(&props);
 }
+void scr_redraw(void)
+{
+    fb_redraw();
+}
 /** @}
  */

 /branches/network/kernel/arch/sparc64/src/drivers/tick.c
 ,11 → 45,12
 #define TICK_RESTART_TIME   50  /* Worst case estimate. */
-/** Initialize tick interrupt. */
+/** Initialize tick and stick interrupt. */
 void tick_init(void)
 {
+    /* initialize TICK interrupt */
     tick_compare_reg_t compare;
     interrupt_register(14, "tick_int", tick_interrupt);
     compare.int_dis = false;
     compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
 ,6 → 57,21
     CPU->arch.next_tick_cmpr = compare.tick_cmpr;
     tick_compare_write(compare.value);
     tick_write(0);
+#if defined (US3)
+    /* disable STICK interrupts and clear any pending ones */
+    tick_compare_reg_t stick_compare;
+    softint_reg_t clear;
+    stick_compare.value = stick_compare_read();
+    stick_compare.int_dis = true;
+    stick_compare.tick_cmpr = 0;
+    stick_compare_write(stick_compare.value);
+    clear.value = 0;
+    clear.stick_int = 1;
+    clear_softint_write(clear.value);
+#endif
 }
 /** Process tick interrupt.
 ,7 → 83,7
 {
     softint_reg_t softint, clear;
     uint64_t drift;
     softint.value = softint_read();
     /*

 /branches/network/kernel/arch/sparc64/src/drivers/sgcn.c
 ,0 → 1,383
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/**
+ * @file
+ * @brief   SGCN driver.
+ */
+#include <arch.h>
+#include <arch/drivers/sgcn.h>
+#include <arch/drivers/kbd.h>
+#include <genarch/ofw/ofw_tree.h>
+#include <debug.h>
+#include <string.h>
+#include <print.h>
+#include <mm/page.h>
+#include <proc/thread.h>
+#include <console/chardev.h>
+#include <console/console.h>
+#include <sysinfo/sysinfo.h>
+#include <synch/spinlock.h>
+#define POLL_INTERVAL       10000
+/*
+ * Physical address at which the SBBC starts. This value has been obtained
+ * by inspecting (using Simics) memory accesses made by OBP. It is valid
+ * for the Simics-simulated Serengeti machine. The author of this code is
+ * not sure whether this value is valid generally.
+ */
+#define SBBC_START      0x63000000000
+/* offset of SRAM within the SBBC memory */
+#define SBBC_SRAM_OFFSET    0x900000
+/* size (in bytes) of the physical memory area which will be mapped */
+#define MAPPED_AREA_SIZE    (128 * 1024)
+/* magic string contained at the beginning of SRAM */
+#define SRAM_TOC_MAGIC      "TOCSRAM"
+/*
+ * Key into the SRAM table of contents which identifies the entry
+ * describing the OBP console buffer. It is worth mentioning
+ * that the OBP console buffer is not the only console buffer
+ * which can be used. It is, however, used because when the kernel
+ * is running, the OBP buffer is not used by OBP any more but OBP
+ * has already made necessary arrangements so that the output will
+ * be read from the OBP buffer and input will go to the OBP buffer.
+ * Therefore HelenOS needs to make no such arrangements any more.
+ */
+#define CONSOLE_KEY     "OBPCONS"
+/* magic string contained at the beginning of the console buffer */
+#define SGCN_BUFFER_MAGIC   "CON"
+/*
+ * Returns a pointer to the object of a given type which is placed at the given
+ * offset from the SRAM beginning.
+ */
+#define SRAM(type, offset)  ((type *) (sram_begin + (offset)))
+/* Returns a pointer to the SRAM table of contents. */
+#define SRAM_TOC        (SRAM(iosram_toc_t, 0))
+/*
+ * Returns a pointer to the object of a given type which is placed at the given
+ * offset from the console buffer beginning.
+ */
+#define SGCN_BUFFER(type, offset) \
+    ((type *) (sgcn_buffer_begin + (offset)))
+/** Returns a pointer to the console buffer header. */
+#define SGCN_BUFFER_HEADER  (SGCN_BUFFER(sgcn_buffer_header_t, 0))
+/** defined in drivers/kbd.c */
+extern kbd_type_t kbd_type;
+/** starting address of SRAM, will be set by the init_sram_begin function */
+static uintptr_t sram_begin;
+/**
+ * starting address of the SGCN buffer, will be set by the
+ * init_sgcn_buffer_begin function
+ */
+static uintptr_t sgcn_buffer_begin;
+/* true iff the kernel driver should ignore pressed keys */
+static bool kbd_disabled;
+/*
+ * Ensures that writing to the buffer and consequent update of the write pointer
+ * are together one atomic operation.
+ */
+SPINLOCK_INITIALIZE(sgcn_output_lock);
+/*
+ * Prevents the input buffer read/write pointers from getting to inconsistent
+ * state.
+ */
+SPINLOCK_INITIALIZE(sgcn_input_lock);
+/* functions referenced from definitions of I/O operations structures */
+static void sgcn_putchar(outdev_t *, const char, bool);
+/** SGCN output device operations */
+static outdev_operations_t sgcnout_ops = {
+    .write = sgcn_putchar
+};
+/** SGCN input device operations */
+static indev_operations_t sgcnin_ops = {
+    .poll = NULL
+};
+static indev_t sgcnin;      /**< SGCN input device. */
+static outdev_t sgcnout;    /**< SGCN output device. */
+/**
+ * Set some sysinfo values (SRAM address and SRAM size).
+ */
+static void register_sram(uintptr_t sram_begin_physical)
+{
+    sysinfo_set_item_val("sram.area.size", NULL, MAPPED_AREA_SIZE);
+    sysinfo_set_item_val("sram.address.physical", NULL,
+        sram_begin_physical);
+}
+/**
+ * Initializes the starting address of SRAM.
+ *
+ * The SRAM starts 0x900000 + C bytes behind the SBBC start in the
+ * physical memory, where C is the value read from the "iosram-toc"
+ * property of the "/chosen" OBP node. The sram_begin variable will
+ * be set to the virtual address which maps to the SRAM physical
+ * address.
+ */
+static void init_sram_begin(void)
+{
+    ofw_tree_node_t *chosen;
+    ofw_tree_property_t *iosram_toc;
+    uintptr_t sram_begin_physical;
+    chosen = ofw_tree_lookup("/chosen");
+    if (!chosen)
+        panic("Cannot find '/chosen'.");
+    iosram_toc = ofw_tree_getprop(chosen, "iosram-toc");
+    if (!iosram_toc)
+        panic("Cannot find property 'iosram-toc'.");
+    if (!iosram_toc->value)
+        panic("Cannot find SRAM TOC.");
+    sram_begin_physical = SBBC_START + SBBC_SRAM_OFFSET
+        + *((uint32_t *) iosram_toc->value);
+    sram_begin = hw_map(sram_begin_physical, MAPPED_AREA_SIZE);
+    register_sram(sram_begin_physical);
+}
+/**
+ * Initializes the starting address of the SGCN buffer.
+ *
+ * The offset of the SGCN buffer within SRAM is obtained from the
+ * SRAM table of contents. The table of contents contains
+ * information about several buffers, among which there is an OBP
+ * console buffer - this one will be used as the SGCN buffer.
+ *
+ * This function also writes the offset of the SGCN buffer within SRAM
+ * under the sram.buffer.offset sysinfo key.
+ */
+static void sgcn_buffer_begin_init(void)
+{
+    static bool initialized;
+    if (initialized)
+        return;
+    init_sram_begin();
+    ASSERT(strcmp(SRAM_TOC->magic, SRAM_TOC_MAGIC) == 0);
+    /* lookup TOC entry with the correct key */
+    uint32_t i;
+    for (i = 0; i < MAX_TOC_ENTRIES; i++) {
+        if (strcmp(SRAM_TOC->keys[i].key, CONSOLE_KEY) == 0)
+            break;
+    }
+    ASSERT(i < MAX_TOC_ENTRIES);
+    sgcn_buffer_begin = sram_begin + SRAM_TOC->keys[i].offset;
+    sysinfo_set_item_val("sram.buffer.offset", NULL,
+        SRAM_TOC->keys[i].offset);
+    initialized = true;
+}
+/**
+ * Writes a single character to the SGCN (circular) output buffer
+ * and updates the output write pointer so that SGCN gets to know
+ * that the character has been written.
+ */
+static void sgcn_do_putchar(const char c)
+{
+    uint32_t begin = SGCN_BUFFER_HEADER->out_begin;
+    uint32_t end = SGCN_BUFFER_HEADER->out_end;
+    uint32_t size = end - begin;
+    /* we need pointers to volatile variables */
+    volatile char *buf_ptr = (volatile char *)
+        SGCN_BUFFER(char, SGCN_BUFFER_HEADER->out_wrptr);
+    volatile uint32_t *out_wrptr_ptr = &(SGCN_BUFFER_HEADER->out_wrptr);
+    volatile uint32_t *out_rdptr_ptr = &(SGCN_BUFFER_HEADER->out_rdptr);
+    /*
+     * Write the character and increment the write pointer modulo the
+     * output buffer size. Note that if we are to rewrite a character
+     * which has not been read by the SGCN controller yet (i.e. the output
+     * buffer is full), we need to wait until the controller reads some more
+     * characters. We wait actively, which means that all threads waiting
+     * for the lock are blocked. However, this situation is
+     *   1) rare - the output buffer is big, so filling the whole
+     *             output buffer is improbable
+     *   2) short-lasting - it will take the controller only a fraction
+     *             of millisecond to pick the unread characters up
+     *   3) not serious - the blocked threads are those that print something
+     *             to user console, which is not a time-critical operation
+     */
+    uint32_t new_wrptr = (((*out_wrptr_ptr) - begin + 1) % size) + begin;
+    while (*out_rdptr_ptr == new_wrptr)
+        ;
+    *buf_ptr = c;
+    *out_wrptr_ptr = new_wrptr;
+}
+/**
+ * SGCN output operation. Prints a single character to the SGCN. If the line
+ * feed character is written ('\n'), the carriage return character ('\r') is
+ * written straight away.
+ */
+static void sgcn_putchar(outdev_t *od, const char c, bool silent)
+{
+    if (!silent) {
+        spinlock_lock(&sgcn_output_lock);
+        sgcn_do_putchar(c);
+        if (c == '\n')
+            sgcn_do_putchar('\r');
+        spinlock_unlock(&sgcn_output_lock);
+    }
+}
+/**
+ * Grabs the input for kernel.
+ */
+void sgcn_grab(void)
+{
+    kbd_disabled = true;
+}
+/**
+ * Releases the input so that userspace can use it.
+ */
+void sgcn_release(void)
+{
+    kbd_disabled = true;
+}
+/**
+ * Function regularly called by the keyboard polling thread. Finds out whether
+ * there are some unread characters in the input queue. If so, it picks them up
+ * and sends them to the upper layers of HelenOS.
+ */
+static void sgcn_poll()
+{
+    uint32_t begin = SGCN_BUFFER_HEADER->in_begin;
+    uint32_t end = SGCN_BUFFER_HEADER->in_end;
+    uint32_t size = end - begin;
+    if (kbd_disabled)
+        return;
+    spinlock_lock(&sgcn_input_lock);
+    /* we need pointers to volatile variables */
+    volatile char *buf_ptr = (volatile char *)
+        SGCN_BUFFER(char, SGCN_BUFFER_HEADER->in_rdptr);
+    volatile uint32_t *in_wrptr_ptr = &(SGCN_BUFFER_HEADER->in_wrptr);
+    volatile uint32_t *in_rdptr_ptr = &(SGCN_BUFFER_HEADER->in_rdptr);
+    while (*in_rdptr_ptr != *in_wrptr_ptr) {
+        buf_ptr = (volatile char *)
+            SGCN_BUFFER(char, SGCN_BUFFER_HEADER->in_rdptr);
+        char c = *buf_ptr;
+        *in_rdptr_ptr = (((*in_rdptr_ptr) - begin + 1) % size) + begin;
+        indev_push_character(&sgcnin, c);
+    }
+    spinlock_unlock(&sgcn_input_lock);
+}
+/**
+ * Polling thread function.
+ */
+static void kkbdpoll(void *arg) {
+    while (1) {
+        if (!silent) {
+            sgcn_poll();
+        }
+        thread_usleep(POLL_INTERVAL);
+    }
+}
+/**
+ * A public function which initializes input from the Serengeti console.
+ */
+indev_t *sgcnin_init(void)
+{
+    sgcn_buffer_begin_init();
+    kbd_type = KBD_SGCN;
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.type", NULL, KBD_SGCN);
+    thread_t *t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
+    if (!t)
+        panic("Cannot create kkbdpoll.");
+    thread_ready(t);
+    indev_initialize("sgcnin", &sgcnin, &sgcnin_ops);
+    return &sgcnin;
+}
+/**
+ * A public function which initializes output to the Serengeti console.
+ */
+void sgcnout_init(void)
+{
+    sgcn_buffer_begin_init();
+    sysinfo_set_item_val("fb.kind", NULL, 4);
+    outdev_initialize("sgcnout", &sgcnout, &sgcnout_ops);
+    stdout = &sgcnout;
+}
+/** @}
+ */

 /branches/network/kernel/arch/sparc64/src/drivers/pci.c
 ,43 → 42,41
 #include <arch/types.h>
 #include <debug.h>
 #include <print.h>
-#include <func.h>
+#include <string.h>
 #include <arch/asm.h>
+#include <sysinfo/sysinfo.h>
-#define PCI_SABRE_REGS_REG  0
+#define SABRE_INTERNAL_REG  0
+#define PSYCHO_INTERNAL_REG 2
-#define PCI_SABRE_IMAP_BASE 0x200
-#define PCI_SABRE_ICLR_BASE 0x300
+#define OBIO_IMR_BASE   0x200
+#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
-#define PCI_PSYCHO_REGS_REG 2
+#define OBIO_CIR_BASE   0x300
+#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
-#define PCI_PSYCHO_IMAP_BASE    0x200
-#define PCI_PSYCHO_ICLR_BASE    0x300
+static void obio_enable_interrupt(pci_t *, int);
+static void obio_clear_interrupt(pci_t *, int);
-static pci_t *pci_sabre_init(ofw_tree_node_t *node);
-static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
-static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
+static pci_t *pci_sabre_init(ofw_tree_node_t *);
+static pci_t *pci_psycho_init(ofw_tree_node_t *);
-static pci_t *pci_psycho_init(ofw_tree_node_t *node);
-static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
-static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
 /** PCI operations for Sabre model. */
 static pci_operations_t pci_sabre_ops = {
-    .enable_interrupt = pci_sabre_enable_interrupt,
-    .clear_interrupt = pci_sabre_clear_interrupt
+    .enable_interrupt = obio_enable_interrupt,
+    .clear_interrupt = obio_clear_interrupt
 };
 /** PCI operations for Psycho model. */
 static pci_operations_t pci_psycho_ops = {
-    .enable_interrupt = pci_psycho_enable_interrupt,
-    .clear_interrupt = pci_psycho_clear_interrupt
+    .enable_interrupt = obio_enable_interrupt,
+    .clear_interrupt = obio_clear_interrupt
 };
 /** Initialize PCI controller (model Sabre).
  *
- * @param node OpenFirmware device tree node of the Sabre.
+ * @param node      OpenFirmware device tree node of the Sabre.
  *
- * @return Address of the initialized PCI structure.
+ * @return      Address of the initialized PCI structure.
  */
 pci_t *pci_sabre_init(ofw_tree_node_t *node)
 {
 ,11 → 93,12
     ofw_upa_reg_t *reg = prop->value;
     count_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < PCI_SABRE_REGS_REG + 1)
+    if (regs < SABRE_INTERNAL_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
+        &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,8 → 107,14
     pci->model = PCI_SABRE;
     pci->op = &pci_sabre_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
+    /*
+     * Set sysinfo data needed by the uspace OBIO driver.
+     */
+    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
 ,9 → 121,9
 /** Initialize the Psycho PCI controller.
  *
- * @param node OpenFirmware device tree node of the Psycho.
+ * @param node      OpenFirmware device tree node of the Psycho.
  *
- * @return Address of the initialized PCI structure.
+ * @return      Address of the initialized PCI structure.
  */
 pci_t *pci_psycho_init(ofw_tree_node_t *node)
 {
 ,11 → 140,12
     ofw_upa_reg_t *reg = prop->value;
     count_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < PCI_PSYCHO_REGS_REG + 1)
+    if (regs < PSYCHO_INTERNAL_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
+        &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,31 → 154,27
     pci->model = PCI_PSYCHO;
     pci->op = &pci_psycho_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
+    /*
+     * Set sysinfo data needed by the uspace OBIO driver.
+     */
+    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
-void pci_sabre_enable_interrupt(pci_t *pci, int inr)
+void obio_enable_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
+    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
 }
-void pci_sabre_clear_interrupt(pci_t *pci, int inr)
+void obio_clear_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
+    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
 }
-void pci_psycho_enable_interrupt(pci_t *pci, int inr)
-{
-    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
-}
-void pci_psycho_clear_interrupt(pci_t *pci, int inr)
-{
-    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
-}
 /** Initialize PCI controller. */
 pci_t *pci_init(ofw_tree_node_t *node)
 {
 ,14 → 217,14
 void pci_enable_interrupt(pci_t *pci, int inr)
 {
-    ASSERT(pci->model);
     ASSERT(pci->op && pci->op->enable_interrupt);
     pci->op->enable_interrupt(pci, inr);
 }
-void pci_clear_interrupt(pci_t *pci, int inr)
+void pci_clear_interrupt(void *pcip, int inr)
 {
-    ASSERT(pci->model);
+    pci_t *pci = (pci_t *)pcip;
     ASSERT(pci->op && pci->op->clear_interrupt);
     pci->op->clear_interrupt(pci, inr);
 }

 /branches/network/kernel/arch/sparc64/src/start.S
 ,6 → 27,7
 #
 #include <arch/arch.h>
+#include <arch/cpu.h>
 #include <arch/regdef.h>
 #include <arch/boot/boot.h>
 #include <arch/stack.h>
 ,6 → 48,16
 #define BSP_FLAG    1
 /*
+ * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
+ * a given processor.
+ */
+#if defined (US)
+    #define PHYSMEM_ADDR_SIZE   41
+#elif defined (US3)
+    #define PHYSMEM_ADDR_SIZE   43
+#endif
+/*
  * Here is where the kernel is passed control from the boot loader.
  *
  * The registers are expected to be in this state:
 ,11 → 78,13
     and %o0, %l0, %l7           ! l7 <= bootstrap processor?
     andn %o0, %l0, %l6          ! l6 <= start of physical memory
-    ! Get bits 40:13 of physmem_base.
+    ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
     srlx %l6, 13, %l5
-    sllx %l5, 13 + (63 - 40), %l5
-    srlx %l5, 63 - 40, %l5          ! l5 <= physmem_base[40:13]
+    ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
+    sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
+    srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
     /*
      * Setup basic runtime environment.
      */
 ,6 → 96,8
                         ! consistent
     wrpr %g0, NWINDOWS - 1, %cleanwin   ! prevent needless clean_window
                         ! traps for kernel
+    wrpr %g0, 0, %wstate            ! use default spill/fill trap
     wrpr %g0, 0, %tl            ! TL = 0, primary context
                         ! register is used
 ,7 → 259,8
     /*
      * Precompute kernel 8K TLB data template.
-     * %l5 contains starting physical address bits [40:13]
+     * %l5 contains starting physical address
+     * bits [(PHYSMEM_ADDR_SIZE - 1):13]
      */
     sethi %hi(kernel_8k_tlb_data_template), %l4
     ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
 ,15 → 298,32
     nop
+:
+#ifdef CONFIG_SMP
     /*
+     * Determine the width of the MID and save its mask to %g3. The width
+     * is
+     *  * 5 for US and US-IIIi,
+     *  * 10 for US3 except US-IIIi.
+     */
+#if defined(US)
+    mov 0x1f, %g3
+#elif defined(US3)
+    mov 0x3ff, %g3
+    rdpr %ver, %g2
+    sllx %g2, 16, %g2
+    srlx %g2, 48, %g2
+    cmp %g2, IMPL_ULTRASPARCIII_I
+    move %xcc, 0x1f, %g3
+#endif
+    /*
      * Read MID from the processor.
      */
-:
-    ldxa [%g0] ASI_UPA_CONFIG, %g1
-    srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
-    and %g1, UPA_CONFIG_MID_MASK, %g1
+    ldxa [%g0] ASI_ICBUS_CONFIG, %g1
+    srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
+    and %g1, %g3, %g1
-#ifdef CONFIG_SMP
     /*
      * Active loop for APs until the BSP picks them up. A processor cannot
      * leave the loop until the global variable 'waking_up_mid' equals its

 /branches/network/kernel/arch/ia64/include/interrupt.h
 ,10 → 50,13
 #define IVT_FIRST       0
 /** External Interrupt vectors. */
+#define VECTOR_TLB_SHOOTDOWN_IPI 0xf0
 #define INTERRUPT_TIMER     255
-#define IRQ_KBD         241
-#define IRQ_MOUSE       252
+#define IRQ_KBD         (0x01 + LEGACY_INTERRUPT_BASE)
+#define IRQ_MOUSE       (0x0c + LEGACY_INTERRUPT_BASE)
 #define INTERRUPT_SPURIOUS  15
+#define LEGACY_INTERRUPT_BASE   0x20
 /** General Exception codes. */
 #define GE_ILLEGALOP        0
 ,7 → 117,7
     /*
      * The following variables are defined only for break_instruction
-     * handler.
+     * handler.
      */
     uint64_t in0;
     uint64_t in1;
 ,6 → 153,8
 extern void external_interrupt(uint64_t vector, istate_t *istate);
 extern void disabled_fp_register(uint64_t vector, istate_t *istate);
+extern void trap_virtual_enable_irqs(uint16_t irqmask);
 #endif
 /** @}

/branches/network/kernel/arch/ia64/include/fpu_context.h
35,7 → 35,6
#ifndef KERN_ia64_FPU_CONTEXT_H_
#define KERN_ia64_FPU_CONTEXT_H_

#define ARCH_HAS_FPU 1
#define FPU_CONTEXT_ALIGN 16

#include <arch/types.h>

 /branches/network/kernel/arch/ia64/include/ski/ski.h
 ,22 → 35,17
 #ifndef KERN_ia64_SKI_H_
 #define KERN_ia64_SKI_H_
-#include <arch/types.h>
-#include <console/console.h>
+#include <console/chardev.h>
 #define SKI_INIT_CONSOLE    20
 #define SKI_GETCHAR     21
 #define SKI_PUTCHAR     31
-extern chardev_t ski_uconsole;
-extern void ski_init_console(void);
+extern indev_t *skiin_init(void);
+extern void skiout_init(void);
 extern void ski_kbd_grab(void);
 extern void ski_kbd_release(void);
-extern void kkbdpoll(void *arg);
 #endif
 /** @}

 /branches/network/kernel/arch/ia64/include/types.h
 ,6 → 65,11
 typedef uint64_t unative_t;
 typedef int64_t native_t;
+typedef struct {
+    unative_t fnc;
+    unative_t gp;
+} fncptr_t;
 #define PRIp "lx"   /**< Format for uintptr_t. */
 #define PRIs "lu"   /**< Format for size_t. */
 #define PRIc "lu"   /**< Format for count_t. */

 /branches/network/kernel/arch/ia64/include/atomic.h
 ,29 → 37,65
 /** Atomic addition.
  *
- * @param val Atomic value.
- * @param imm Value to add.
+ * @param val       Atomic value.
+ * @param imm       Value to add.
  *
- * @return Value before addition.
+ * @return      Value before addition.
  */
 static inline long atomic_add(atomic_t *val, int imm)
 {
     long v;
-    asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
+    asm volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v),
+        "+m" (val->count) : "i" (imm));
     return v;
 }
-static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
-static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
-static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; }
-static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; }
+static inline uint64_t test_and_set(atomic_t *val) {
+    uint64_t v;
+    asm volatile (
+        "movl %0 = 0x01;;\n"
+        "xchg8 %0 = %1, %0;;\n"
+        : "=r" (v), "+m" (val->count)
+    );
+    return v;
+}
-static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1); }
-static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1); }
+static inline void atomic_inc(atomic_t *val)
+{
+    atomic_add(val, 1);
+}
+static inline void atomic_dec(atomic_t *val)
+{
+    atomic_add(val, -1);
+}
+static inline long atomic_preinc(atomic_t *val)
+{
+    return atomic_add(val, 1) + 1;
+}
+static inline long atomic_predec(atomic_t *val)
+{
+    return atomic_add(val, -1) - 1;
+}
+static inline long atomic_postinc(atomic_t *val)
+{
+    return atomic_add(val, 1);
+}
+static inline long atomic_postdec(atomic_t *val)
+{
+    return atomic_add(val, -1);
+}
 #endif
 /** @}

 /branches/network/kernel/arch/ia64/include/arch.h
 ,6 → 39,8
 #include <arch/ski/ski.h>
+extern void arch_pre_main(void);
 #endif
 /** @}

 /branches/network/kernel/arch/ia64/include/proc/task.h
 ,14 → 31,19
  */
 /** @file
  */
+#include <proc/task.h>
 #ifndef KERN_ia64_TASK_H_
 #define KERN_ia64_TASK_H_
+#include <adt/bitmap.h>
 typedef struct {
+    bitmap_t *iomap;
 } task_arch_t;
-#define task_create_arch(t)
+#define task_create_arch(t) { (t)->arch.iomap = NULL; }
 #define task_destroy_arch(t)
 #endif

 /branches/network/kernel/arch/ia64/include/bootinfo.h
 ,13 → 29,23
 #ifndef KERN_ia64_BOOTINFO_H_
 #define KERN_ia64_BOOTINFO_H_
+#define BOOTINFO_ADDRESS 0x4401000
 #define CONFIG_INIT_TASKS   32
+#define MEMMAP_ITEMS 128
+#define EFI_MEMMAP_FREE_MEM 0
+#define EFI_MEMMAP_IO 1
+#define EFI_MEMMAP_IO_PORTS 2
+/** Size of buffer for storing task name in binit_task_t. */
+#define BOOTINFO_TASK_NAME_BUFLEN 32
 typedef struct {
     void *addr;
     unsigned long size;
+    char name[BOOTINFO_TASK_NAME_BUFLEN];
 } binit_task_t;
 typedef struct {
 ,9 → 53,24
     binit_task_t tasks[CONFIG_INIT_TASKS];
 } binit_t;
+typedef struct {
+    unsigned int type;
+    unsigned long base;
+    unsigned long size;
+}efi_memmap_item_t;
 typedef struct {
     binit_t taskmap;
+    efi_memmap_item_t memmap[MEMMAP_ITEMS];
+    unsigned int memmap_items;
+    unsigned long * sapic;
+    unsigned long sys_freq;
+    unsigned long freq_scale;
+    unsigned int wakeup_intno;
+    int hello_configured;
 } bootinfo_t;
 extern bootinfo_t *bootinfo;

 /branches/network/kernel/arch/ia64/include/asm.h
 ,29 → 36,72
 #define KERN_ia64_ASM_H_
 #include <config.h>
+#include <typedefs.h>
 #include <arch/types.h>
 #include <arch/register.h>
 #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
-static inline void  outb(uint64_t port,uint8_t v)
+static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
-    *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
+    uintptr_t prt = (uintptr_t) port;
+    *((uint8_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
     asm volatile ("mf\n" ::: "memory");
 }
+static inline void pio_write_16(ioport16_t *port, uint16_t v)
+{
+    uintptr_t prt = (uintptr_t) port;
-static inline uint8_t inb(uint64_t port)
+    *((uint16_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
+    asm volatile ("mf\n" ::: "memory");
+}
+static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
+    uintptr_t prt = (uintptr_t) port;
+    *((uint32_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
     asm volatile ("mf\n" ::: "memory");
+}
-    return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
+    uintptr_t prt = (uintptr_t) port;
+    asm volatile ("mf\n" ::: "memory");
+    return *((uint8_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    uintptr_t prt = (uintptr_t) port;
+    asm volatile ("mf\n" ::: "memory");
+    return *((uint16_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12))));
+}
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    uintptr_t prt = (uintptr_t) port;
+    asm volatile ("mf\n" ::: "memory");
+    return *((uint32_t *)(IA64_IOSPACE_ADDRESS +
+        ((prt & 0xfff) | ((prt >> 2) << 12))));
+}
 /** Return base address of current stack
  *
  * Return the base address of the current stack.
 ,9 → 112,14
 {
     uint64_t v;
-    asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+    //I'm not sure why but this code bad inlines in scheduler,
+    //so THE shifts about 16B and causes kernel panic
+    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+    //return v;
-    return v;
+    //this code have the same meaning but inlines well
+    asm volatile ("mov %0 = r12" : "=r" (v)  );
+    return v & (~(STACK_SIZE-1));
 }
 /** Return Processor State Register.
 ,6 → 171,16
     return v;
 }
+static inline uint64_t cr64_read(void)
+{
+    uint64_t v;
+    asm volatile ("mov %0 = cr64\n" : "=r" (v));
+    return v;
+}
 /** Write ITC (Interval Timer Counter) register.
  *
  * @param v New counter value.
 ,7 → 355,8
 extern void cpu_sleep(void);
 extern void asm_delay_loop(uint32_t t);
-extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
+extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
+    uint64_t, uint64_t);
 #endif

 /branches/network/kernel/arch/ia64/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia64mm
+/** @addtogroup ia64mm
  * @{
  */
 /** @file
 ,12 → 35,16
 #ifndef KERN_ia64_FRAME_H_
 #define KERN_ia64_FRAME_H_
-#define FRAME_WIDTH     14  /* 16K */
-#define FRAME_SIZE      (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  14  /* 16K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifdef KERNEL
 #ifndef __ASM__
+#include <arch/types.h>
+extern uintptr_t last_frame;
 extern void frame_arch_init(void);
 #define physmem_print()

 /branches/network/kernel/arch/ia64/include/mm/page.h
 ,8 → 46,25
 /** Bit width of the TLB-locked portion of kernel address space. */
 #define KERNEL_PAGE_WIDTH       28  /* 256M */
 #define IO_PAGE_WIDTH           26  /* 64M */
+#define FW_PAGE_WIDTH           28  /* 256M */
+#define USPACE_IO_PAGE_WIDTH        12  /* 4K */
+/*
+ * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses
+ * because of "minimal virtual bits implemented is 51" it is possible to
+ * have values up to 0x0007000000000000
+ */
+/* Firmware area (bellow 4GB in phys mem) */
+#define FW_OFFSET             0x00000000F0000000
+/* Legacy IO space */
+#define IO_OFFSET             0x0001000000000000
+/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */
+#define VIO_OFFSET            0x0002000000000000
 #define PPN_SHIFT           12
 #define VRN_SHIFT           61
 ,8 → 79,8
 #define REGION_REGISTERS        8
-#define KA2PA(x)    ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
-#define PA2KA(x)    ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
+#define KA2PA(x)    ((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT)))
+#define PA2KA(x)    ((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT)))
 #define VHPT_WIDTH          20  /* 1M */
 #define VHPT_SIZE           (1 << VHPT_WIDTH)

 /branches/network/kernel/arch/ia64/include/mm/tlb.h
 ,9 → 35,6
 #ifndef KERN_ia64_TLB_H_
 #define KERN_ia64_TLB_H_
-#define tlb_arch_init()
-#define tlb_print()
 #include <arch/mm/page.h>
 #include <arch/mm/asid.h>
 #include <arch/interrupt.h>
 ,8 → 43,8
 /** Data and instruction Translation Register indices. */
 #define DTR_KERNEL  0
 #define ITR_KERNEL  0
-#define DTR_KSTACK1 1
-#define DTR_KSTACK2 2
+#define DTR_KSTACK1 4
+#define DTR_KSTACK2 5
 /** Portion of TLB insertion format data structure. */
 union tlb_entry {

 /branches/network/kernel/arch/ia64/include/mm/vhpt.h
 ,8 → 44,8
 {
     vhpt_entry_t ventry;
-    ventry.word[0]=tentry.word[0];
-    ventry.word[1]=tentry.word[1];
+    ventry.word[0] = tentry.word[0];
+    ventry.word[1] = tentry.word[1];
     return ventry;
 }

 /branches/network/kernel/arch/ia64/include/register.h
 ,11 → 40,11
 #define PSR_I_MASK  0x4000
 #define PSR_PK_MASK 0x8000
-#define PSR_DT_MASK (1<<17)
-#define PSR_RT_MASK (1<<27)
+#define PSR_DT_MASK (1 << 17)
+#define PSR_RT_MASK (1 << 27)
-#define PSR_DFL_MASK    (1<<18)
-#define PSR_DFH_MASK    (1<<19)
+#define PSR_DFL_MASK    (1 << 18)
+#define PSR_DFH_MASK    (1 << 19)
 #define PSR_IT_MASK 0x0000001000000000

/branches/network/kernel/arch/ia64/include/debug.h
1,5 → 1,5
/*
* Copyright (c) 2005
* Copyright (c) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

 /branches/network/kernel/arch/ia64/include/cpu.h
 ,6 → 38,7
 #include <arch/types.h>
 #include <arch/register.h>
 #include <arch/asm.h>
+#include <arch/bootinfo.h>
 #define FAMILY_ITANIUM  0x7
 #define FAMILY_ITANIUM2 0x1f
 ,6 → 64,32
     return v;
 }
+#define CR64_ID_SHIFT 24
+#define CR64_ID_MASK 0xff000000
+#define CR64_EID_SHIFT 16
+#define CR64_EID_MASK 0xff0000
+static inline int ia64_get_cpu_id(void)
+{
+    uint64_t cr64=cr64_read();
+    return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
+}
+static inline int ia64_get_cpu_eid(void)
+{
+    uint64_t cr64=cr64_read();
+    return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
+}
+static inline void ipi_send_ipi(int id, int eid, int intno)
+{
+    (bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
+    srlz_d();
+}
 #endif
 /** @}

 /branches/network/kernel/arch/ia64/include/drivers/it.h
 ,7 → 41,7
  * from firmware.
  *
  */
-#define IT_DELTA        100000
+#define IT_DELTA        it_delta
 extern void it_init(void);

 /branches/network/kernel/arch/ia64/include/drivers/kbd.h
 ,0 → 1,46
+/*
+ * Copyright (c) 2006 Jakub Jermar, Jakub Vana
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup ia6464
+ * @{
+ */
+/** @file
+ */
+#ifndef KERN_ia64_KBD_H_
+#define KERN_ia64_KBD_H_
+#define KBD_UNKNOWN  0
+#define KBD_SKI      1
+#define KBD_LEGACY   2
+#define KBD_NS16550  3
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/ia64/Makefile.inc
 ,18 → 29,11
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf64-little
 BFD_ARCH = ia64-elf64
 TARGET = ia64-pc-linux-gnu
 TOOLCHAIN_DIR = $(CROSS_PREFIX)/ia64
-INIT0_ADDRESS = 0xe000000004404000
-INIT0_SIZE = 0x100000
 CMN1 = -mconstant-gp -fno-unwind-tables -mfixed-range=f32-f127
 GCC_CFLAGS += $(CMN1)
 ICC_CFLAGS += $(CMN1)
 ,58 → 41,35
 LFLAGS += -EL
 AFLAGS += -mconstant-gp
-DEFS += -D__64_BITS__ -DINIT0_ADDRESS=$(INIT0_ADDRESS) -DINIT0_SIZE=$(INIT0_SIZE) -D$(MACHINE)
+DEFS += -D__64_BITS__
-## Compile with page hash table support.
-#
-CONFIG_PAGE_HT = y
-DEFS += -DCONFIG_PAGE_HT
-## Compile with support for address space identifiers.
-#
-CONFIG_ASID = y
-CONFIG_ASID_FIFO = y
-## Compile with support for software integer division.
-#
-CONFIG_SOFTINT = y
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/start.S \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/dummy.s \
-    arch/$(ARCH)/src/ia64.c \
-    arch/$(ARCH)/src/fpu_context.c \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/ivt.S \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/mm/vhpt.c \
-    arch/$(ARCH)/src/proc/scheduler.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/it.c
+    arch/$(KARCH)/src/start.S \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/dummy.s \
+    arch/$(KARCH)/src/ia64.c \
+    arch/$(KARCH)/src/fpu_context.c \
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/ivt.S \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/mm/vhpt.c \
+    arch/$(KARCH)/src/proc/scheduler.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/smp/smp.c \
+    arch/$(KARCH)/src/drivers/it.c
 ifeq ($(MACHINE),ski)
-    ARCH_SOURCES += arch/$(ARCH)/src/ski/ski.c
+    ARCH_SOURCES += arch/$(KARCH)/src/ski/ski.c
     DEFS += -DSKI
-#   BFD = elf64-ia64-little
     BFD = binary
 endif
 ifeq ($(MACHINE),i460GX)
-    ARCH_SOURCES += arch/$(ARCH)/src/drivers/ega.c
-    CONFIG_I8042 = y
-    DEFS += -DI460GX -DCONFIG_I8042
+    DEFS += -DI460GX
     BFD = binary
 endif

 /branches/network/kernel/arch/ia64/src/fpu_context.c
 ,8 → 149,10
         "stf.spill [%7] = f127, 0x80\n;;"
         :
-        : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])),
-          "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7]))
+        : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])),
+          "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])),
+          "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])),
+          "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7]))
     );
 }
 ,14 → 269,16
         "ldf.fill f127 = [%7], 0x80\n;;"
         :
-        : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])),
-          "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7]))
+        : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])),
+          "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])),
+          "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])),
+          "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7]))
     );
 }
 void fpu_enable(void)
 {
-    uint64_t a = 0 ;
+    uint64_t a = 0;
     asm volatile (
         "rsm %0 ;;"

 /branches/network/kernel/arch/ia64/src/smp/smp.c
 ,0 → 1,167
+/*
+ * Copyright (c) 2005 Jakub Vana
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup ia64
+ * @{
+ */
+/** @file
+ */
+#include <arch.h>
+#include <arch/ski/ski.h>
+#include <arch/drivers/it.h>
+#include <arch/interrupt.h>
+#include <arch/barrier.h>
+#include <arch/asm.h>
+#include <arch/register.h>
+#include <arch/types.h>
+#include <arch/context.h>
+#include <arch/stack.h>
+#include <arch/mm/page.h>
+#include <mm/as.h>
+#include <config.h>
+#include <userspace.h>
+#include <console/console.h>
+#include <proc/uarg.h>
+#include <syscall/syscall.h>
+#include <ddi/irq.h>
+#include <ddi/device.h>
+#include <arch/bootinfo.h>
+#include <smp/smp.h>
+#include <smp/ipi.h>
+#include <arch/atomic.h>
+#include <panic.h>
+#include <print.h>
+#ifdef CONFIG_SMP
+extern char cpu_by_id_eid_list[256][256];
+static void sapic_init(void)
+{
+    bootinfo->sapic = (unative_t *)(PA2KA((unative_t)(bootinfo->sapic)) |
+        FW_OFFSET);
+}
+static void ipi_broadcast_arch_all(int ipi)
+{
+    int id, eid;
+    int myid, myeid;
+    myid = ia64_get_cpu_id();
+    myeid = ia64_get_cpu_eid();
+    for (id = 0; id < 256; id++)
+        for (eid = 0; eid < 256; eid++)
+            if ((id != myid) || (eid != myeid))
+                ipi_send_ipi(id, eid, ipi);
+}
+void ipi_broadcast_arch(int ipi )
+{
+    int id, eid;
+    int myid, myeid;
+    myid = ia64_get_cpu_id();
+    myeid = ia64_get_cpu_eid();
+    for (id = 0; id < 256; id++)
+        for (eid = 0; eid < 256; eid++)
+            if ((id != myid) || (eid != myeid))
+                if (cpu_by_id_eid_list[id][eid])
+                    ipi_send_ipi(id, eid, ipi);
+}
+void smp_init(void)
+{
+    if (!bootinfo->hello_configured)
+        return;
+    /*
+     * If we have not got system prepared by hello, we are not able to start
+     * AP's. This means we are running on a simulator.
+     */
+    sapic_init();
+    ipi_broadcast_arch_all(bootinfo->wakeup_intno);
+    volatile long long brk;
+        for (brk = 0; brk < 100LL * 1024LL * 1024LL; brk++)
+        ;   /* wait a while before CPUs starts */
+    config.cpu_count = 0;
+    int id, eid;
+    for (id = 0; id < 256; id++)
+        for (eid = 0; eid < 256; eid++)
+                if (cpu_by_id_eid_list[id][eid] == 1) {
+                    config.cpu_count++;
+                    cpu_by_id_eid_list[id][eid] = 2;
+            }
+}
+void kmp(void *arg __attribute__((unused)))
+{
+    int id, eid;
+    int myid, myeid;
+    myid = ia64_get_cpu_id();
+    myeid = ia64_get_cpu_eid();
+    for (id = 0; id < 256; id++)
+        for (eid = 0; eid < 256; eid++)
+                if ((id != myid) || (eid != myeid))
+                    if (cpu_by_id_eid_list[id][eid] != 0) {
+                        if (cpu_by_id_eid_list[id][eid] == 1) {
+                            printf("Found Late CPU ID:%d "
+                            "EDI:%d Not added to "
+                            "system!!!\n", id, eid);
+                            continue;
+                    }
+                    cpu_by_id_eid_list[id][eid] = 3;
+                    /*
+                     * There may be just one AP being
+                     * initialized at the time. After
+                     * it comes completely up, it is
+                     * supposed to wake us up.
+                     */
+                    if (waitq_sleep_timeout(
+                        &ap_completion_wq, 1000000,
+                        SYNCH_FLAGS_NONE) ==
+                        ESYNCH_TIMEOUT) {
+                        printf("%s: waiting for cpu "
+                            "ID:%d EID:%d timed out\n",
+                            __FUNCTION__, id, eid);
+                        }
+                }
+}
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/ia64/src/ddi/ddi.c
 ,5 → 1,6
 /*
  * Copyright (c) 2006 Jakub Jermar
+ * Copyright (c) 2008 Jakub vana
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,19 → 36,39
 #include <ddi/ddi.h>
 #include <proc/task.h>
 #include <arch/types.h>
+#include <mm/slab.h>
+#include <errno.h>
+#define IO_MEMMAP_PAGES 16384
+#define PORTS_PER_PAGE  4
 /** Enable I/O space range for task.
  *
  * Interrupts are disabled and task is locked.
  *
- * @param task Task.
- * @param ioaddr Startign I/O space address.
- * @param size Size of the enabled I/O range.
+ * @param task      Task.
+ * @param ioaddr    Starting I/O space address.
+ * @param size      Size of the enabled I/O range.
  *
  * @return 0 on success or an error code from errno.h.
  */
 int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
 {
+    if (!task->arch.iomap) {
+        uint8_t *map;
+        task->arch.iomap = malloc(sizeof(bitmap_t), 0);
+        map = malloc(BITS2BYTES(IO_MEMMAP_PAGES), 0);
+        if(!map)
+            return ENOMEM;
+        bitmap_initialize(task->arch.iomap, map, IO_MEMMAP_PAGES);
+        bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES);
+    }
+    uintptr_t iopage = ioaddr / PORTS_PER_PAGE;
+    size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE);
+    bitmap_set_range(task->arch.iomap, iopage, size / 4);
     return 0;
 }

 /branches/network/kernel/arch/ia64/src/asm.S
 ,7 → 51,7
     adds r14 = 7, in1
     mov r2 = ar.lc
-    mov r8 = in0
+    mov r8 = in0 ;;
     and r14 = -8, r14 ;;
     cmp.ne p6, p7 = r14, in1
 (p7)    br.cond.dpnt 3f ;;
 ,6 → 128,10
 memsetb:
     br _memsetb
+.global memsetw
+memsetw:
+    br _memsetw
 .global cpu_halt
 cpu_halt:
     br cpu_halt

 /branches/network/kernel/arch/ia64/src/proc/scheduler.c
 ,14 → 47,17
 {
 }
-/** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack is mapped in DTR. */
+/** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack
+ * is mapped in DTR.
+ */
 void before_thread_runs_arch(void)
 {
     uintptr_t base;
-    base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
+    base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
-    if ((uintptr_t) THREAD->kstack < base || (uintptr_t) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) {
+    if ((uintptr_t) THREAD->kstack < base ||
+        (uintptr_t) THREAD->kstack > base + (1 << (KERNEL_PAGE_WIDTH))) {
         /*
          * Kernel stack of this thread is not mapped by DTR[TR_KERNEL].
          * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
 ,8 → 67,11
         dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1);
         /* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
-        dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
-        dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
+        dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack,
+            KA2PA(THREAD->kstack), true, DTR_KSTACK1);
+        dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack +
+            PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true,
+            DTR_KSTACK2);
     }
     /*

 /branches/network/kernel/arch/ia64/src/ia64.c
 ,64 → 50,91
 #include <proc/uarg.h>
 #include <syscall/syscall.h>
 #include <ddi/irq.h>
-#include <ddi/device.h>
-#include <arch/drivers/ega.h>
 #include <arch/bootinfo.h>
-#include <genarch/kbd/i8042.h>
+#include <genarch/drivers/legacy/ia32/io.h>
+#include <genarch/drivers/ega/ega.h>
+#include <genarch/kbrd/kbrd.h>
+#include <genarch/srln/srln.h>
+#include <genarch/drivers/i8042/i8042.h>
+#include <genarch/drivers/ns16550/ns16550.h>
+#include <arch/drivers/kbd.h>
+#include <smp/smp.h>
+#include <smp/ipi.h>
+#include <arch/atomic.h>
+#include <panic.h>
+#include <print.h>
+#include <sysinfo/sysinfo.h>
+#include <string.h>
+/* NS16550 as a COM 1 */
+#define NS16550_IRQ  (4 + LEGACY_INTERRUPT_BASE)
 bootinfo_t *bootinfo;
+static uint64_t iosapic_base = 0xfec00000;
+/** Performs ia64-specific initialization before main_bsp() is called. */
 void arch_pre_main(void)
 {
     /* Setup usermode init tasks. */
-//#ifdef I460GX
     unsigned int i;
     init.cnt = bootinfo->taskmap.count;
     for (i = 0; i < init.cnt; i++) {
-        init.tasks[i].addr = ((unsigned long) bootinfo->taskmap.tasks[i].addr) | VRN_MASK;
+        init.tasks[i].addr =
+            ((unsigned long) bootinfo->taskmap.tasks[i].addr) |
+            VRN_MASK;
         init.tasks[i].size = bootinfo->taskmap.tasks[i].size;
+        strncpy(init.tasks[i].name, bootinfo->taskmap.tasks[i].name,
+            CONFIG_TASK_NAME_BUFLEN);
     }
-/*
-#else
-    init.cnt = 8;
-    init.tasks[0].addr = INIT0_ADDRESS;
-    init.tasks[0].size = INIT0_SIZE;
-    init.tasks[1].addr = INIT0_ADDRESS + 0x400000;
-    init.tasks[1].size = INIT0_SIZE;
-    init.tasks[2].addr = INIT0_ADDRESS + 0x800000;
-    init.tasks[2].size = INIT0_SIZE;
-    init.tasks[3].addr = INIT0_ADDRESS + 0xc00000;
-    init.tasks[3].size = INIT0_SIZE;
-    init.tasks[4].addr = INIT0_ADDRESS + 0x1000000;
-    init.tasks[4].size = INIT0_SIZE;
-    init.tasks[5].addr = INIT0_ADDRESS + 0x1400000;
-    init.tasks[5].size = INIT0_SIZE;
-    init.tasks[6].addr = INIT0_ADDRESS + 0x1800000;
-    init.tasks[6].size = INIT0_SIZE;
-    init.tasks[7].addr = INIT0_ADDRESS + 0x1c00000;
-    init.tasks[7].size = INIT0_SIZE;
-#endif*/
 }
 void arch_pre_mm_init(void)
 {
-    /* Set Interruption Vector Address (i.e. location of interruption vector table). */
+    /*
+     * Set Interruption Vector Address (i.e. location of interruption vector
+     * table).
+     */
     iva_write((uintptr_t) &ivt);
     srlz_d();
 }
+static void iosapic_init(void)
+{
+    uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET;
+    int i;
+    int myid, myeid;
+    myid = ia64_get_cpu_id();
+    myeid = ia64_get_cpu_eid();
+    for (i = 0; i < 16; i++) {
+        if (i == 2)
+            continue;    /* Disable Cascade interrupt */
+        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i;
+        srlz_d();
+        ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i;
+        srlz_d();
+        ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1;
+        srlz_d();
+        ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) |
+            myeid << (48 - 32);
+        srlz_d();
+    }
+}
 void arch_post_mm_init(void)
 {
-    irq_init(INR_COUNT, INR_COUNT);
-#ifdef SKI
-    ski_init_console();
-#else
-    ega_init();
-#endif
+    if (config.cpu_active == 1) {
+        iosapic_init();
+        irq_init(INR_COUNT, INR_COUNT);
+    }
     it_init();
 }
 ,51 → 146,55
 {
 }
-#ifdef I460GX
-#define POLL_INTERVAL       50000       /* 50 ms */
-/** Kernel thread for polling keyboard. */
-static void i8042_kkbdpoll(void *arg)
-{
-    while (1) {
-        i8042_poll();
-        thread_usleep(POLL_INTERVAL);
-    }
-}
-#endif
 void arch_post_smp_init(void)
 {
-    if (config.cpu_active == 1) {
-        /*
-         * Create thread that polls keyboard.
-         */
 #ifdef SKI
-        thread_t *t;
-        t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
-        if (!t)
-            panic("cannot create kkbdpoll\n");
-        thread_ready(t);
-#endif
-#ifdef I460GX
-        devno_t kbd = device_assign_devno();
-        devno_t mouse = device_assign_devno();
-        /* keyboard controller */
-        i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE);
-        thread_t *t;
-        t = thread_create(i8042_kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
-        if (!t)
-            panic("cannot create kkbdpoll\n");
-        thread_ready(t);
+    indev_t *in;
+    in = skiin_init();
+    if (in)
+        srln_init(in);
+    skiout_init();
 #endif
-    }
+#ifdef CONFIG_EGA
+    ega_init(EGA_BASE, EGA_VIDEORAM);
+#endif
+#ifdef CONFIG_NS16550
+    indev_t *kbrdin_ns16550
+        = ns16550_init((ns16550_t *) NS16550_BASE, NS16550_IRQ, NULL, NULL);
+    if (kbrdin_ns16550)
+        srln_init(kbrdin_ns16550);
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ);
+    sysinfo_set_item_val("kbd.type", NULL, KBD_NS16550);
+    sysinfo_set_item_val("kbd.address.physical", NULL,
+        (uintptr_t) NS16550_BASE);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) NS16550_BASE);
+#endif
+#ifdef CONFIG_I8042
+    indev_t *kbrdin_i8042 = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
+    if (kbrdin_i8042)
+        kbrd_init(kbrdin_i8042);
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
+    sysinfo_set_item_val("kbd.type", NULL, KBD_LEGACY);
+    sysinfo_set_item_val("kbd.address.physical", NULL,
+        (uintptr_t) I8042_BASE);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) I8042_BASE);
+#endif
+    sysinfo_set_item_val("ia64_iospace", NULL, true);
+    sysinfo_set_item_val("ia64_iospace.address", NULL, true);
+    sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET);
 }
 /** Enter userspace and never return. */
 void userspace(uspace_arg_t *kernel_uarg)
 {
 ,26 → 203,25
     psr.value = psr_read();
     psr.cpl = PL_USER;
-    psr.i = true;               /* start with interrupts enabled */
+    psr.i = true;           /* start with interrupts enabled */
     psr.ic = true;
-    psr.ri = 0;             /* start with instruction #0 */
-    psr.bn = 1;             /* start in bank 0 */
+    psr.ri = 0;         /* start with instruction #0 */
+    psr.bn = 1;         /* start in bank 0 */
     asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
     rsc.loadrs = 0;
     rsc.be = false;
     rsc.pl = PL_USER;
-    rsc.mode = 3;               /* eager mode */
+    rsc.mode = 3;           /* eager mode */
     switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
-                ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
-                ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE,
-                (uintptr_t) kernel_uarg->uspace_uarg,
-                psr.value, rsc.value);
+        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE -
+        ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
+        ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE,
+        (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
-    while (1) {
+    while (1)
         ;
-    }
 }
 /** Set thread-local-storage pointer.
 ,8 → 240,9
 {
 #ifdef SKI
     ski_kbd_grab();
-#endif
+#endif
 }
 /** Return console to userspace
  *
  */
 ,9 → 255,27
 void arch_reboot(void)
 {
-    // TODO
-    while (1);
+    pio_write_8((ioport8_t *)0x64, 0xfe);
+    while (1)
+        ;
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    fptr->fnc = (unative_t) addr;
+    fptr->gp = ((unative_t *) caller)[1];
+    return (void *) fptr;
+}
 /** @}
  */

 /branches/network/kernel/arch/ia64/src/ski/ski.c
 ,29 → 35,19
 #include <arch/ski/ski.h>
 #include <console/console.h>
 #include <console/chardev.h>
-#include <arch/interrupt.h>
 #include <sysinfo/sysinfo.h>
 #include <arch/types.h>
-#include <ddi/device.h>
-#include <ddi/irq.h>
-#include <ipc/irq.h>
 #include <proc/thread.h>
 #include <synch/spinlock.h>
 #include <arch/asm.h>
+#include <arch/drivers/kbd.h>
+#include <arch.h>
-#define SKI_KBD_INR 0
+static indev_t skiin;       /**< Ski input device. */
+static outdev_t skiout;     /**< Ski output device. */
-static irq_t ski_kbd_irq;
-static devno_t ski_kbd_devno;
-chardev_t ski_console;
-chardev_t ski_uconsole;
 static bool kbd_disabled;
-static void ski_putchar(chardev_t *d, const char ch);
-static int32_t ski_getchar(void);
 /** Display character on debug console
  *
  * Use SSC (Simulator System Call) to
 ,21 → 56,31
  * @param d Character device.
  * @param ch Character to be printed.
  */
-void ski_putchar(chardev_t *d, const char ch)
+static void ski_putchar(outdev_t *d, const char ch, bool silent)
 {
-    asm volatile (
-        "mov r15 = %0\n"
-        "mov r32 = %1\n"    /* r32 is in0 */
-        "break 0x80000\n"   /* modifies r8 */
-        :
-        : "i" (SKI_PUTCHAR), "r" (ch)
-        : "r15", "in0", "r8"
-    );
-    if (ch == '\n')
-        ski_putchar(d, '\r');
+    if (!silent) {
+        asm volatile (
+            "mov r15 = %0\n"
+            "mov r32 = %1\n"   /* r32 is in0 */
+            "break 0x80000\n"  /* modifies r8 */
+            :
+            : "i" (SKI_PUTCHAR), "r" (ch)
+            : "r15", "in0", "r8"
+        );
+        if (ch == '\n')
+            ski_putchar(d, '\r', false);
+    }
 }
+static indev_operations_t skiin_ops = {
+    .poll = NULL
+};
+static outdev_operations_t skiout_ops = {
+    .write = ski_putchar
+};
 /** Ask debug console if a key was pressed.
  *
  * Use SSC (Simulator System Call) to
 ,7 → 90,7
  *
  * @return ASCII code of pressed key or 0 if no key pressed.
  */
-int32_t ski_getchar(void)
+static int32_t ski_getchar(void)
 {
     uint64_t ch;
 ,102 → 107,47
     return (int32_t) ch;
 }
-/**
- * This is a blocking wrapper for ski_getchar().
- * To be used when the kernel crashes.
- */
-static char ski_getchar_blocking(chardev_t *d)
-{
-    int ch;
-    while(!(ch = ski_getchar()))
-        ;
-    if(ch == '\r')
-        ch = '\n';
-    return (char) ch;
-}
 /** Ask keyboard if a key was pressed. */
 static void poll_keyboard(void)
 {
     char ch;
-    static char last;
-    ipl_t ipl;
-    ipl = interrupts_disable();
-    if (kbd_disabled) {
-        interrupts_restore(ipl);
+    if (kbd_disabled)
         return;
-    }
-    spinlock_lock(&ski_kbd_irq.lock);
     ch = ski_getchar();
     if(ch == '\r')
         ch = '\n';
     if (ch) {
-        if (ski_kbd_irq.notif_cfg.notify && ski_kbd_irq.notif_cfg.answerbox) {
-            chardev_push_character(&ski_uconsole, ch);
-            ipc_irq_send_notif(&ski_kbd_irq);
-        } else {
-            chardev_push_character(&ski_console, ch);
-        }
-        last = ch;
-        spinlock_unlock(&ski_kbd_irq.lock);
-        interrupts_restore(ipl);
+        indev_push_character(&skiin, ch);
         return;
     }
-    if (last) {
-        if (ski_kbd_irq.notif_cfg.notify && ski_kbd_irq.notif_cfg.answerbox) {
-            chardev_push_character(&ski_uconsole, 0);
-            ipc_irq_send_notif(&ski_kbd_irq);
-        }
-        last = 0;
-    }
-    spinlock_unlock(&ski_kbd_irq.lock);
-    interrupts_restore(ipl);
 }
-/* Called from getc(). */
-static void ski_kbd_enable(chardev_t *d)
-{
-    kbd_disabled = false;
-}
+#define POLL_INTERVAL           10000           /* 10 ms */
-/* Called from getc(). */
-static void ski_kbd_disable(chardev_t *d)
+/** Kernel thread for polling keyboard. */
+static void kkbdpoll(void *arg)
 {
-    kbd_disabled = true;
+    while (1) {
+        if (!silent) {
+            poll_keyboard();
+        }
+        thread_usleep(POLL_INTERVAL);
+    }
 }
-/** Decline to service hardware IRQ.
- *
- * This is only a virtual IRQ, so always decline.
- *
- * @return Always IRQ_DECLINE.
- */
-static irq_ownership_t ski_kbd_claim(void)
-{
-    return IRQ_DECLINE;
-}
-static chardev_operations_t ski_ops = {
-    .resume = ski_kbd_enable,
-    .suspend = ski_kbd_disable,
-    .write = ski_putchar,
-    .read = ski_getchar_blocking
-};
 /** Initialize debug console
  *
  * Issue SSC (Simulator System Call) to
  * to open debug console.
  */
-void ski_init_console(void)
+static void ski_init(void)
 {
+    static bool initialized;
+    if (initialized)
+        return;
     asm volatile (
         "mov r15 = %0\n"
         "break 0x80000\n"
 ,54 → 155,46
         : "i" (SKI_INIT_CONSOLE)
         : "r15", "r8"
     );
+    initialized = true;
+}
-    chardev_initialize("ski_console", &ski_console, &ski_ops);
-    chardev_initialize("ski_uconsole", &ski_uconsole, &ski_ops);
-    stdin = &ski_console;
-    stdout = &ski_console;
+indev_t *skiin_init(void)
+{
+    ski_init();
-    ski_kbd_devno = device_assign_devno();
-    irq_initialize(&ski_kbd_irq);
-    ski_kbd_irq.inr = SKI_KBD_INR;
-    ski_kbd_irq.devno = ski_kbd_devno;
-    ski_kbd_irq.claim = ski_kbd_claim;
-    irq_register(&ski_kbd_irq);
+    indev_initialize("skiin", &skiin, &skiin_ops);
+    thread_t *t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
+    if (t)
+        thread_ready(t);
+    else
+        return NULL;
     sysinfo_set_item_val("kbd", NULL, true);
-    sysinfo_set_item_val("kbd.inr", NULL, SKI_KBD_INR);
-    sysinfo_set_item_val("kbd.devno", NULL, ski_kbd_devno);
+    sysinfo_set_item_val("kbd.type", NULL, KBD_SKI);
+    return &skiin;
 }
-void ski_kbd_grab(void)
+void skiout_init(void)
 {
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&ski_kbd_irq.lock);
-    ski_kbd_irq.notif_cfg.notify = false;
-    spinlock_unlock(&ski_kbd_irq.lock);
-    interrupts_restore(ipl);
+    ski_init();
+    outdev_initialize("skiout", &skiout, &skiout_ops);
+    stdout = &skiout;
+    sysinfo_set_item_val("fb", NULL, false);
 }
-void ski_kbd_release(void)
+void ski_kbd_grab(void)
 {
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&ski_kbd_irq.lock);
-    if (ski_kbd_irq.notif_cfg.answerbox)
-        ski_kbd_irq.notif_cfg.notify = true;
-    spinlock_unlock(&ski_kbd_irq.lock);
-    interrupts_restore(ipl);
+    kbd_disabled = true;
 }
-#define POLL_INTERVAL       50000       /* 50 ms */
-/** Kernel thread for polling keyboard. */
-void kkbdpoll(void *arg)
+void ski_kbd_release(void)
 {
-    while (1) {
-        poll_keyboard();
-        thread_usleep(POLL_INTERVAL);
-    }
+    kbd_disabled = false;
 }
 /** @}

 /branches/network/kernel/arch/ia64/src/cpu/cpu.c
 ,8 → 70,8
     }
     printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id,
-        family_str, vendor, CPU->arch.cpuid3.archrev, CPU->arch.cpuid3.model,
-        CPU->arch.cpuid3.revision);
+        family_str, vendor, CPU->arch.cpuid3.archrev,
+        CPU->arch.cpuid3.model, CPU->arch.cpuid3.revision);
 }
 /** @}

 /branches/network/kernel/arch/ia64/src/mm/tlb.c
 ,7 → 92,7
 /** Invalidate entries belonging to an address space.
  *
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
  */
 void tlb_invalidate_asid(asid_t asid)
 {
 ,59 → 131,45
     uint64_t ps;
     switch (b) {
-    case 0: /*cnt 1-3*/
+    case 0: /* cnt 1 - 3 */
         ps = PAGE_WIDTH;
         break;
-    case 1: /*cnt 4-15*/
-        /*cnt=((cnt-1)/4)+1;*/
-        ps = PAGE_WIDTH+2;
-        va &= ~((1<<ps)-1);
+    case 1: /* cnt 4 - 15 */
+        ps = PAGE_WIDTH + 2;
+        va &= ~((1 << ps) - 1);
         break;
-    case 2: /*cnt 16-63*/
-        /*cnt=((cnt-1)/16)+1;*/
-        ps = PAGE_WIDTH+4;
-        va &= ~((1<<ps)-1);
+    case 2: /* cnt 16 - 63 */
+        ps = PAGE_WIDTH + 4;
+        va &= ~((1 << ps) - 1);
         break;
-    case 3: /*cnt 64-255*/
-        /*cnt=((cnt-1)/64)+1;*/
-        ps = PAGE_WIDTH+6;
-        va &= ~((1<<ps)-1);
+    case 3: /* cnt 64 - 255 */
+        ps = PAGE_WIDTH + 6;
+        va &= ~((1 << ps) - 1);
         break;
-    case 4: /*cnt 256-1023*/
-        /*cnt=((cnt-1)/256)+1;*/
-        ps = PAGE_WIDTH+8;
-        va &= ~((1<<ps)-1);
+    case 4: /* cnt 256 - 1023 */
+        ps = PAGE_WIDTH + 8;
+        va &= ~((1 << ps) - 1);
         break;
-    case 5: /*cnt 1024-4095*/
-        /*cnt=((cnt-1)/1024)+1;*/
-        ps = PAGE_WIDTH+10;
-        va &= ~((1<<ps)-1);
+    case 5: /* cnt 1024 - 4095 */
+        ps = PAGE_WIDTH + 10;
+        va &= ~((1 << ps) - 1);
         break;
-    case 6: /*cnt 4096-16383*/
-        /*cnt=((cnt-1)/4096)+1;*/
-        ps = PAGE_WIDTH+12;
-        va &= ~((1<<ps)-1);
+    case 6: /* cnt 4096 - 16383 */
+        ps = PAGE_WIDTH + 12;
+        va &= ~((1 << ps) - 1);
         break;
-    case 7: /*cnt 16384-65535*/
-    case 8: /*cnt 65536-(256K-1)*/
-        /*cnt=((cnt-1)/16384)+1;*/
-        ps = PAGE_WIDTH+14;
-        va &= ~((1<<ps)-1);
+    case 7: /* cnt 16384 - 65535 */
+    case 8: /* cnt 65536 - (256K - 1) */
+        ps = PAGE_WIDTH + 14;
+        va &= ~((1 << ps) - 1);
         break;
     default:
-        /*cnt=((cnt-1)/(16384*16))+1;*/
-        ps=PAGE_WIDTH+18;
-        va&=~((1<<ps)-1);
+        ps = PAGE_WIDTH + 18;
+        va &= ~((1 << ps) - 1);
         break;
     }
-    /*cnt+=(page!=va);*/
-    for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
-        asm volatile (
-            "ptc.l %0,%1;;"
-            :
-            : "r" (va), "r" (ps<<2)
-        );
-    }
+    for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
+        asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
     srlz_d();
     srlz_i();
 ,9 → 182,10
 /** Insert data into data translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
  */
 void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
 {
 ,9 → 194,10
 /** Insert data into instruction translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
  */
 void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
 {
 ,10 → 206,12
 /** Insert data into instruction or data translation cache.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
+ * @param dtc       If true, insert into data translation cache, use
+ *          instruction translation cache otherwise.
  */
 void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
 {
 ,19 → 234,20
     }
     asm volatile (
-        "mov r8=psr;;\n"
+        "mov r8 = psr;;\n"
         "rsm %0;;\n"            /* PSR_IC_MASK */
         "srlz.d;;\n"
         "srlz.i;;\n"
-        "mov cr.ifa=%1\n"       /* va */
-        "mov cr.itir=%2;;\n"        /* entry.word[1] */
-        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
+        "mov cr.ifa = %1\n"     /* va */
+        "mov cr.itir = %2;;\n"      /* entry.word[1] */
+        "cmp.eq p6,p7 = %4,r0;;\n"  /* decide between itc and dtc */
         "(p6) itc.i %3;;\n"
         "(p7) itc.d %3;;\n"
-        "mov psr.l=r8;;\n"
+        "mov psr.l = r8;;\n"
         "srlz.d;;\n"
         :
-        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
+        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+            "r" (entry.word[0]), "r" (dtc)
         : "p6", "p7", "r8"
     );
 ,12 → 260,14
 /** Insert data into instruction translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param tr Translation register.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
+ * @param tr        Translation register.
  */
-void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+void
+itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
     tr_mapping_insert(va, asid, entry, false, tr);
 }
 ,12 → 274,14
 /** Insert data into data translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param tr Translation register.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
+ * @param tr        Translation register.
  */
-void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+void
+dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
 {
     tr_mapping_insert(va, asid, entry, true, tr);
 }
 ,13 → 288,17
 /** Insert data into instruction or data translation register.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
- * @param dtr If true, insert into data translation register, use instruction translation register otherwise.
- * @param tr Translation register.
+ * @param va        Virtual page address.
+ * @param asid      Address space identifier.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
+ * @param dtr       If true, insert into data translation register, use
+ *          instruction translation register otherwise.
+ * @param tr        Translation register.
  */
-void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
+void
+tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
+    index_t tr)
 {
     region_register rr;
     bool restore_rr = false;
 ,19 → 319,20
     }
     asm volatile (
-        "mov r8=psr;;\n"
+        "mov r8 = psr;;\n"
         "rsm %0;;\n"            /* PSR_IC_MASK */
         "srlz.d;;\n"
         "srlz.i;;\n"
-        "mov cr.ifa=%1\n"           /* va */
-        "mov cr.itir=%2;;\n"        /* entry.word[1] */
-        "cmp.eq p6,p7=%5,r0;;\n"    /* decide between itr and dtr */
-        "(p6) itr.i itr[%4]=%3;;\n"
-        "(p7) itr.d dtr[%4]=%3;;\n"
-        "mov psr.l=r8;;\n"
+        "mov cr.ifa = %1\n"         /* va */
+        "mov cr.itir = %2;;\n"      /* entry.word[1] */
+        "cmp.eq p6,p7 = %5,r0;;\n"  /* decide between itr and dtr */
+        "(p6) itr.i itr[%4] = %3;;\n"
+        "(p7) itr.d dtr[%4] = %3;;\n"
+        "mov psr.l = r8;;\n"
         "srlz.d;;\n"
         :
-        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
+        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+            "r" (entry.word[0]), "r" (tr), "r" (dtr)
         : "p6", "p7", "r8"
     );
 ,12 → 345,15
 /** Insert data into DTLB.
  *
- * @param page Virtual page address including VRN bits.
- * @param frame Physical frame address.
- * @param dtr If true, insert into data translation register, use data translation cache otherwise.
- * @param tr Translation register if dtr is true, ignored otherwise.
+ * @param page      Virtual page address including VRN bits.
+ * @param frame     Physical frame address.
+ * @param dtr       If true, insert into data translation register, use data
+ *          translation cache otherwise.
+ * @param tr        Translation register if dtr is true, ignored otherwise.
  */
-void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
+void
+dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
+    index_t tr)
 {
     tlb_entry_t entry;
 ,18 → 379,18
  *
  * Purge DTR entries used by the kernel.
  *
- * @param page Virtual page address including VRN bits.
- * @param width Width of the purge in bits.
+ * @param page      Virtual page address including VRN bits.
+ * @param width     Width of the purge in bits.
  */
 void dtr_purge(uintptr_t page, count_t width)
 {
-    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
+    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
 }
 /** Copy content of PTE into data translation cache.
  *
- * @param t PTE.
+ * @param t     PTE.
  */
 void dtc_pte_copy(pte_t *t)
 {
 ,7 → 416,7
 /** Copy content of PTE into instruction translation cache.
  *
- * @param t PTE.
+ * @param t     PTE.
  */
 void itc_pte_copy(pte_t *t)
 {
 ,8 → 443,8
 /** Instruction TLB fault handler for faults with VHPT turned off.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector        Interruption vector.
+ * @param istate        Structure with saved interruption state.
  */
 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
 {
 ,16 → 472,77
          */
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            fault_if_from_uspace(istate,"Page fault at %p.",va);
+            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
+                istate->cr_iip);
         }
     }
 }
+static int is_io_page_accessible(int page)
+{
+    if (TASK->arch.iomap)
+        return bitmap_get(TASK->arch.iomap, page);
+    else
+        return 0;
+}
+#define IO_FRAME_BASE 0xFFFFC000000
+/**
+ * There is special handling of memory mapped legacy io, because of 4KB sized
+ * access for userspace.
+ *
+ * @param va        Virtual address of page fault.
+ * @param istate    Structure with saved interruption state.
+ *
+ * @return      One on success, zero on failure.
+ */
+static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
+{
+    if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) {
+        if (TASK) {
+            uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
+                USPACE_IO_PAGE_WIDTH;
+            if (is_io_page_accessible(io_page)) {
+                uint64_t page, frame;
+                page = IO_OFFSET +
+                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+                frame = IO_FRAME_BASE +
+                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+                tlb_entry_t entry;
+                entry.word[0] = 0;
+                entry.word[1] = 0;
+                entry.p = true;     /* present */
+                entry.ma = MA_UNCACHEABLE;
+                entry.a = true;     /* already accessed */
+                entry.d = true;     /* already dirty */
+                entry.pl = PL_USER;
+                entry.ar = AR_READ | AR_WRITE;
+                entry.ppn = frame >> PPN_SHIFT;
+                entry.ps = USPACE_IO_PAGE_WIDTH;
+                dtc_mapping_insert(page, TASK->as->asid, entry);
+                return 1;
+            } else {
+                fault_if_from_uspace(istate,
+                    "IO access fault at %p.", va);
+            }
+        }
+    }
+    return 0;
+}
 /** Data TLB fault handler for faults with VHPT turned off.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector    Interruption vector.
+ * @param istate    Structure with saved interruption state.
  */
 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
 {
 ,13 → 575,17
         dtc_pte_copy(t);
         page_table_unlock(AS, true);
     } else {
+        page_table_unlock(AS, true);
+        if (try_memmap_io_insertion(va, istate))
+            return;
         /*
-         * Forward the page fault to the address space page fault handler.
+         * Forward the page fault to the address space page fault
+         * handler.
          */
-        page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            fault_if_from_uspace(istate,"Page fault at %p.",va);
+            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
+                istate->cr_iip);
         }
     }
 }
 ,18 → 594,18
  *
  * This fault should not occur.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector    Interruption vector.
+ * @param istate    Structure with saved interruption state.
  */
 void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
 {
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Data Dirty bit fault handler.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector    Interruption vector.
+ * @param istate    Structure with saved interruption state.
  */
 void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
 {
 ,10 → 630,9
         dtc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-            t->d = true;
-            dtc_pte_copy(t);
+            fault_if_from_uspace(istate,"Page fault at %p.",va);
+            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
+                istate->cr_iip);
         }
     }
     page_table_unlock(AS, true);
 ,8 → 640,8
 /** Instruction access bit fault handler.
  *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param vector    Interruption vector.
+ * @param istate    Structure with saved interruption state.
  */
 void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
 {
 ,10 → 666,9
         itc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-            t->a = true;
-            itc_pte_copy(t);
+            fault_if_from_uspace(istate, "Page fault at %p.", va);
+            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
+                istate->cr_iip);
         }
     }
     page_table_unlock(AS, true);
 ,10 → 702,9
         dtc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
-            t->a = true;
-            itc_pte_copy(t);
+            fault_if_from_uspace(istate, "Page fault at %p.", va);
+            panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
+                istate->cr_iip);
         }
     }
     page_table_unlock(AS, true);
 ,11 → 743,19
     } else {
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d\n", __func__, va, rid);
+            fault_if_from_uspace(istate, "Page fault at %p.", va);
+            panic("%s: va=%p, rid=%d.", __func__, va, rid);
         }
     }
 }
+void tlb_arch_init(void)
+{
+}
+void tlb_print(void)
+{
+}
 /** @}
  */

 /branches/network/kernel/arch/ia64/src/mm/vhpt.c
 ,7 → 41,8
 uintptr_t vhpt_set_up(void)
 {
-    vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH, FRAME_KA | FRAME_ATOMIC);
+    vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
+        FRAME_KA | FRAME_ATOMIC);
     if (!vhpt_base)
         panic("Kernel configured with VHPT but no memory for table.");
     vhpt_invalidate_all();

 /branches/network/kernel/arch/ia64/src/mm/as.c
 ,7 → 68,7
             continue;
         rr.word = rr_read(i);
-        rr.map.ve = false;          /* disable VHPT walker */
+        rr.map.ve = false;      /* disable VHPT walker */
         rr.map.rid = ASID2RID(as->asid, i);
         rr.map.ps = PAGE_WIDTH;
         rr_write(i, rr.word);

 /branches/network/kernel/arch/ia64/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia64mm
+/** @addtogroup ia64mm
  * @{
  */
 /** @file
 ,26 → 36,55
 #include <mm/frame.h>
 #include <config.h>
 #include <panic.h>
+#include <arch/bootinfo.h>
+#include <align.h>
+#include <macros.h>
-/*
- * This is Ski-specific and certainly not sufficient
- * for real ia64 systems that provide memory map.
- */
-#define MEMORY_SIZE (64 * 1024 * 1024)
-#define MEMORY_BASE (64 * 1024 * 1024)
+#define KERNEL_RESERVED_AREA_BASE   (0x4400000)
+#define KERNEL_RESERVED_AREA_SIZE   (16 * 1024 * 1024)
-#define ROM_BASE    0xa0000               //For ski
-#define ROM_SIZE    (384 * 1024)          //For ski
-void poke_char(int x,int y,char ch, char c);
+#define ROM_BASE    0xa0000               /* for simulators */
+#define ROM_SIZE    (384 * 1024)          /* for simulators */
+#define MIN_ZONE_SIZE   (64 * 1024)
+#define MINCONF 1
+uintptr_t last_frame = 0;
 void frame_arch_init(void)
 {
-    zone_create(MEMORY_BASE >> FRAME_WIDTH, SIZE2FRAMES(MEMORY_SIZE), (MEMORY_SIZE) >> FRAME_WIDTH, 0);
-    /*
-     * Blacklist ROM regions.
-     */
-    frame_mark_unavailable(ADDR2PFN(ROM_BASE), SIZE2FRAMES(ROM_SIZE));
+    if (config.cpu_active == 1) {
+        unsigned int i;
+        for (i = 0; i < bootinfo->memmap_items; i++) {
+            if (bootinfo->memmap[i].type == EFI_MEMMAP_FREE_MEM) {
+                uint64_t base = bootinfo->memmap[i].base;
+                uint64_t size = bootinfo->memmap[i].size;
+                uint64_t abase = ALIGN_UP(base, FRAME_SIZE);
+                if (size > FRAME_SIZE)
+                    size -= abase - base;
+                if (size > MIN_ZONE_SIZE) {
+                    zone_create(abase >> FRAME_WIDTH,
+                        size >> FRAME_WIDTH,
+                        max(MINCONF, abase >> FRAME_WIDTH),
+);
+                }
+                if (abase + size > last_frame)
+                    last_frame = abase + size;
+            }
+        }
+        /*
+         * Blacklist ROM regions.
+         */
+        frame_mark_unavailable(ADDR2PFN(ROM_BASE),
+            SIZE2FRAMES(ROM_SIZE));
+        frame_mark_unavailable(ADDR2PFN(KERNEL_RESERVED_AREA_BASE),
+            SIZE2FRAMES(KERNEL_RESERVED_AREA_SIZE));
+    }
 }
 /** @}

 /branches/network/kernel/arch/ia64/src/mm/page.c
 ,7 → 27,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia64mm
+/** @addtogroup ia64mm
  * @{
  */
 /** @file
 ,6 → 47,7
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <memstr.h>
+#include <align.h>
 static void set_environment(void);
 ,9 → 63,9
 void set_environment(void)
 {
     region_register rr;
-    pta_register pta;
+    pta_register pta;
     int i;
-#ifdef CONFIG_VHPT
+#ifdef CONFIG_VHPT
     uintptr_t vhpt_base;
 #endif
 ,10 → 123,10
  *
  * Interrupts must be disabled.
  *
- * @param page Address of virtual page including VRN bits.
- * @param asid Address space identifier.
+ * @param page      Address of virtual page including VRN bits.
+ * @param asid      Address space identifier.
  *
- * @return VHPT entry address.
+ * @return      VHPT entry address.
  */
 vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
 {
 ,10 → 167,11
  *
  * Interrupts must be disabled.
  *
- * @param page Address of virtual page including VRN bits.
- * @param asid Address space identifier.
+ * @param page      Address of virtual page including VRN bits.
+ * @param asid      Address space identifier.
  *
- * @return True if page and asid match the page and asid of t, false otherwise.
+ * @return      True if page and asid match the page and asid of t,
+ *          false otherwise.
  */
 bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
 {
 ,12 → 212,15
 /** Set up one VHPT entry.
  *
  * @param v VHPT entry to be set up.
- * @param page Virtual address of the page mapped by the entry.
- * @param asid Address space identifier of the address space to which page belongs.
- * @param frame Physical address of the frame to wich page is mapped.
- * @param flags Different flags for the mapping.
+ * @param page      Virtual address of the page mapped by the entry.
+ * @param asid      Address space identifier of the address space to which
+ *          page belongs.
+ * @param frame     Physical address of the frame to wich page is mapped.
+ * @param flags     Different flags for the mapping.
  */
-void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags)
+void
+vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame,
+    int flags)
 {
     region_register rr_save, rr;
     index_t vrn;
 ,7 → 254,8
     v->word[3] = 0;
     v->present.p = true;
-    v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
+    v->present.ma = (flags & PAGE_CACHEABLE) ?
+        MA_WRITEBACK : MA_UNCACHEABLE;
     v->present.a = false;   /* not accessed */
     v->present.d = false;   /* not dirty */
     v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
 ,5 → 268,11
     v->present.tag.tag_word = tag;
 }
+uintptr_t hw_map(uintptr_t physaddr, size_t size __attribute__ ((unused)))
+{
+    /* THIS is a dirty hack. */
+    return (uintptr_t)((uint64_t)(PA2KA(physaddr)) + VIO_OFFSET);
+}
 /** @}
  */

 /branches/network/kernel/arch/ia64/src/interrupt.c
 ,7 → 38,6
 #include <ddi/irq.h>
 #include <panic.h>
 #include <print.h>
-#include <symtab.h>
 #include <debug.h>
 #include <console/console.h>
 #include <arch/types.h>
 ,6 → 52,8
 #include <ipc/irq.h>
 #include <ipc/ipc.h>
 #include <synch/spinlock.h>
+#include <mm/tlb.h>
+#include <symtab.h>
 #define VECTORS_64_BUNDLE   20
 #define VECTORS_16_BUNDLE   48
 ,9 → 137,9
 {
     char *ifa, *iipa, *iip;
-    ifa = get_symtab_entry(istate->cr_ifa);
-    iipa = get_symtab_entry(istate->cr_iipa);
-    iip = get_symtab_entry(istate->cr_iip);
+    ifa = symtab_fmt_name_lookup(istate->cr_ifa);
+    iipa = symtab_fmt_name_lookup(istate->cr_iipa);
+    iip = symtab_fmt_name_lookup(istate->cr_iip);
     putchar('\n');
     printf("Interrupted context dump:\n");
 ,21 → 186,21
         break;
     }
-    fault_if_from_uspace(istate, "General Exception (%s)", desc);
+    fault_if_from_uspace(istate, "General Exception (%s).", desc);
     dump_interrupted_context(istate);
-    panic("General Exception (%s)\n", desc);
+    panic("General Exception (%s).", desc);
 }
 void disabled_fp_register(uint64_t vector, istate_t *istate)
 {
-#ifdef CONFIG_FPU_LAZY
-    scheduler_fpu_lazy_request();
+#ifdef CONFIG_FPU_LAZY
+    scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "Interruption: %#hx (%s)",
+    fault_if_from_uspace(istate, "Interruption: %#hx (%s).",
         (uint16_t) vector, vector_to_string(vector));
     dump_interrupted_context(istate);
-    panic("Interruption: %#hx (%s)\n", (uint16_t) vector,
+    panic("Interruption: %#hx (%s).", (uint16_t) vector,
         vector_to_string(vector));
 #endif
 }
 ,40 → 228,82
 void universal_handler(uint64_t vector, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "Interruption: %#hx (%s)\n",
+    fault_if_from_uspace(istate, "Interruption: %#hx (%s).",
         (uint16_t) vector, vector_to_string(vector));
     dump_interrupted_context(istate);
-    panic("Interruption: %#hx (%s)\n", (uint16_t) vector,
+    panic("Interruption: %#hx (%s).", (uint16_t) vector,
         vector_to_string(vector));
 }
+static void end_of_local_irq(void)
+{
+    asm volatile ("mov cr.eoi=r0;;");
+}
 void external_interrupt(uint64_t vector, istate_t *istate)
 {
+    cr_ivr_t ivr;
     irq_t *irq;
-    cr_ivr_t ivr;
     ivr.value = ivr_read();
     srlz_d();
-    irq = irq_dispatch_and_lock(ivr.vector);
-    if (irq) {
-        irq->handler(irq, irq->arg);
-        spinlock_unlock(&irq->lock);
-    } else {
-        switch (ivr.vector) {
-        case INTERRUPT_SPURIOUS:
+    switch (ivr.vector) {
+    case INTERRUPT_SPURIOUS:
 #ifdef CONFIG_DEBUG
-            printf("cpu%d: spurious interrupt\n", CPU->id);
+        printf("cpu%d: spurious interrupt\n", CPU->id);
 #endif
-            break;
+        break;
-        default:
-            panic("\nUnhandled External Interrupt Vector %d\n",
+#ifdef CONFIG_SMP
+    case VECTOR_TLB_SHOOTDOWN_IPI:
+        tlb_shootdown_ipi_recv();
+        end_of_local_irq();
+        break;
+#endif
+    case INTERRUPT_TIMER:
+        irq = irq_dispatch_and_lock(ivr.vector);
+        if (irq) {
+            irq->handler(irq);
+            spinlock_unlock(&irq->lock);
+        } else {
+            panic("Unhandled Internal Timer Interrupt (%d).",
                 ivr.vector);
-            break;
         }
+        break;
+    default:
+        irq = irq_dispatch_and_lock(ivr.vector);
+        if (irq) {
+            /*
+             * The IRQ handler was found.
+             */
+            if (irq->preack) {
+                /* Send EOI before processing the interrupt */
+                end_of_local_irq();
+            }
+            irq->handler(irq);
+            if (!irq->preack)
+                end_of_local_irq();
+            spinlock_unlock(&irq->lock);
+        } else {
+            /*
+             * Unhandled interrupt.
+             */
+            end_of_local_irq();
+#ifdef CONFIG_DEBUG
+            printf("\nUnhandled External Interrupt Vector %d\n",
+                ivr.vector);
+#endif
+        }
+        break;
     }
 }
+void trap_virtual_enable_irqs(uint16_t irqmask)
+{
+}
 /** @}
  */

 /branches/network/kernel/arch/ia64/src/drivers/it.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia64
+/** @addtogroup ia64
  * @{
  */
 /** @file
 ,25 → 44,44
 #include <ddi/device.h>
 #include <arch.h>
-#define IT_SERVICE_CLOCKS 64
+#define IT_SERVICE_CLOCKS   64
+#define FREQ_NUMERATOR_SHIFT    32
+#define FREQ_NUMERATOR_MASK 0xffffffff00000000ULL
+#define FREQ_DENOMINATOR_SHIFT  0
+#define FREQ_DENOMINATOR_MASK   0xffffffffULL
+uint64_t it_delta;
 static irq_t it_irq;
-static irq_ownership_t it_claim(void);
-static void it_interrupt(irq_t *irq, void *arg, ...);
+static irq_ownership_t it_claim(irq_t *);
+static void it_interrupt(irq_t *);
 /** Initialize Interval Timer. */
 void it_init(void)
 {
     cr_itv_t itv;
-    irq_initialize(&it_irq);
-    it_irq.inr = INTERRUPT_TIMER;
-    it_irq.devno = device_assign_devno();
-    it_irq.claim = it_claim;
-    it_irq.handler = it_interrupt;
-    irq_register(&it_irq);
+    if (config.cpu_active == 1) {
+        irq_initialize(&it_irq);
+        it_irq.inr = INTERRUPT_TIMER;
+        it_irq.devno = device_assign_devno();
+        it_irq.claim = it_claim;
+        it_irq.handler = it_interrupt;
+        irq_register(&it_irq);
+        uint64_t base_freq;
+        base_freq  = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >>
+            FREQ_NUMERATOR_SHIFT;
+        base_freq *= bootinfo->sys_freq;
+        base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >>
+            FREQ_DENOMINATOR_SHIFT;
+        it_delta = base_freq / HZ;
+    }
     /* initialize Interval Timer external interrupt vector */
     itv.value = itv_read();
     itv.vector = INTERRUPT_TIMER;
 ,13 → 104,13
  *
  * @return Always IRQ_ACCEPT.
  */
-irq_ownership_t it_claim(void)
+irq_ownership_t it_claim(irq_t *irq)
 {
     return IRQ_ACCEPT;
 }
 /** Process Interval Timer interrupt. */
-void it_interrupt(irq_t *irq, void *arg, ...)
+void it_interrupt(irq_t *irq)
 {
     int64_t c;
     int64_t m;

 /branches/network/kernel/arch/ia64/src/start.S
 ,19 → 32,15
 #include <mm/asid.h>
 #define RR_MASK (0xFFFFFFFF00000002)
-#define RID_SHIFT 8
-#define PS_SHIFT 2
+#define RID_SHIFT   8
+#define PS_SHIFT    2
-#define KERNEL_TRANSLATION_I  0x0010000000000661
-#define KERNEL_TRANSLATION_D  0x0010000000000661
-#define KERNEL_TRANSLATION_VIO 0x0010000000000671
-#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
-#define VIO_OFFSET            0x0002000000000000
+#define KERNEL_TRANSLATION_I    0x0010000000000661
+#define KERNEL_TRANSLATION_D    0x0010000000000661
+#define KERNEL_TRANSLATION_VIO  0x0010000000000671
+#define KERNEL_TRANSLATION_IO   0x00100FFFFC000671
+#define KERNEL_TRANSLATION_FW   0x00100000F0000671
-#define IO_OFFSET             0x0001000000000000
 .section K_TEXT_START, "ax"
 .global kernel_image_start
 ,6 → 49,19
 kernel_image_start:
     .auto
+#ifdef CONFIG_SMP
+    # Identify self(CPU) in OS structures by ID / EID
+    mov r9 = cr64
+    mov r10 = 1
+    movl r12 = 0xffffffff
+    movl r8 = cpu_by_id_eid_list
+    and r8 = r8, r12
+    shr r9 = r9, 16
+    add r8 = r8, r9
+    st1 [r8] = r10
+#endif
     mov psr.l = r0
     srlz.i
     srlz.d
 ,39 → 68,29
     # Fill TR.i and TR.d using Region Register #VRN_KERNEL
     movl r8 = (VRN_KERNEL << VRN_SHIFT)
     mov r9 = rr[r8]
     movl r10 = (RR_MASK)
     and r9 = r10, r9
     movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
     or  r9 = r10, r9
     mov rr[r8] = r9
     movl r8 = (VRN_KERNEL << VRN_SHIFT)
     mov cr.ifa = r8
-    mov r11 = cr.itir ;;
-    movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
-    or r10 =r10 , r11  ;;
-    mov cr.itir = r10;;
+    mov r11 = cr.itir
+    movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
+    or r10 = r10, r11
+    mov cr.itir = r10
     movl r10 = (KERNEL_TRANSLATION_I)
     itr.i itr[r0] = r10
     movl r10 = (KERNEL_TRANSLATION_D)
     itr.d dtr[r0] = r10
     movl r7 = 1
     movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
     mov cr.ifa = r8
 ,15 → 97,13
     movl r10 = (KERNEL_TRANSLATION_VIO)
     itr.d dtr[r7] = r10
+    mov r11 = cr.itir
+    movl r10 = ~0xfc
+    and r10 = r10, r11
+    movl r11 = (IO_PAGE_WIDTH << PS_SHIFT)
+    or r10 = r10, r11
+    mov cr.itir = r10
-    mov r11 = cr.itir ;;
-    movl r10 = ~0xfc;;
-    and r10 =r10 , r11  ;;
-    movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
-    or r10 =r10 , r11  ;;
-    mov cr.itir = r10;;
     movl r7 = 2
     movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
     mov cr.ifa = r8
 ,12 → 110,26
     movl r10 = (KERNEL_TRANSLATION_IO)
     itr.d dtr[r7] = r10
+    # Setup mapping for fimware arrea (also SAPIC)
+    mov r11 = cr.itir
+    movl r10 = ~0xfc
+    and r10 = r10, r11
+    movl r11 = (FW_PAGE_WIDTH << PS_SHIFT)
+    or r10 = r10, r11
+    mov cr.itir = r10
+    movl r7 = 3
+    movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
+    mov cr.ifa = r8
+    movl r10 = (KERNEL_TRANSLATION_FW)
+    itr.d dtr[r7] = r10
-    # initialize PSR
+    # Initialize PSR
     movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
     mov r9 = psr
     or r10 = r10, r9
     mov cr.ipsr = r10
     mov cr.ifs = r0
 ,11 → 139,14
     srlz.i
     .explicit
     /*
-     * Return From Interupt is the only the way to fill upper half word of PSR.
+     * Return From Interrupt is the only way to
+     * fill the upper half word of PSR.
      */
-    rfi;;
+    rfi ;;
 .global paging_start
 paging_start:
 ,45 → 154,64
      * Now we are paging.
      */
-    # switch to register bank 1
+    # Switch to register bank 1
     bsw.1
+#ifdef CONFIG_SMP
+    # Am I BSP or AP?
+    movl r20 = bsp_started ;;
+    ld8 r20 = [r20] ;;
+    cmp.eq p3, p2 = r20, r0 ;;
+#else
+    cmp.eq p3, p2 = r0, r0 ;;   /* you are BSP */
+#endif  /* CONFIG_SMP */
-    # initialize register stack
+    # Initialize register stack
     mov ar.rsc = r0
     movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
     mov ar.bspstore = r8
     loadrs
-    # initialize memory stack to some sane value
+    # Initialize memory stack to some sane value
     movl r12 = stack0 ;;
     add r12 = -16, r12  /* allocate a scratch area on the stack */
-    # initialize gp (Global Pointer) register
+    # Initialize gp (Global Pointer) register
     movl r20 = (VRN_KERNEL << VRN_SHIFT);;
     or r20 = r20,r1;;
     movl r1 = _hardcoded_load_address
     /*
-     * Initialize hardcoded_* variables.
+     * Initialize hardcoded_* variables. Do only BSP
      */
-    movl r14 = _hardcoded_ktext_size
-    movl r15 = _hardcoded_kdata_size
-    movl r16 = _hardcoded_load_address ;;
-    addl r17 = @gprel(hardcoded_ktext_size), gp
-    addl r18 = @gprel(hardcoded_kdata_size), gp
-    addl r19 = @gprel(hardcoded_load_address), gp
-    addl r21 = @gprel(bootinfo), gp
+(p3)    movl r14 = _hardcoded_ktext_size
+(p3)    movl r15 = _hardcoded_kdata_size
+(p3)    movl r16 = _hardcoded_load_address ;;
+(p3)    addl r17 = @gprel(hardcoded_ktext_size), gp
+(p3)    addl r18 = @gprel(hardcoded_kdata_size), gp
+(p3)    addl r19 = @gprel(hardcoded_load_address), gp
+(p3)    addl r21 = @gprel(bootinfo), gp
     ;;
-    st8 [r17] = r14
-    st8 [r18] = r15
-    st8 [r19] = r16
-    st8 [r21] = r20
+(p3)    st8 [r17] = r14
+(p3)    st8 [r18] = r15
+(p3)    st8 [r19] = r16
+(p3)    st8 [r21] = r20
     ssm (1 << 19) ;; /* Disable f32 - f127 */
     srlz.i
     srlz.d ;;
+#ifdef CONFIG_SMP
+(p2)    movl r18 = main_ap ;;
+(p2)    mov b1 = r18 ;;
+(p2)    br.call.sptk.many b0 = b1
+    # Mark that BSP is on
+    mov r20 = 1 ;;
+    movl r21 = bsp_started ;;
+    st8 [r21] = r20 ;;
+#endif
     br.call.sptk.many b0 = arch_pre_main
     movl r18 = main_bsp ;;
 ,6 → 218,51
     mov b1 = r18 ;;
     br.call.sptk.many b0 = b1
 :
     br 0b
+#ifdef CONFIG_SMP
+.align 4096
+kernel_image_ap_start:
+    .auto
+    # Identify self(CPU) in OS structures by ID / EID
+    mov r9 = cr64
+    mov r10 = 1
+    movl r12 = 0xffffffff
+    movl r8 = cpu_by_id_eid_list
+    and r8 = r8, r12
+    shr r9 = r9, 16
+    add r8 = r8, r9
+    st1 [r8] = r10
+    # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list)
+kernel_image_ap_start_loop:
+    movl r11 = kernel_image_ap_start_loop
+    and r11 = r11, r12
+    mov b1 = r11
+    ld1 r20 = [r8] ;;
+    movl r21 = 3 ;;
+    cmp.eq p2, p3 = r20, r21 ;;
+(p3)    br.call.sptk.many b0 = b1
+    movl r11 = kernel_image_start
+    and r11 = r11, r12
+    mov b1 = r11
+    br.call.sptk.many b0 = b1
+.align 16
+.global bsp_started
+bsp_started:
+.space 8
+.align 4096
+.global cpu_by_id_eid_list
+cpu_by_id_eid_list:
+.space 65536
+#endif  /* CONFIG_SMP */

 /branches/network/kernel/arch/arm32/_link.ld.in
 ,15 → 1,16
 /*
- *  ARM linker script
- *
+ * ARM linker script
+ *
  *  kernel text
  *  kernel data
- *
+ *
  */
+#define KERNEL_LOAD_ADDRESS 0x80200000
 OUTPUT_ARCH(arm)
-ENTRY(kernel_image_start)
+ENTRY(kernel_image_start)
 SECTIONS {
     . = KERNEL_LOAD_ADDRESS;
     .text : {
 ,29 → 20,29
     }
     .data : {
         kdata_start = .;
-        *(.data);       /* initialized data */
+        *(.data);                       /* initialized data */
         hardcoded_ktext_size = .;
-        LONG(ktext_end - ktext_start);
+        LONG(ktext_end - ktext_start);
         hardcoded_kdata_size = .;
         LONG(kdata_end - kdata_start);
         hardcoded_load_address = .;
         LONG(KERNEL_LOAD_ADDRESS);
-        *(.bss);        /* uninitialized static variables */
-        *(COMMON);      /* global variables */
+        *(.bss);                        /* uninitialized static variables */
+        *(COMMON);                      /* global variables */
         *(.rodata*);
         *(.sdata);
         *(.reginfo);
         symbol_table = .;
-        *(symtab.*);
+        *(symtab.*);
     }
     .sbss : {
         *(.sbss);
         *(.scommon);
     }
     kdata_end = .;
     /DISCARD/ : {
       *(.mdebug*);
       *(.pdr);
 ,5 → 49,4
       *(.comment);
       *(.note);
     }
 }

 /branches/network/kernel/arch/arm32/include/asm/boot.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
 /** @file
 ,26 → 37,9
 #define KERN_arm32_ASM_BOOT_H_
 /** Size of a temporary stack used for initial kernel start. */
-#define TEMP_STACK_SIZE 0x100
+#define TEMP_STACK_SIZE  0x100
-#ifndef __ASM__
-/** Kernel entry point.
- *
- * Implemented in assembly. Copies boot_bootinfo (declared as bootinfo in
- * boot/arch/arm32/loader/main.c) to #bootinfo struct. Then jumps to
- * #arch_pre_main and #main_bsp.
- *
- * @param entry          Entry point address (not used).
- * @param boot_bootinfo  Struct holding information about loaded tasks.
- * @param bootinfo_size  Size of the bootinfo structure.
- */
-extern void kernel_image_start(void *entry, void *boot_bootinfo,
-    unsigned int bootinfo_size);
 #endif
-#endif
 /** @}
  */

/branches/network/kernel/arch/arm32/include/interrupt.h
37,6 → 37,7
#define KERN_arm32_INTERRUPT_H_

#include <arch/types.h>
#include <arch/exception.h>

/** Initial size of exception dispatch table. */
#define IVT_ITEMS 6

 /branches/network/kernel/arch/arm32/include/regutils.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
 /**
 ,7 → 57,10
 static inline uint32_t nm## _status_reg_read(void) \
 { \
     uint32_t retval; \
-    asm volatile("mrs %0, " #reg : "=r" (retval)); \
+    asm volatile( \
+        "mrs %[retval], " #reg \
+        : [retval] "=r" (retval) \
+    ); \
     return retval; \
 }
 ,7 → 67,10
 #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
 static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
 { \
-    asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \
+    asm volatile( \
+        "msr " #reg "_" #field ", %[value]" \
+        :: [value] "r" (value) \
+    ); \
 }

 /branches/network/kernel/arch/arm32/include/console.h
 ,13 → 36,6
 #ifndef KERN_arm32_CONSOLE_H_
 #define KERN_arm32_CONSOLE_H_
-/** Initializes console.
- *
- * @param devno Console device number.
- */
-extern void console_init(devno_t devno);
 #endif
 /** @}

 /branches/network/kernel/arch/arm32/include/types.h
 ,6 → 64,9
 typedef uint32_t unative_t;
 typedef int32_t native_t;
+typedef struct {
+} fncptr_t;
 #define PRIp "x"    /**< Format for uintptr_t. */
 #define PRIs "u"    /**< Format for size_t. */
 #define PRIc "u"    /**< Format for count_t. */

 /branches/network/kernel/arch/arm32/include/atomic.h
 ,10 → 26,10
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
-/** @file
+/** @file
  *  @brief Atomic operations.
  */
 ,26 → 42,26
  * @param i   Value to be added.
  *
  * @return Value after addition.
+ *
  */
 static inline long atomic_add(atomic_t *val, int i)
 {
     int ret;
     volatile long *mem = &(val->count);
     asm volatile (
-    "1:\n"
-        "ldr r2, [%1]       \n"
-        "add r3, r2, %2     \n"
-        "str r3, %0         \n"
-        "swp r3, r3, [%1]   \n"
-        "cmp r3, r2         \n"
-        "bne 1b             \n"
-        : "=m" (ret)
-        : "r" (mem), "r" (i)
+        "1:\n"
+            "ldr r2, [%[mem]]\n"
+            "add r3, r2, %[i]\n"
+            "str r3, %[ret]\n"
+            "swp r3, r3, [%[mem]]\n"
+            "cmp r3, r2\n"
+            "bne 1b\n"
+        : [ret] "=m" (ret)
+        : [mem] "r" (mem), [i] "r" (i)
         : "r3", "r2"
     );
     return ret;
 }

 /branches/network/kernel/arch/arm32/include/arch.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
 /** @file
 ,6 → 36,26
 #ifndef KERN_arm32_ARCH_H_
 #define KERN_arm32_ARCH_H_
+#define TASKMAP_MAX_RECORDS  32
+#define CPUMAP_MAX_RECORDS   32
+#define BOOTINFO_TASK_NAME_BUFLEN 32
+#include <typedefs.h>
+typedef struct {
+    uintptr_t addr;
+    uint32_t size;
+    char name[BOOTINFO_TASK_NAME_BUFLEN];
+} utask_t;
+typedef struct {
+    uint32_t cnt;
+    utask_t tasks[TASKMAP_MAX_RECORDS];
+} bootinfo_t;
+extern void arch_pre_main(void *entry, bootinfo_t *bootinfo);
 #endif
 /** @}

 /branches/network/kernel/arch/arm32/include/asm.h
 ,10 → 26,10
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
-/** @file
+/** @file
  *  @brief Declarations of functions implemented in assembly.
  */
 ,6 → 36,7
 #ifndef KERN_arm32_ASM_H_
 #define KERN_arm32_ASM_H_
+#include <typedefs.h>
 #include <arch/types.h>
 #include <arch/stack.h>
 #include <config.h>
 ,19 → 47,50
 {
 }
+static inline void pio_write_8(ioport8_t *port, uint8_t v)
+{
+    *port = v;
+}
+static inline void pio_write_16(ioport16_t *port, uint16_t v)
+{
+    *port = v;
+}
+static inline void pio_write_32(ioport32_t *port, uint32_t v)
+{
+    *port = v;
+}
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
+    return *port;
+}
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    return *port;
+}
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    return *port;
+}
 /** Return base address of current stack.
- *
+ *
  * Return the base address of the current stack.
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
 {
     uintptr_t v;
     asm volatile (
-        "and %0, sp, %1\n"
-        : "=r" (v)
-        : "r" (~(STACK_SIZE - 1))
+        "and %[v], sp, %[size]\n"
+        : [v] "=r" (v)
+        : [size] "r" (~(STACK_SIZE - 1))
     );
     return v;
 }

 /branches/network/kernel/arch/arm32/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32mm
+/** @addtogroup arm32mm
  * @{
  */
 /** @file
 ,8 → 36,8
 #ifndef KERN_arm32_FRAME_H_
 #define KERN_arm32_FRAME_H_
-#define FRAME_WIDTH     12 /* 4KB frames */
-#define FRAME_SIZE      (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  12  /* 4KB frames */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifdef KERNEL
 #ifndef __ASM__
 ,8 → 44,8
 #include <arch/types.h>
-#define BOOT_PAGE_TABLE_SIZE    0x4000
-#define BOOT_PAGE_TABLE_ADDRESS 0x4000
+#define BOOT_PAGE_TABLE_SIZE     0x4000
+#define BOOT_PAGE_TABLE_ADDRESS  0x4000
 #define BOOT_PAGE_TABLE_START_FRAME     (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH)
 #define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)

 /branches/network/kernel/arch/arm32/include/mm/page.h
 ,9 → 193,8
 static inline void set_ptl0_addr(pte_level0_t *pt)
 {
     asm volatile (
-        "mcr p15, 0, %0, c2, c0, 0 \n"
-        :
-        : "r"(pt)
+        "mcr p15, 0, %[pt], c2, c0, 0\n"
+        :: [pt] "r" (pt)
     );
 }

 /branches/network/kernel/arch/arm32/include/mm/tlb.h
 ,9 → 36,6
 #ifndef KERN_arm32_TLB_H_
 #define KERN_arm32_TLB_H_
-#define tlb_arch_init()
-#define tlb_print()
 #endif
 /** @}

 /branches/network/kernel/arch/arm32/include/barrier.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
 /** @file
 ,12 → 39,12
 /*
  * TODO: implement true ARM memory barriers for macros below.
  */
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
-#define memory_barrier()        asm volatile ("" ::: "memory")
-#define read_barrier()          asm volatile ("" ::: "memory")
-#define write_barrier()         asm volatile ("" ::: "memory")
+#define memory_barrier()  asm volatile ("" ::: "memory")
+#define read_barrier()    asm volatile ("" ::: "memory")
+#define write_barrier()   asm volatile ("" ::: "memory")
 #define smc_coherence(a)
 #define smc_coherence_block(a, l)

 /branches/network/kernel/arch/arm32/include/drivers/gxemul.h
 ,41 → 38,33
 #ifndef KERN_arm32_GXEMUL_H_
 #define KERN_arm32_GXEMUL_H_
-#include <console/chardev.h>
-/** Last interrupt number (beginning from 0) whose status is probed
+/** Last interrupt number (beginning from 0) whose status is probed
  * from interrupt controller
  */
-#define GXEMUL_IRQC_MAX_IRQ     8
+#define GXEMUL_IRQC_MAX_IRQ  8
+#define GXEMUL_KBD_IRQ       2
+#define GXEMUL_TIMER_IRQ     4
 /** Timer frequency */
-#define GXEMUL_TIMER_FREQ       100
+#define GXEMUL_TIMER_FREQ  100
-/** Struct containing mappings of gxemul HW devices into kernel part
- *  of virtual address space.
- */
-typedef struct {
-    uintptr_t videoram;
-    uintptr_t kbd;
-    uintptr_t rtc;
-    uintptr_t rtc_freq;
-    uintptr_t rtc_ack;
-    uintptr_t irqc;
-    uintptr_t irqc_mask;
-    uintptr_t irqc_unmask;
-} gxemul_hw_map_t;
+#define GXEMUL_KBD_ADDRESS   0x10000000
+#define GXEMUL_MP_ADDRESS    0x11000000
+#define GXEMUL_FB_ADDRESS    0x12000000
+#define GXEMUL_RTC_ADDRESS   0x15000000
+#define GXEMUL_IRQC_ADDRESS  0x16000000
-extern void gxemul_hw_map_init(void);
-extern void gxemul_console_init(devno_t devno);
-extern void gxemul_release_console(void);
-extern void gxemul_grab_console(void);
-extern void gxemul_timer_irq_start(void);
-extern void gxemul_debug_putc(char ch);
-extern void gxemul_cpu_halt(void);
-extern void gxemul_irq_exception(int exc_no, istate_t *istate);
-extern size_t gxemul_get_memory_size(void);
-extern uintptr_t gxemul_get_fb_address(void);
+extern void *gxemul_kbd;
+extern void *gxemul_rtc;
+extern void *gxemul_irqc;
+#define GXEMUL_HALT_OFFSET        0x010
+#define GXEMUL_RTC_FREQ_OFFSET    0x100
+#define GXEMUL_MP_MEMSIZE_OFFSET  0x090
+#define GXEMUL_RTC_ACK_OFFSET     0x110
+extern void gxemul_init(void);
 #endif
 /** @}

 /branches/network/kernel/arch/arm32/Makefile.inc
 ,10 → 29,6
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf32-littlearm
 BFD_ARCH = arm
 BFD = binary
 ,62 → 35,28
 TARGET = arm-linux-gnu
 TOOLCHAIN_DIR = $(CROSS_PREFIX)/arm
-KERNEL_LOAD_ADDRESS = 0x80200000
-# ifeq ($(MACHINE), gxemul_testarm)
-    DMACHINE = MACHINE_GXEMUL_TESTARM
-# endif
 ATSIGN = %
 GCC_CFLAGS += -fno-zero-initialized-in-bss
-DEFS += -D__32_BITS__ -DKERNEL_LOAD_ADDRESS=$(KERNEL_LOAD_ADDRESS) -D$(DMACHINE)
+DEFS += -D__32_BITS__
-# Compile with framebuffer support
-ifeq ($(CONFIG_FB), y)
-    DEFS += -DCONFIG_FB -DFB_INVERT_ENDIAN
-endif
-## Compile with hierarchical page tables support.
-#
-CONFIG_PAGE_PT = y
-DEFS += -DCONFIG_PAGE_PT
-## Compile with support for address space identifiers.
-#
-# no HW support for ASIDs
-#CONFIG_ASID = y
-#CONFIG_ASID_FIFO = y
-## Compile with support with software division and multiplication.
-#
-CONFIG_SOFTINT = y
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/start.S \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/arm32.c \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/dummy.S \
-    arch/$(ARCH)/src/panic.S \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/debug/print.c \
-    arch/$(ARCH)/src/console.c \
-    arch/$(ARCH)/src/exception.c \
-    arch/$(ARCH)/src/userspace.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/mm/page_fault.c
-# ifeq ($(MACHINE), gxemul_testarm)
-    ARCH_SOURCES += arch/$(ARCH)/src/drivers/gxemul.c
-# endif
+    arch/$(KARCH)/src/start.S \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/arm32.c \
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/dummy.S \
+    arch/$(KARCH)/src/panic.S \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/console.c \
+    arch/$(KARCH)/src/exception.c \
+    arch/$(KARCH)/src/userspace.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/mm/page_fault.c \
+    arch/$(KARCH)/src/drivers/gxemul.c

 /branches/network/kernel/arch/arm32/src/exception.c
 ,13 → 34,12
  */
 #include <arch/exception.h>
-#include <arch/debug/print.h>
 #include <arch/memstr.h>
 #include <arch/regutils.h>
 #include <interrupt.h>
-#include <arch/machine.h>
 #include <arch/mm/page_fault.h>
 #include <arch/barrier.h>
+#include <arch/drivers/gxemul.h>
 #include <print.h>
 #include <syscall/syscall.h>
 ,57 → 62,60
  *
  * Temporary exception stack is used to save a few registers
  * before stack switch takes place.
+ *
  */
 inline static void setup_stack_and_save_regs()
 {
-    asm volatile(
-        "ldr r13, =exc_stack        \n"
-        "stmfd r13!, {r0}       \n"
-        "mrs r0, spsr           \n"
-        "and r0, r0, #0x1f      \n"
-        "cmp r0, #0x10          \n"
-        "bne 1f             \n"
+    asm volatile (
+        "ldr r13, =exc_stack\n"
+        "stmfd r13!, {r0}\n"
+        "mrs r0, spsr\n"
+        "and r0, r0, #0x1f\n"
+        "cmp r0, #0x10\n"
+        "bne 1f\n"
         /* prev mode was usermode */
-        "ldmfd r13!, {r0}       \n"
-        "ldr r13, =supervisor_sp    \n"
-        "ldr r13, [r13]         \n"
-        "stmfd r13!, {lr}       \n"
-        "stmfd r13!, {r0-r12}       \n"
-        "stmfd r13!, {r13, lr}^     \n"
-        "mrs r0, spsr           \n"
-        "stmfd r13!, {r0}       \n"
-        "b 2f               \n"
+        "ldmfd r13!, {r0}\n"
+        "ldr r13, =supervisor_sp\n"
+        "ldr r13, [r13]\n"
+        "stmfd r13!, {lr}\n"
+        "stmfd r13!, {r0-r12}\n"
+        "stmfd r13!, {r13, lr}^\n"
+        "mrs r0, spsr\n"
+        "stmfd r13!, {r0}\n"
+        "b 2f\n"
         /* mode was not usermode */
-    "1:\n"
-        "stmfd r13!, {r1, r2, r3}   \n"
-        "mrs r1, cpsr           \n"
-        "mov r2, lr         \n"
-        "bic r1, r1, #0x1f      \n"
-        "orr r1, r1, r0         \n"
-        "mrs r0, cpsr           \n"
-        "msr cpsr_c, r1         \n"
-        "mov r3, r13            \n"
-        "stmfd r13!, {r2}       \n"
-        "mov r2, lr         \n"
-        "stmfd r13!, {r4-r12}       \n"
-        "mov r1, r13            \n"
-        /* the following two lines are for debugging */
-        "mov sp, #0         \n"
-        "mov lr, #0         \n"
-        "msr cpsr_c, r0         \n"
-        "ldmfd r13!, {r4, r5, r6, r7}   \n"
-        "stmfd r1!, {r4, r5, r6}    \n"
-        "stmfd r1!, {r7}        \n"
-        "stmfd r1!, {r2}        \n"
-        "stmfd r1!, {r3}        \n"
-        "mrs r0, spsr           \n"
-        "stmfd r1!, {r0}        \n"
-        "mov r13, r1            \n"
-    "2:\n"
+        "1:\n"
+            "stmfd r13!, {r1, r2, r3}\n"
+            "mrs r1, cpsr\n"
+            "mov r2, lr\n"
+            "bic r1, r1, #0x1f\n"
+            "orr r1, r1, r0\n"
+            "mrs r0, cpsr\n"
+            "msr cpsr_c, r1\n"
+            "mov r3, r13\n"
+            "stmfd r13!, {r2}\n"
+            "mov r2, lr\n"
+            "stmfd r13!, {r4-r12}\n"
+            "mov r1, r13\n"
+            /* the following two lines are for debugging */
+            "mov sp, #0\n"
+            "mov lr, #0\n"
+            "msr cpsr_c, r0\n"
+            "ldmfd r13!, {r4, r5, r6, r7}\n"
+            "stmfd r1!, {r4, r5, r6}\n"
+            "stmfd r1!, {r7}\n"
+            "stmfd r1!, {r2}\n"
+            "stmfd r1!, {r3}\n"
+            "mrs r0, spsr\n"
+            "stmfd r1!, {r0}\n"
+            "mov r13, r1\n"
+        "2:\n"
     );
 }
 ,10 → 191,13
 }
 /** Calls exception dispatch routine. */
-#define CALL_EXC_DISPATCH(exception)        \
-    asm("mov r0, %0" : : "i" (exception));  \
-    asm("mov r1, r13");         \
-    asm("bl exc_dispatch");
+#define CALL_EXC_DISPATCH(exception) \
+    asm volatile ( \
+        "mov r0, %[exc]\n" \
+        "mov r1, r13\n" \
+        "bl exc_dispatch\n" \
+        :: [exc] "i" (exception) \
+    );\
 /** General exception handler.
  *
 ,9 → 206,9
  *
  *  @param exception Exception number.
  */
-#define PROCESS_EXCEPTION(exception)        \
-    setup_stack_and_save_regs();        \
-    CALL_EXC_DISPATCH(exception)        \
+#define PROCESS_EXCEPTION(exception) \
+    setup_stack_and_save_regs(); \
+    CALL_EXC_DISPATCH(exception) \
     load_regs();
 /** Updates specified exception vector to jump to given handler.
 ,7 → 259,10
 /** Low-level Prefetch Abort Exception handler. */
 static void prefetch_abort_exception_entry(void)
 {
-    asm("sub lr, lr, #4");
+    asm volatile (
+        "sub lr, lr, #4"
+    );
     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
 }
 ,7 → 269,10
 /** Low-level Data Abort Exception handler. */
 static void data_abort_exception_entry(void)
 {
-    asm("sub lr, lr, #8");
+    asm volatile (
+        "sub lr, lr, #8"
+    );
     PROCESS_EXCEPTION(EXC_DATA_ABORT);
 }
 ,7 → 284,10
  */
 static void irq_exception_entry(void)
 {
-    asm("sub lr, lr, #4");
+    asm volatile (
+        "sub lr, lr, #4"
+    );
     setup_stack_and_save_regs();
     switch_to_irq_servicing_mode();
 ,6 → 307,12
         istate->r3, istate->r4, istate->r5, istate->r6);
 }
+/** Returns the mask of active interrupts. */
+static inline uint32_t gxemul_irqc_get_sources(void)
+{
+    return *((uint32_t *) gxemul_irqc);
+}
 /** Interrupt Exception handler.
  *
  * Determines the sources of interrupt and calls their handlers.
 ,7 → 319,23
  */
 static void irq_exception(int exc_no, istate_t *istate)
 {
-    machine_irq_exception(exc_no, istate);
+    uint32_t sources = gxemul_irqc_get_sources();
+    unsigned int i;
+    for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) {
+        if (sources & (1 << i)) {
+            irq_t *irq = irq_dispatch_and_lock(i);
+            if (irq) {
+                /* The IRQ handler was found. */
+                irq->handler(irq);
+                spinlock_unlock(&irq->lock);
+            } else {
+                /* Spurious interrupt.*/
+                printf("cpu%d: spurious interrupt (inum=%d)\n",
+                    CPU->id, i);
+            }
+        }
+    }
 }
 /** Fills exception vectors with appropriate exception handlers. */
 ,7 → 359,7
     install_handler((unsigned) irq_exception_entry,
         (unsigned *) EXC_IRQ_VEC);
-    install_handler((unsigned)fiq_exception_entry,
+    install_handler((unsigned) fiq_exception_entry,
         (unsigned *) EXC_FIQ_VEC);
 }
 ,17 → 369,23
 {
     uint32_t control_reg;
-    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
+    asm volatile (
+        "mrc p15, 0, %[control_reg], c1, c1"
+        : [control_reg] "=r" (control_reg)
+    );
     /* switch on the high vectors bit */
     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
-    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
+    asm volatile (
+        "mcr p15, 0, %[control_reg], c1, c1"
+        :: [control_reg] "r" (control_reg)
+    );
 }
 #endif
 /** Initializes exception handling.
- *
+ *
  * Installs low-level exception handlers and then registers
  * exceptions and their handlers to kernel exception dispatcher.
  */
 ,18 → 409,18
  */
 void print_istate(istate_t *istate)
 {
-    dprintf("istate dump:\n");
-    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
+    printf("istate dump:\n");
+    printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
         istate->r0, istate->r1, istate->r2, istate->r3);
-    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
+    printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
         istate->r4, istate->r5, istate->r6, istate->r7);
-    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
+    printf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
         istate->r8, istate->r9, istate->r10, istate->r11);
-    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
+    printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
         istate->r12, istate->sp, istate->lr, istate->spsr);
-    dprintf(" pc: %x\n", istate->pc);
+    printf(" pc: %x\n", istate->pc);
 }
 /** @}

 /branches/network/kernel/arch/arm32/src/console.c
 ,32 → 26,28
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32
+/** @addtogroup arm32
  * @{
  */
-/** @file
+/** @file
  *  @brief Console.
  */
 #include <console/console.h>
 #include <arch/console.h>
-#include <arch/machine.h>
+#include <genarch/fb/fb.h>
-void console_init(devno_t devno)
-{
-    machine_console_init(devno);
-}
 /** Acquire console back for kernel. */
 void arch_grab_console(void)
 {
-    machine_grab_console();
+#ifdef CONFIG_FB
+    fb_redraw();
+#endif
 }
 /** Return console to userspace. */
 void arch_release_console(void)
 {
-    machine_release_console();
 }
 /** @}

 /branches/network/kernel/arch/arm32/src/arm32.c
 ,36 → 34,37
  */
 #include <arch.h>
-#include <arch/boot.h>
 #include <config.h>
 #include <arch/console.h>
-#include <ddi/device.h>
 #include <genarch/fb/fb.h>
 #include <genarch/fb/visuals.h>
+#include <genarch/drivers/dsrln/dsrlnin.h>
+#include <genarch/drivers/dsrln/dsrlnout.h>
+#include <genarch/srln/srln.h>
+#include <sysinfo/sysinfo.h>
 #include <ddi/irq.h>
-#include <arch/debug/print.h>
+#include <arch/drivers/gxemul.h>
 #include <print.h>
 #include <config.h>
 #include <interrupt.h>
 #include <arch/regutils.h>
-#include <arch/machine.h>
 #include <userspace.h>
+#include <macros.h>
+#include <string.h>
-/** Information about loaded tasks. */
-bootinfo_t bootinfo;
-/** Performs arm32 specific initialization before main_bsp() is called. */
-void arch_pre_main(void)
+/** Performs arm32-specific initialization before main_bsp() is called. */
+void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
 {
     unsigned int i;
-    init.cnt = bootinfo.cnt;
-    for (i = 0; i < bootinfo.cnt; ++i) {
-        init.tasks[i].addr = bootinfo.tasks[i].addr;
-        init.tasks[i].size = bootinfo.tasks[i].size;
+    init.cnt = bootinfo->cnt;
+    for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); ++i) {
+        init.tasks[i].addr = bootinfo->tasks[i].addr;
+        init.tasks[i].size = bootinfo->tasks[i].size;
+        strncpy(init.tasks[i].name, bootinfo->tasks[i].name,
+            CONFIG_TASK_NAME_BUFLEN);
     }
 }
 /** Performs arm32 specific initialization before mm is initialized. */
 ,18 → 77,27
 /** Performs arm32 specific initialization afterr mm is initialized. */
 void arch_post_mm_init(void)
 {
-    machine_hw_map_init();
+    gxemul_init();
     /* Initialize exception dispatch table */
     exception_init();
     interrupt_init();
-    console_init(device_assign_devno());
 #ifdef CONFIG_FB
-    fb_init(machine_get_fb_address(), 640, 480, 1920, VISUAL_RGB_8_8_8);
-#endif
+    fb_properties_t prop = {
+        .addr = GXEMUL_FB_ADDRESS,
+        .offset = 0,
+        .x = 640,
+        .y = 480,
+        .scan = 1920,
+        .visual = VISUAL_BGR_8_8_8,
+    };
+    fb_init(&prop);
+#else
+#ifdef CONFIG_ARM_PRN
+    dsrlnout_init((ioport8_t *) gxemul_kbd);
+#endif /* CONFIG_ARM_PRN */
+#endif /* CONFIG_FB */
 }
 /** Performs arm32 specific tasks needed after cpu is initialized.
 ,6 → 126,23
  */
 void arch_post_smp_init(void)
 {
+#ifdef CONFIG_ARM_KBD
+    /*
+     * Initialize the msim/GXemul keyboard port. Then initialize the serial line
+     * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
+     */
+    indev_t *kbrdin = dsrlnin_init((dsrlnin_t *) gxemul_kbd, GXEMUL_KBD_IRQ);
+    if (kbrdin)
+        srln_init(kbrdin);
+    /*
+     * This is the necessary evil until the userspace driver is entirely
+     * self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
+    sysinfo_set_item_val("kbd.address.virtual", NULL, (unative_t) gxemul_kbd);
+#endif
 }
 ,7 → 176,8
 /** Halts CPU. */
 void cpu_halt(void)
 {
-    machine_cpu_halt();
+    *((char *) (gxemul_kbd + GXEMUL_HALT_OFFSET))
+        = 0;
 }
 /** Reboot. */
 ,9 → 184,22
 void arch_reboot()
 {
     /* not implemented */
-    for (;;)
-        ;
+    while (1);
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/arm32/src/cpu/cpu.c
 ,7 → 36,7
 #include <arch/cpu.h>
 #include <cpu.h>
 #include <arch.h>
-#include <print.h>
+#include <print.h>
 /** Number of indexes left out in the #imp_data array */
 #define IMP_DATA_START_OFFSET 0x40
 ,10 → 82,10
 {
     uint32_t ident;
     asm volatile (
-        "mrc p15, 0, %0, c0, c0, 0\n"
-        : "=r" (ident)
+        "mrc p15, 0, %[ident], c0, c0, 0\n"
+        : [ident] "=r" (ident)
     );
     cpu->imp_num = ident >> 24;
     cpu->variant_num = (ident << 8) >> 28;
     cpu->arch_num = (ident << 12) >> 28;

 /branches/network/kernel/arch/arm32/src/mm/tlb.c
 ,7 → 48,7
     asm volatile (
         "eor r1, r1\n"
         "mcr p15, 0, r1, c8, c7, 0\n"
-        : : : "r1"
+        ::: "r1"
     );
 }
 ,9 → 68,8
 static inline void invalidate_page(uintptr_t page)
 {
     asm volatile (
-        "mcr p15, 0, %0, c8, c7, 1"
-        :
-        : "r" (page)
+        "mcr p15, 0, %[page], c8, c7, 1\n"
+        :: [page] "r" (page)
     );
 }
 ,7 → 80,7
  * @param page Address of the first page whose entry is to be invalidated.
  * @param cnt Number of entries to invalidate.
  */
-void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
+void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, count_t cnt)
 {
     unsigned int i;
 ,5 → 88,13
         invalidate_page(page + i * PAGE_SIZE);
 }
+void tlb_arch_init(void)
+{
+}
+void tlb_print(void)
+{
+}
 /** @}
  */

 /branches/network/kernel/arch/arm32/src/mm/page_fault.c
 ,7 → 34,6
  */
 #include <panic.h>
 #include <arch/exception.h>
-#include <arch/debug/print.h>
 #include <arch/mm/page_fault.h>
 #include <mm/as.h>
 #include <genarch/mm/page_pt.h>
 ,12 → 48,13
 static inline fault_status_t read_fault_status_register(void)
 {
     fault_status_union_t fsu;
     /* fault status is stored in CP15 register 5 */
     asm volatile (
-        "mrc p15, 0, %0, c5, c0, 0"
-        : "=r"(fsu.dummy)
+        "mrc p15, 0, %[dummy], c5, c0, 0"
+        : [dummy] "=r" (fsu.dummy)
     );
     return fsu.fs;
 }
 ,17 → 61,18
 /** Returns FAR (fault address register) content.
  *
  * @return FAR (fault address register) content (address that caused a page
- *     fault)
+ *         fault)
  */
 static inline uintptr_t read_fault_address_register(void)
 {
     uintptr_t ret;
     /* fault adress is stored in CP15 register 6 */
     asm volatile (
-        "mrc p15, 0, %0, c6, c0, 0"
-        : "=r"(ret)
+        "mrc p15, 0, %[ret], c6, c0, 0"
+        : [ret] "=r" (ret)
     );
     return ret;
 }
 ,29 → 81,26
  * @param instr Instruction
  *
  * @return true when instruction is load/store, false otherwise
+ *
  */
 static inline bool is_load_store_instruction(instruction_t instr)
 {
     /* load store immediate offset */
-    if (instr.type == 0x2) {
+    if (instr.type == 0x2)
         return true;
-    }
     /* load store register offset */
-    if (instr.type == 0x3 && instr.bit4 == 0) {
+    if ((instr.type == 0x3) && (instr.bit4 == 0))
         return true;
-    }
     /* load store multiple */
-    if (instr.type == 0x4) {
+    if (instr.type == 0x4)
         return true;
-    }
     /* oprocessor load/store */
-    if (instr.type == 0x6) {
+    if (instr.type == 0x6)
         return true;
-    }
     return false;
 }
 ,12 → 113,11
 static inline bool is_swap_instruction(instruction_t instr)
 {
     /* swap, swapb instruction */
-    if (instr.type == 0x0 &&
-        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
-        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
+    if ((instr.type == 0x0) &&
+        ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
+        (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
         return true;
-    }
     return false;
 }
 ,8 → 139,8
     /* undefined instructions */
     if (instr.condition == 0xf) {
-        panic("page_fault - instruction doesn't access memory "
-            "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
+        panic("page_fault - instruction does not access memory "
+            "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
         return PF_ACCESS_EXEC;
     }
 ,7 → 159,7
     }
     panic("page_fault - instruction doesn't access memory "
-        "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
+        "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
     return PF_ACCESS_EXEC;
 }
 ,12 → 181,12
     if (ret == AS_PF_FAULT) {
         print_istate(istate);
-        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
+        printf("page fault - pc: %x, va: %x, status: %x(%x), "
             "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
             access);
-        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
-        panic("page fault\n");
+        fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
+        panic("Page fault.");
     }
 }
 ,9 → 200,9
     int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
     if (ret == AS_PF_FAULT) {
-        dprintf("prefetch_abort\n");
+        printf("prefetch_abort\n");
         print_istate(istate);
-        panic("page fault - prefetch_abort at address: %x\n",
+        panic("page fault - prefetch_abort at address: %x.",
             istate->pc);
     }
 }

 /branches/network/kernel/arch/arm32/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup arm32mm
+/** @addtogroup arm32mm
  * @{
  */
 /** @file
 ,9 → 35,8
 #include <mm/frame.h>
 #include <arch/mm/frame.h>
-#include <arch/machine.h>
+#include <arch/drivers/gxemul.h>
 #include <config.h>
-#include <arch/debug/print.h>
 /** Address of the last frame in the memory. */
 uintptr_t last_frame = 0;
 ,11 → 44,12
 /** Creates memory zones. */
 void frame_arch_init(void)
 {
-    /* all memory as one zone */
-    zone_create(0, ADDR2PFN(machine_get_memory_size()),
+    last_frame = *((uintptr_t *) (GXEMUL_MP_ADDRESS + GXEMUL_MP_MEMSIZE_OFFSET));
+    /* All memory as one zone */
+    zone_create(0, ADDR2PFN(last_frame),
         BOOT_PAGE_TABLE_START_FRAME + BOOT_PAGE_TABLE_SIZE_IN_FRAMES, 0);
-    last_frame = machine_get_memory_size();
     /* blacklist boot page table */
     frame_mark_unavailable(BOOT_PAGE_TABLE_START_FRAME,
         BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
 ,10 → 58,9
 /** Frees the boot page table. */
 void boot_page_table_free(void)
 {
-    int i;
-    for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++) {
+    unsigned int i;
+    for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++)
         frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS);
-    }
 }
 /** @}

 /branches/network/kernel/arch/arm32/src/mm/page.c
 ,19 → 51,15
  */
 void page_arch_init(void)
 {
+    int flags = PAGE_CACHEABLE;
+    page_mapping_operations = &pt_mapping_operations;
     uintptr_t cur;
-    int flags;
-    page_mapping_operations = &pt_mapping_operations;
-    flags = PAGE_CACHEABLE;
-    /* PA2KA(identity) mapping for all frames until last_frame */
-    for (cur = 0; cur < last_frame; cur += FRAME_SIZE) {
+    /* Kernel identity mapping */
+    for (cur = 0; cur < last_frame; cur += FRAME_SIZE)
         page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
-    }
-    /* create mapping for exception table at high offset */
+    /* Create mapping for exception table at high offset */
 #ifdef HIGH_EXCEPTION_VECTORS
     void *virtaddr = frame_alloc(ONE_FRAME, FRAME_KA);
     page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, KA2PA(virtaddr), flags);
 ,9 → 66,9
 #else
 #error "Only high exception vector supported now"
 #endif
     as_switch(NULL, AS_KERNEL);
     boot_page_table_free();
 }
 ,10 → 86,10
 {
     if (last_frame + ALIGN_UP(size, PAGE_SIZE) >
         KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) {
-        panic("Unable to map physical memory %p (%d bytes)",
+        panic("Unable to map physical memory %p (%d bytes).",
             physaddr, size)
     }
     uintptr_t virtaddr = PA2KA(last_frame);
     pfn_t i;
     for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) {
 ,7 → 97,7
             physaddr + PFN2ADDR(i),
             PAGE_NOT_CACHEABLE | PAGE_READ | PAGE_WRITE | PAGE_KERNEL);
     }
     last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
     return virtaddr;
 }

/branches/network/kernel/arch/arm32/src/panic.S
31,5 → 31,5
.global panic_printf

panic_printf:
bl debug_printf
bl printf
bl cpu_halt

 /branches/network/kernel/arch/arm32/src/userspace.c
 ,12 → 90,11
     /* set user mode, set registers, jump */
     asm volatile (
-        "mov sp, %0         \n"
-        "msr spsr_c, %1         \n"
-        "ldmfd sp!, {r0-r12, sp, lr}^   \n"
+        "mov sp, %[ustate]\n"
+        "msr spsr_c, %[user_mode]\n"
+        "ldmfd sp!, {r0-r12, sp, lr}^\n"
         "ldmfd sp!, {pc}^\n"
-        :
-        : "r" (&ustate), "r" (user_mode)
+        :: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
     );
     /* unreachable */

 /branches/network/kernel/arch/arm32/src/interrupt.c
 ,13 → 35,16
 #include <arch/asm.h>
 #include <arch/regutils.h>
+#include <arch/drivers/gxemul.h>
 #include <ddi/irq.h>
-#include <arch/machine.h>
+#include <ddi/device.h>
 #include <interrupt.h>
 /** Initial size of a table holding interrupt handlers. */
 #define IRQ_COUNT 8
+static irq_t gxemul_timer_irq;
 /** Disable interrupts.
  *
  * @return Old interrupt priority level.
 ,7 → 52,7
 ipl_t interrupts_disable(void)
 {
     ipl_t ipl = current_status_reg_read();
     current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
     return ipl;
 ,9 → 65,9
 ipl_t interrupts_enable(void)
 {
     ipl_t ipl = current_status_reg_read();
     current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
     return ipl;
 }
 ,6 → 91,41
     return current_status_reg_read();
 }
+/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
+ *
+ * @param frequency Interrupts frequency (0 disables RTC).
+ */
+static void gxemul_timer_start(uint32_t frequency)
+{
+    *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))
+        = frequency;
+}
+static irq_ownership_t gxemul_timer_claim(irq_t *irq)
+{
+    return IRQ_ACCEPT;
+}
+/** Timer interrupt handler.
+ *
+ * @param irq Interrupt information.
+ * @param arg Not used.
+ */
+static void gxemul_timer_irq_handler(irq_t *irq)
+{
+    /*
+    * We are holding a lock which prevents preemption.
+    * Release the lock, call clock() and reacquire the lock again.
+    */
+    spinlock_unlock(&irq->lock);
+    clock();
+    spinlock_lock(&irq->lock);
+    /* acknowledge tick */
+    *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))
+        = 0;
+}
 /** Initialize basic tables for exception dispatching
  * and starts the timer.
  */
 ,7 → 132,16
 void interrupt_init(void)
 {
     irq_init(IRQ_COUNT, IRQ_COUNT);
-    machine_timer_irq_start();
+    irq_initialize(&gxemul_timer_irq);
+    gxemul_timer_irq.devno = device_assign_devno();
+    gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
+    gxemul_timer_irq.claim = gxemul_timer_claim;
+    gxemul_timer_irq.handler = gxemul_timer_irq_handler;
+    irq_register(&gxemul_timer_irq);
+    gxemul_timer_start(GXEMUL_TIMER_FREQ);
 }
 /** @}

 /branches/network/kernel/arch/arm32/src/drivers/gxemul.c
 ,361 → 33,19
  *  @brief GXemul drivers.
  */
-#include <interrupt.h>
-#include <ipc/irq.h>
-#include <console/chardev.h>
 #include <arch/drivers/gxemul.h>
-#include <console/console.h>
-#include <sysinfo/sysinfo.h>
-#include <print.h>
-#include <ddi/device.h>
 #include <mm/page.h>
-#include <arch/machine.h>
-#include <arch/debug/print.h>
-/* Addresses of devices. */
-#define GXEMUL_VIDEORAM            0x10000000
-#define GXEMUL_KBD                 0x10000000
-#define GXEMUL_HALT_OFFSET         0x10
-#define GXEMUL_RTC                 0x15000000
-#define GXEMUL_RTC_FREQ_OFFSET     0x100
-#define GXEMUL_RTC_ACK_OFFSET      0x110
-#define GXEMUL_IRQC                0x16000000
-#define GXEMUL_IRQC_MASK_OFFSET    0x4
-#define GXEMUL_IRQC_UNMASK_OFFSET  0x8
-#define GXEMUL_MP                  0x11000000
-#define GXEMUL_MP_MEMSIZE_OFFSET   0x0090
-#define GXEMUL_FB                  0x12000000
+void *gxemul_kbd;
+void *gxemul_rtc;
+void *gxemul_irqc;
-/* IRQs */
-#define GXEMUL_KBD_IRQ      2
-#define GXEMUL_TIMER_IRQ    4
-static gxemul_hw_map_t gxemul_hw_map;
-static chardev_t console;
-static irq_t gxemul_console_irq;
-static irq_t gxemul_timer_irq;
-static bool hw_map_init_called = false;
-static void gxemul_kbd_enable(chardev_t *dev);
-static void gxemul_kbd_disable(chardev_t *dev);
-static void gxemul_write(chardev_t *dev, const char ch);
-static char gxemul_do_read(chardev_t *dev);
-static chardev_operations_t gxemul_ops = {
-    .resume = gxemul_kbd_enable,
-    .suspend = gxemul_kbd_disable,
-    .write = gxemul_write,
-    .read = gxemul_do_read,
-};
-/** Returns the mask of active interrupts. */
-static inline uint32_t gxemul_irqc_get_sources(void)
+void gxemul_init(void)
 {
-    return *((uint32_t *) gxemul_hw_map.irqc);
+    gxemul_kbd = (void *) hw_map(GXEMUL_KBD_ADDRESS, PAGE_SIZE);
+    gxemul_rtc = (void *) hw_map(GXEMUL_RTC_ADDRESS, PAGE_SIZE);
+    gxemul_irqc = (void *) hw_map(GXEMUL_IRQC_ADDRESS, PAGE_SIZE);
 }
-/** Masks interrupt.
- *
- * @param irq interrupt number
- */
-static inline void gxemul_irqc_mask(uint32_t irq)
-{
-    *((uint32_t *) gxemul_hw_map.irqc_mask) = irq;
-}
-/** Unmasks interrupt.
- *
- * @param irq interrupt number
- */
-static inline void gxemul_irqc_unmask(uint32_t irq)
-{
-    *((uint32_t *) gxemul_hw_map.irqc_unmask) = irq;
-}
-/** Initializes #gxemul_hw_map. */
-void gxemul_hw_map_init(void)
-{
-    gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE);
-    gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE);
-    gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE);
-    gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE);
-    gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET;
-    gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET;
-    gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET;
-    gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc +
-        GXEMUL_IRQC_UNMASK_OFFSET;
-    hw_map_init_called = true;
-}
-/** Putchar that works with gxemul.
- *
- * @param dev Not used.
- * @param ch Characted to be printed.
- */
-static void gxemul_write(chardev_t *dev, const char ch)
-{
-    *((char *) gxemul_hw_map.videoram) = ch;
-}
-/** Enables gxemul keyboard (interrupt unmasked).
- *
- * @param dev Not used.
- *
- * Called from getc().
- */
-static void gxemul_kbd_enable(chardev_t *dev)
-{
-    gxemul_irqc_unmask(GXEMUL_KBD_IRQ);
-}
-/** Disables gxemul keyboard (interrupt masked).
- *
- * @param dev not used
- *
- * Called from getc().
- */
-static void gxemul_kbd_disable(chardev_t *dev)
-{
-    gxemul_irqc_mask(GXEMUL_KBD_IRQ);
-}
-/** Read character using polling, assume interrupts disabled.
- *
- *  @param dev Not used.
- */
-static char gxemul_do_read(chardev_t *dev)
-{
-    char ch;
-    while (1) {
-        ch = *((volatile char *) gxemul_hw_map.kbd);
-        if (ch) {
-            if (ch == '\r')
-                return '\n';
-            if (ch == 0x7f)
-                return '\b';
-            return ch;
-        }
-    }
-}
-/** Process keyboard interrupt.
- *
- *  @param irq IRQ information.
- *  @param arg Not used.
- */
-static void gxemul_irq_handler(irq_t *irq, void *arg, ...)
-{
-    if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) {
-        ipc_irq_send_notif(irq);
-    } else {
-        char ch = 0;
-        ch = *((char *) gxemul_hw_map.kbd);
-        if (ch == '\r') {
-            ch = '\n';
-        }
-        if (ch == 0x7f) {
-            ch = '\b';
-        }
-        chardev_push_character(&console, ch);
-    }
-}
-static irq_ownership_t gxemul_claim(void)
-{
-    return IRQ_ACCEPT;
-}
-/** Acquire console back for kernel. */
-void gxemul_grab_console(void)
-{
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&gxemul_console_irq.lock);
-    gxemul_console_irq.notif_cfg.notify = false;
-    spinlock_unlock(&gxemul_console_irq.lock);
-    interrupts_restore(ipl);
-}
-/** Return console to userspace. */
-void gxemul_release_console(void)
-{
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&gxemul_console_irq.lock);
-    if (gxemul_console_irq.notif_cfg.answerbox) {
-        gxemul_console_irq.notif_cfg.notify = true;
-    }
-    spinlock_unlock(&gxemul_console_irq.lock);
-    interrupts_restore(ipl);
-}
-/** Initializes console object representing gxemul console.
- *
- *  @param devno device number.
- */
-void gxemul_console_init(devno_t devno)
-{
-    chardev_initialize("gxemul_console", &console, &gxemul_ops);
-    stdin = &console;
-    stdout = &console;
-    irq_initialize(&gxemul_console_irq);
-    gxemul_console_irq.devno = devno;
-    gxemul_console_irq.inr = GXEMUL_KBD_IRQ;
-    gxemul_console_irq.claim = gxemul_claim;
-    gxemul_console_irq.handler = gxemul_irq_handler;
-    irq_register(&gxemul_console_irq);
-    gxemul_irqc_unmask(GXEMUL_KBD_IRQ);
-    sysinfo_set_item_val("kbd", NULL, true);
-    sysinfo_set_item_val("kbd.devno", NULL, devno);
-    sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
-    sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd);
-}
-/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
- *
- * @param frequency Interrupts frequency (0 disables RTC).
- */
-static void gxemul_timer_start(uint32_t frequency)
-{
-    *((uint32_t*) gxemul_hw_map.rtc_freq) = frequency;
-}
-static irq_ownership_t gxemul_timer_claim(void)
-{
-    return IRQ_ACCEPT;
-}
-/** Timer interrupt handler.
- *
- * @param irq Interrupt information.
- * @param arg Not used.
- */
-static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...)
-{
-    /*
-    * We are holding a lock which prevents preemption.
-    * Release the lock, call clock() and reacquire the lock again.
-    */
-    spinlock_unlock(&irq->lock);
-    clock();
-    spinlock_lock(&irq->lock);
-    /* acknowledge tick */
-    *((uint32_t*) gxemul_hw_map.rtc_ack) = 0;
-}
-/** Initializes and registers timer interrupt handler. */
-static void gxemul_timer_irq_init(void)
-{
-    irq_initialize(&gxemul_timer_irq);
-    gxemul_timer_irq.devno = device_assign_devno();
-    gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
-    gxemul_timer_irq.claim = gxemul_timer_claim;
-    gxemul_timer_irq.handler = gxemul_timer_irq_handler;
-    irq_register(&gxemul_timer_irq);
-}
-/** Starts timer.
- *
- * Initiates regular timer interrupts after initializing
- * corresponding interrupt handler.
- */
-void gxemul_timer_irq_start(void)
-{
-    gxemul_timer_irq_init();
-    gxemul_timer_start(GXEMUL_TIMER_FREQ);
-}
-/** Returns the size of emulated memory.
- *
- * @return Size in bytes.
- */
-size_t gxemul_get_memory_size(void)
-{
-    return  *((int *) (GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET));
-}
-/** Prints a character.
- *
- *  @param ch Character to be printed.
- */
-void gxemul_debug_putc(char ch)
-{
-    char *addr = 0;
-    if (!hw_map_init_called) {
-        addr = (char *) GXEMUL_KBD;
-    } else {
-        addr = (char *) gxemul_hw_map.videoram;
-    }
-    *(addr) = ch;
-}
-/** Stops gxemul. */
-void gxemul_cpu_halt(void)
-{
-    char * addr = 0;
-    if (!hw_map_init_called) {
-        addr = (char *) GXEMUL_KBD;
-    } else {
-        addr = (char *) gxemul_hw_map.videoram;
-    }
-    *(addr + GXEMUL_HALT_OFFSET) = '\0';
-}
-/** Gxemul specific interrupt exception handler.
- *
- * Determines sources of the interrupt from interrupt controller and
- * calls high-level handlers for them.
- *
- * @param exc_no Interrupt exception number.
- * @param istate Saved processor state.
- */
-void gxemul_irq_exception(int exc_no, istate_t *istate)
-{
-    uint32_t sources = gxemul_irqc_get_sources();
-    int i;
-    for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) {
-        if (sources & (1 << i)) {
-            irq_t *irq = irq_dispatch_and_lock(i);
-            if (irq) {
-                /* The IRQ handler was found. */
-                irq->handler(irq, irq->arg);
-                spinlock_unlock(&irq->lock);
-            } else {
-                /* Spurious interrupt.*/
-                dprintf("cpu%d: spurious interrupt (inum=%d)\n",
-                    CPU->id, i);
-            }
-        }
-    }
-}
-/** Returns address of framebuffer device.
- *
- *  @return Address of framebuffer device.
- */
-uintptr_t gxemul_get_fb_address(void)
-{
-    return (uintptr_t) GXEMUL_FB;
-}
 /** @}
  */

 /branches/network/kernel/arch/arm32/src/start.S
 ,30 → 40,12
     mrs r3, cpsr
     bic r3, r3, #0x1f
     orr r3, r3, #0x13
-    msr cpsr_c, r3
+    msr cpsr_c, r3
     ldr sp, =temp_stack
-    cmp r2, #0
-    beq bootinfo_end
-    ldr r3, =bootinfo
-    bootinfo_loop:
-        ldr r4, [r1]
-        str r4, [r3]
-        add r1, r1, #4
-        add r3, r3, #4
-        add r2, r2, #-4
-        cmp r2, #0
-        bne bootinfo_loop
-    bootinfo_end:
     bl arch_pre_main
     bl main_bsp
     .space TEMP_STACK_SIZE
 ,4 → 56,3
 supervisor_sp:
     .space 4

 /branches/network/kernel/arch/ppc32/_link.ld.in
 ,11 → 1,11
 /** PPC32 linker script
  *
  * umapped section:
- *  kernel text
- *  kernel data
+ *  kernel text
+ *  kernel data
  * mapped section:
- *  kernel text
- *  kernel data
+ *  kernel text
+ *  kernel data
  *
  */
 ,7 → 27,7
         unmapped_kdata_start = .;
     }
-    .mapped PA2KA(BOOT_OFFSET): AT (BOOT_OFFSET) {
+    .mapped PA2KA(BOOT_OFFSET): AT (BOOT_OFFSET) {
         ktext_start = .;
         *(K_TEXT_START);
         *(.text);
 ,22 → 37,22
         *(K_DATA_START);
         *(.rodata);
         *(.rodata.*);
-        *(.data);       /* initialized data */
+        *(.data);       /* initialized data */
         *(.sdata);
         *(.sdata2);
         *(.sbss);
         hardcoded_ktext_size = .;
-        LONG(ktext_end - ktext_start);
+        LONG(ktext_end - ktext_start);
         hardcoded_kdata_size = .;
         LONG(kdata_end - kdata_start);
         hardcoded_load_address = .;
         LONG(PA2KA(BOOT_OFFSET));
-        *(.bss);        /* uninitialized static variables */
-        *(COMMON);      /* global variables */
+        *(.bss);        /* uninitialized static variables */
+        *(COMMON);      /* global variables */
         symbol_table = .;
-        *(symtab.*);            /* Symbol table, must be LAST symbol!*/
+        *(symtab.*);    /* Symbol table, must be LAST symbol!*/
         kdata_end = .;
     }
 }

 /branches/network/kernel/arch/ppc32/include/asm/regname.h
 ,15 → 211,19
 #define dbat2l  541
 #define dbat3u  542
 #define dbat3l  543
+#define tlbmiss 980
+#define ptehi   981
+#define ptelo   982
 #define hid0    1008
 /* MSR bits */
-#define msr_ir  (1 << 4)
-#define msr_dr  (1 << 5)
+#define msr_dr  (1 << 4)
+#define msr_ir  (1 << 5)
 #define msr_pr  (1 << 14)
 #define msr_ee  (1 << 15)
 /* HID0 bits */
+#define hid0_sten   (1 << 24)
 #define hid0_ice    (1 << 15)
 #define hid0_dce    (1 << 14)
 #define hid0_icfi   (1 << 11)

 /branches/network/kernel/arch/ppc32/include/exception.h
 ,6 → 36,7
 #define KERN_ppc32_EXCEPTION_H_
 #include <arch/types.h>
+#include <arch/regutils.h>
 typedef struct {
     uint32_t r0;
 ,6 → 75,7
     uint32_t lr;
     uint32_t ctr;
     uint32_t xer;
+    uint32_t dar;
     uint32_t r12;
     uint32_t sp;
 } istate_t;
 ,11 → 86,10
 }
 /** Return true if exception happened while in userspace */
-#include <panic.h>
 static inline int istate_from_uspace(istate_t *istate)
 {
-    panic("istate_from_uspace not yet implemented");
-    return 0;
+    /* true if privilege level PR (copied from MSR) == 1 */
+    return (istate->srr1 & MSR_PR) != 0;
 }
 static inline unative_t istate_get_pc(istate_t *istate)

 /branches/network/kernel/arch/ppc32/include/regutils.h
 ,0 → 1,45
+/*
+ * Copyright (c) 2008 Jiri Svoboda
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup ppc32
+ * @{
+ */
+/**
+ * @file
+ * @brief Utilities for convenient manipulation with ppc32 registers.
+ */
+#ifndef KERN_ppc32_REGUTILS_H_
+#define KERN_ppc32_REGUTILS_H_
+#define MSR_PR (1 << 14)
+#endif
+/** @}
+ */

 /branches/network/kernel/arch/ppc32/include/types.h
 ,6 → 57,9
 typedef uint32_t unative_t;
 typedef int32_t native_t;
+typedef struct {
+} fncptr_t;
 /**< Formats for uintptr_t, size_t, count_t and index_t */
 #define PRIp "x"
 #define PRIs "u"
 ,11 → 87,13
 /** Page Table Entry. */
 typedef struct {
-    unsigned p : 1;       /**< Present bit. */
-    unsigned a : 1;       /**< Accessed bit. */
-    unsigned g : 1;       /**< Global bit. */
-    unsigned valid : 1;   /**< Valid content even if not present. */
-    unsigned pfn : 20;    /**< Physical frame number. */
+    unsigned present : 1;             /**< Present bit. */
+    unsigned page_write_through : 1;  /**< Write thought caching. */
+    unsigned page_cache_disable : 1;  /**< No caching. */
+    unsigned accessed : 1;            /**< Accessed bit. */
+    unsigned global : 1;              /**< Global bit. */
+    unsigned valid : 1;               /**< Valid content even if not present. */
+    unsigned pfn : 20;                /**< Physical frame number. */
 } pte_t;
 #endif

 /branches/network/kernel/arch/ppc32/include/boot/boot.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32
+/** @addtogroup ppc32
  * @{
  */
 /** @file
 ,21 → 35,24
 #ifndef KERN_ppc32_BOOT_H_
 #define KERN_ppc32_BOOT_H_
-#define BOOT_OFFSET     0x8000
+#define BOOT_OFFSET  0x8000
 /* Temporary stack size for boot process */
-#define TEMP_STACK_SIZE 0x1000
+#define TEMP_STACK_SIZE  0x1000
-#define TASKMAP_MAX_RECORDS 32
-#define MEMMAP_MAX_RECORDS 32
+#define TASKMAP_MAX_RECORDS  32
+#define MEMMAP_MAX_RECORDS   32
 #ifndef __ASM__
+#define BOOTINFO_TASK_NAME_BUFLEN 32
 #include <arch/types.h>
 typedef struct {
     uintptr_t addr;
     uint32_t size;
+    char name[BOOTINFO_TASK_NAME_BUFLEN];
 } utask_t;
 typedef struct {
 ,13 → 82,13
 typedef struct {
     uintptr_t addr;
     unsigned int size;
-} keyboard_t;
+} macio_t;
 typedef struct {
     memmap_t memmap;
     taskmap_t taskmap;
     screen_t screen;
-    keyboard_t keyboard;
+    macio_t macio;
 } bootinfo_t;
 extern bootinfo_t bootinfo;

 /branches/network/kernel/arch/ppc32/include/arch.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32
+/** @addtogroup ppc32
  * @{
  */
 /** @file
 ,7 → 35,7
 #ifndef KERN_ppc32_ARCH_H_
 #define KERN_ppc32_ARCH_H_
-#include <arch/drivers/cuda.h>
+extern void arch_pre_main(void);
 #endif

 /branches/network/kernel/arch/ppc32/include/asm.h
 ,6 → 36,7
 #define KERN_ppc32_ASM_H_
 #include <arch/types.h>
+#include <typedefs.h>
 #include <config.h>
 /** Enable interrupts.
 ,6 → 150,36
 extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
+static inline void pio_write_8(ioport8_t *port, uint8_t v)
+{
+    *port = v;
+}
+static inline void pio_write_16(ioport16_t *port, uint16_t v)
+{
+    *port = v;
+}
+static inline void pio_write_32(ioport32_t *port, uint32_t v)
+{
+    *port = v;
+}
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
+    return *port;
+}
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    return *port;
+}
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    return *port;
+}
 #endif
 /** @}

 /branches/network/kernel/arch/ppc32/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32mm
+/** @addtogroup ppc32mm
  * @{
  */
 /** @file
 ,13 → 35,13
 #ifndef KERN_ppc32_FRAME_H_
 #define KERN_ppc32_FRAME_H_
-#define FRAME_WIDTH     12  /* 4K */
-#define FRAME_SIZE      (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  12  /* 4K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifdef KERNEL
 #ifndef __ASM__
-#include <arch/types.h>
+#include <arch/types.h>
 extern uintptr_t last_frame;

 /branches/network/kernel/arch/ppc32/include/mm/page.h
 ,7 → 120,7
 /* Macros for querying the last-level PTEs. */
 #define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
-#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
+#define PTE_PRESENT_ARCH(pte)           ((pte)->present != 0)
 #define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
 #define PTE_WRITABLE_ARCH(pte)          1
 #define PTE_EXECUTABLE_ARCH(pte)        1
 ,13 → 134,13
 {
     pte_t *p = &pt[i];
-    return ((1 << PAGE_CACHEABLE_SHIFT) |
-        ((!p->p) << PAGE_PRESENT_SHIFT) |
+    return (((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT) |
+        ((!p->present) << PAGE_PRESENT_SHIFT) |
         (1 << PAGE_USER_SHIFT) |
         (1 << PAGE_READ_SHIFT) |
         (1 << PAGE_WRITE_SHIFT) |
         (1 << PAGE_EXEC_SHIFT) |
-        (p->g << PAGE_GLOBAL_SHIFT));
+        (p->global << PAGE_GLOBAL_SHIFT));
 }
 static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
 ,8 → 147,9
 {
     pte_t *p = &pt[i];
-    p->p = !(flags & PAGE_NOT_PRESENT);
-    p->g = (flags & PAGE_GLOBAL) != 0;
+    p->page_cache_disable = !(flags & PAGE_CACHEABLE);
+    p->present = !(flags & PAGE_NOT_PRESENT);
+    p->global = (flags & PAGE_GLOBAL) != 0;
     p->valid = 1;
 }

 /branches/network/kernel/arch/ppc32/include/mm/tlb.h
 ,6 → 39,11
 #include <arch/types.h>
 #include <typedefs.h>
+#define WIMG_GUARDED    0x01
+#define WIMG_COHERENT   0x02
+#define WIMG_NO_CACHE   0x04
+#define WIMG_WRITETHRU  0x08
 typedef struct {
     unsigned v : 1;          /**< Valid */
     unsigned vsid : 24;      /**< Virtual Segment ID */
 ,9 → 58,27
     unsigned pp : 2;         /**< Page protection */
 } phte_t;
+typedef struct {
+    unsigned v : 1;
+    unsigned vsid : 24;
+    unsigned reserved0 : 1;
+    unsigned api : 6;
+} ptehi_t;
+typedef struct {
+    unsigned rpn : 20;
+    unsigned xpn : 3;
+    unsigned reserved0 : 1;
+    unsigned c : 1;
+    unsigned wimg : 4;
+    unsigned x : 1;
+    unsigned pp : 2;
+} ptelo_t;
+extern void pht_init(void);
 extern void pht_refill(int n, istate_t *istate);
-extern bool pht_real_refill(int n, istate_t *istate) __attribute__ ((section("K_UNMAPPED_TEXT_START")));
-extern void pht_init(void);
+extern bool pht_refill_real(int n, istate_t *istate) __attribute__ ((section("K_UNMAPPED_TEXT_START")));
+extern void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) __attribute__ ((section("K_UNMAPPED_TEXT_START")));
 #endif

 /branches/network/kernel/arch/ppc32/include/barrier.h
 ,6 → 55,7
         "dcbst 0, %0\n"
         "sync\n"
         "icbi 0, %0\n"
+        "sync\n"
         "isync\n"
         :: "r" (addr)
     );
 ,7 → 77,10
         asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
     }
-    asm volatile ("isync");
+    asm volatile (
+        "sync\n"
+        "isync\n"
+    );
 }
 #endif

 /branches/network/kernel/arch/ppc32/include/drivers/cuda.h
 ,10 → 38,8
 #include <arch/types.h>
 #include <typedefs.h>
-extern void cuda_init(devno_t devno, uintptr_t base, size_t size);
+extern void cuda_init(uintptr_t base, size_t size);
 extern int cuda_get_scancode(void);
-extern void cuda_grab(void);
-extern void cuda_release(void);
 #endif

 /branches/network/kernel/arch/ppc32/Makefile.inc
 ,10 → 29,6
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf32-powerpc
 BFD_ARCH = powerpc:common
 BFD = binary
 ,44 → 41,22
 DEFS += -D__32_BITS__
-## Own configuration directives
-#
-CONFIG_FB = y
-## Compile with hierarchical page tables support.
-#
-CONFIG_PAGE_PT = y
-DEFS += -DCONFIG_PAGE_PT
-## Compile with support for address space identifiers.
-#
-CONFIG_ASID = y
-CONFIG_ASID_FIFO = y
-## Compile with support for software integer division.
-#
-CONFIG_SOFTINT = y
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/debug/panic.s \
-    arch/$(ARCH)/src/fpu_context.S \
-    arch/$(ARCH)/src/boot/boot.S \
-    arch/$(ARCH)/src/ppc32.c \
-    arch/$(ARCH)/src/dummy.s \
-    arch/$(ARCH)/src/exception.S \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/proc/scheduler.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/cuda.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/drivers/pic.c
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/debug/panic.s \
+    arch/$(KARCH)/src/fpu_context.S \
+    arch/$(KARCH)/src/boot/boot.S \
+    arch/$(KARCH)/src/ppc32.c \
+    arch/$(KARCH)/src/dummy.s \
+    arch/$(KARCH)/src/exception.S \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/proc/scheduler.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/drivers/cuda.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/drivers/pic.c

 /branches/network/kernel/arch/ppc32/src/exception.S
 ,7 → 60,7
 :
-    subi sp, sp, 160
+    subi sp, sp, 164
     stw r0, 8(sp)
     stw r2, 12(sp)
     stw r3, 16(sp)
 ,11 → 109,14
     mfxer r12
     stw r12, 148(sp)
-    mfsprg1 r12
+    mfdar r12
     stw r12, 152(sp)
+    mfsprg1 r12
+    stw r12, 156(sp)
     mfsprg2 r12
-    stw r12, 156(sp)
+    stw r12, 160(sp)
 .endm
 .org 0x100
 ,16 → 140,7
 exc_data_storage:
     CONTEXT_STORE
-    li r3, 2
-    mr r4, sp
-    addi r4, r4, 8
-    bl pht_real_refill
-    cmpwi r3, 0
-    bne iret_real
-    li r3, 2
-    b jump_to_kernel
+    b data_storage
 .org 0x400
 .global exc_instruction_storage
 ,17 → 147,8
 exc_instruction_storage:
     CONTEXT_STORE
-    li r3, 3
-    mr r4, sp
-    addi r4, r4, 8
-    bl pht_real_refill
-    cmpwi r3, 0
-    bne iret_real
+    b instruction_storage
-    li r3, 3
-    b jump_to_kernel
 .org 0x500
 .global exc_external
 exc_external:
 ,7 → 208,7
 .org 0xc00
 .global exc_syscall
 exc_syscall:
-    CONTEXT_STORE
+    CONTEXT_STORE
     b jump_to_kernel_syscall
 ,7 → 220,63
     li r3, 12
     b jump_to_kernel
+.org 0x1000
+.global exc_itlb_miss
+exc_itlb_miss:
+    CONTEXT_STORE
+    b tlb_miss
+.org 0x1100
+.global exc_dtlb_miss_load
+exc_dtlb_miss_load:
+    CONTEXT_STORE
+    b tlb_miss
+.org 0x1200
+.global exc_dtlb_miss_store
+exc_dtlb_miss_store:
+    CONTEXT_STORE
+    b tlb_miss
 .org 0x4000
+data_storage:
+    li r3, 2
+    mr r4, sp
+    addi r4, r4, 8
+    bl pht_refill_real
+    cmpwi r3, 0
+    bne iret_real
+    li r3, 2
+    b jump_to_kernel
+instruction_storage:
+    li r3, 3
+    mr r4, sp
+    addi r4, r4, 8
+    bl pht_refill_real
+    cmpwi r3, 0
+    bne iret_real
+    li r3, 3
+    b jump_to_kernel
+tlb_miss:
+    li r3, 16
+    mfspr r4, tlbmiss
+    mfspr r5, ptehi
+    mfspr r6, ptelo
+    mr r7, sp
+    addi r7, r7, 20
+    bl tlb_refill_real
+    b iret_real
 jump_to_kernel:
     lis r12, iret@ha
     addi r12, r12, iret@l
 ,7 → 313,6
     rfi
 iret_real:
     lwz r0, 8(sp)
     lwz r2, 12(sp)
     lwz r3, 16(sp)
 ,7 → 362,7
     lwz r12, 148(sp)
     mtxer r12
-    lwz r12, 152(sp)
-    lwz sp, 156(sp)
+    lwz r12, 156(sp)
+    lwz sp, 160(sp)
     rfi

 /branches/network/kernel/arch/ppc32/src/asm.S
 ,9 → 66,9
     mr sp, r4
-    # %r3 is defined to hold pcb_ptr - set it to 0
+    # %r6 is defined to hold pcb_ptr - set it to 0
-    xor r3, r3, r3
+    xor r6, r6, r6
     # jump to userspace
 ,8 → 131,8
     lwz r12, 148(sp)
     mtxer r12
-    lwz r12, 152(sp)
-    lwz sp, 156(sp)
+    lwz r12, 156(sp)
+    lwz sp, 160(sp)
     rfi
 ,8 → 197,8
     lwz r12, 148(sp)
     mtxer r12
-    lwz r12, 152(sp)
-    lwz sp, 156(sp)
+    lwz r12, 156(sp)
+    lwz sp, 160(sp)
     rfi

 /branches/network/kernel/arch/ppc32/src/boot/boot.S
 ,7 → 33,7
 .global kernel_image_start
 kernel_image_start:
     # load temporal kernel stack
     lis sp, kernel_stack@ha
 ,7 → 52,7
     beq bootinfo_end
     addis r3, r3, 0x8000
     lis r31, bootinfo@ha
     addi r31, r31, bootinfo@l  # r31 = bootinfo

 /branches/network/kernel/arch/ppc32/src/ppc32.c
 ,24 → 42,27
 #include <userspace.h>
 #include <proc/uarg.h>
 #include <console/console.h>
-#include <ddi/device.h>
 #include <ddi/irq.h>
 #include <arch/drivers/pic.h>
+#include <macros.h>
+#include <string.h>
-#define IRQ_COUNT   64
+#define IRQ_COUNT  64
 bootinfo_t bootinfo;
+/** Performs ppc32-specific initialization before main_bsp() is called. */
 void arch_pre_main(void)
 {
-    /* Setup usermode */
     init.cnt = bootinfo.taskmap.count;
     uint32_t i;
-    for (i = 0; i < bootinfo.taskmap.count; i++) {
+    for (i = 0; i < min3(bootinfo.taskmap.count, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
         init.tasks[i].addr = PA2KA(bootinfo.taskmap.tasks[i].addr);
         init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
+        strncpy(init.tasks[i].name, bootinfo.taskmap.tasks[i].name,
+            CONFIG_TASK_NAME_BUFLEN);
     }
 }
 ,35 → 78,50
 void arch_post_mm_init(void)
 {
     if (config.cpu_active == 1) {
+#ifdef CONFIG_FB
         /* Initialize framebuffer */
-        unsigned int visual;
-        switch (bootinfo.screen.bpp) {
-        case 8:
-            visual = VISUAL_INDIRECT_8;
-            break;
-        case 16:
-            visual = VISUAL_RGB_5_5_5;
-            break;
-        case 24:
-            visual = VISUAL_RGB_8_8_8;
-            break;
-        case 32:
-            visual = VISUAL_RGB_0_8_8_8;
-            break;
-        default:
-            panic("Unsupported bits per pixel");
+        if (bootinfo.screen.addr) {
+            unsigned int visual;
+            switch (bootinfo.screen.bpp) {
+            case 8:
+                visual = VISUAL_INDIRECT_8;
+                break;
+            case 16:
+                visual = VISUAL_RGB_5_5_5;
+                break;
+            case 24:
+                visual = VISUAL_RGB_8_8_8;
+                break;
+            case 32:
+                visual = VISUAL_RGB_0_8_8_8;
+                break;
+            default:
+                panic("Unsupported bits per pixel.");
+            }
+            fb_properties_t prop = {
+                .addr = bootinfo.screen.addr,
+                .offset = 0,
+                .x = bootinfo.screen.width,
+                .y = bootinfo.screen.height,
+                .scan = bootinfo.screen.scanline,
+                .visual = visual,
+            };
+            fb_init(&prop);
         }
-        fb_init(bootinfo.screen.addr, bootinfo.screen.width, bootinfo.screen.height, bootinfo.screen.scanline, visual);
+#endif
         /* Initialize IRQ routing */
         irq_init(IRQ_COUNT, IRQ_COUNT);
-        /* Initialize PIC */
-        pic_init(bootinfo.keyboard.addr, PAGE_SIZE);
-        /* Initialize I/O controller */
-        cuda_init(device_assign_devno(), bootinfo.keyboard.addr + 0x16000, 2 * PAGE_SIZE);
+        if (bootinfo.macio.addr) {
+            /* Initialize PIC */
+            pic_init(bootinfo.macio.addr, PAGE_SIZE);
+            /* Initialize I/O controller */
+            cuda_init(bootinfo.macio.addr + 0x16000, 2 * PAGE_SIZE);
+        }
         /* Merge all zones to 1 big zone */
         zone_merge_all();
 ,11 → 146,13
 void userspace(uspace_arg_t *kernel_uarg)
 {
-    userspace_asm((uintptr_t) kernel_uarg->uspace_uarg, (uintptr_t) kernel_uarg->uspace_stack + THREAD_STACK_SIZE - SP_DELTA, (uintptr_t) kernel_uarg->uspace_entry);
+    userspace_asm((uintptr_t) kernel_uarg->uspace_uarg,
+        (uintptr_t) kernel_uarg->uspace_stack +
+        THREAD_STACK_SIZE - SP_DELTA,
+        (uintptr_t) kernel_uarg->uspace_entry);
     /* Unreachable */
-    for (;;)
-        ;
+    while (true);
 }
 /** Acquire console back for kernel
 ,7 → 160,9
  */
 void arch_grab_console(void)
 {
-    cuda_grab();
+#ifdef CONFIG_FB
+    fb_redraw();
+#endif
 }
 /** Return console to userspace
 ,8 → 170,21
  */
 void arch_release_console(void)
 {
-    cuda_release();
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/ppc32/src/mm/tlb.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32mm
+/** @addtogroup ppc32mm
  * @{
  */
 /** @file
 ,12 → 35,22
 #include <mm/tlb.h>
 #include <arch/mm/tlb.h>
 #include <arch/interrupt.h>
+#include <interrupt.h>
 #include <mm/as.h>
 #include <arch.h>
 #include <print.h>
+#include <macros.h>
 #include <symtab.h>
+static unsigned int seed = 10;
+static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
+#define TLB_FLUSH \
+    "tlbie %0\n" \
+    "addi %0, %0, 0x1000\n"
 /** Try to find PTE for faulting address
  *
  * Try to find PTE for faulting address.
 ,7 → 75,7
      * Check if the mapping exists in page tables.
      */
     pte_t *pte = page_mapping_find(as, badvaddr);
-    if ((pte) && (pte->p)) {
+    if ((pte) && (pte->present)) {
         /*
          * Mapping found in page tables.
          * Immediately succeed.
 ,7 → 97,7
              */
             page_table_lock(as, lock);
             pte = page_mapping_find(as, badvaddr);
-            ASSERT((pte) && (pte->p));
+            ASSERT((pte) && (pte->present));
             *pfrc = 0;
             return pte;
         case AS_PF_DEFER:
 ,11 → 106,10
             return NULL;
         case AS_PF_FAULT:
             page_table_lock(as, lock);
-            printf("Page fault.\n");
             *pfrc = rc;
             return NULL;
         default:
-            panic("unexpected rc (%d)\n", rc);
+            panic("Unexpected rc (%d).", rc);
         }
     }
 }
 ,21 → 117,20
 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
 {
-    char *symbol = "";
-    char *sym2 = "";
+    char *symbol;
+    char *sym2;
-    char *s = get_symtab_entry(istate->pc);
-    if (s)
-        symbol = s;
-    s = get_symtab_entry(istate->lr);
-    if (s)
-        sym2 = s;
-    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr,
+    symbol = symtab_fmt_name_lookup(istate->pc);
+    sym2 = symtab_fmt_name_lookup(istate->lr);
+    fault_if_from_uspace(istate,
+        "PHT Refill Exception on %p.", badvaddr);
+    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
         istate->pc, symbol, sym2);
 }
-static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)
+static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
 {
     uint32_t page = (vaddr >> 12) & 0xffff;
     uint32_t api = (vaddr >> 22) & 0x3f;
 ,11 → 156,12
     uint32_t i;
     bool found = false;
-    /* Find unused or colliding
-       PTE in PTEG */
+    /* Find colliding PTE in PTEG */
     for (i = 0; i < 8; i++) {
-        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) &&
-            (phte[base + i].api == api))) {
+        if ((phte[base + i].v)
+            && (phte[base + i].vsid == vsid)
+            && (phte[base + i].api == api)
+            && (phte[base + i].h == 0)) {
             found = true;
             break;
         }
 ,86 → 168,25
     }
     if (!found) {
-        /* Secondary hash (not) */
-        uint32_t base2 = (~hash & 0x3ff) << 3;
-        /* Find unused or colliding
-           PTE in PTEG */
+        /* Find unused PTE in PTEG */
         for (i = 0; i < 8; i++) {
-            if ((!phte[base2 + i].v) ||
-                ((phte[base2 + i].vsid == vsid) &&
-                (phte[base2 + i].api == api))) {
+            if (!phte[base + i].v) {
                 found = true;
-                base = base2;
-                h = 1;
                 break;
             }
         }
-        if (!found) {
-            // TODO: A/C precedence groups
-            i = page % 8;
-        }
     }
-    phte[base + i].v = 1;
-    phte[base + i].vsid = vsid;
-    phte[base + i].h = h;
-    phte[base + i].api = api;
-    phte[base + i].rpn = pfn;
-    phte[base + i].r = 0;
-    phte[base + i].c = 0;
-    phte[base + i].pp = 2; // FIXME
-}
-static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
-{
-    uint32_t page = (vaddr >> 12) & 0xffff;
-    uint32_t api = (vaddr >> 22) & 0x3f;
-    uint32_t vsid;
-    asm volatile (
-        "mfsrin %0, %1\n"
-        : "=r" (vsid)
-        : "r" (vaddr)
-    );
-    uint32_t sdr1;
-    asm volatile (
-        "mfsdr1 %0\n"
-        : "=r" (sdr1)
-    );
-    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
-    /* Primary hash (xor) */
-    uint32_t h = 0;
-    uint32_t hash = vsid ^ page;
-    uint32_t base = (hash & 0x3ff) << 3;
-    uint32_t i;
-    bool found = false;
-    /* Find unused or colliding
-       PTE in PTEG */
-    for (i = 0; i < 8; i++) {
-        if ((!phte_physical[base + i].v) ||
-            ((phte_physical[base + i].vsid == vsid) &&
-            (phte_physical[base + i].api == api))) {
-            found = true;
-            break;
-        }
-    }
     if (!found) {
         /* Secondary hash (not) */
         uint32_t base2 = (~hash & 0x3ff) << 3;
-        /* Find unused or colliding
-           PTE in PTEG */
+        /* Find colliding PTE in PTEG */
         for (i = 0; i < 8; i++) {
-            if ((!phte_physical[base2 + i].v) ||
-                ((phte_physical[base2 + i].vsid == vsid) &&
-                (phte_physical[base2 + i].api == api))) {
+            if ((phte[base2 + i].v)
+                && (phte[base2 + i].vsid == vsid)
+                && (phte[base2 + i].api == api)
+                && (phte[base2 + i].h == 1)) {
                 found = true;
                 base = base2;
                 h = 1;
 ,26 → 195,37
         }
         if (!found) {
-            // TODO: A/C precedence groups
-            i = page % 8;
+            /* Find unused PTE in PTEG */
+            for (i = 0; i < 8; i++) {
+                if (!phte[base2 + i].v) {
+                    found = true;
+                    base = base2;
+                    h = 1;
+                    break;
+                }
+            }
         }
+        if (!found)
+            i = RANDI(seed) % 8;
     }
-    phte_physical[base + i].v = 1;
-    phte_physical[base + i].vsid = vsid;
-    phte_physical[base + i].h = h;
-    phte_physical[base + i].api = api;
-    phte_physical[base + i].rpn = pfn;
-    phte_physical[base + i].r = 0;
-    phte_physical[base + i].c = 0;
-    phte_physical[base + i].pp = 2; // FIXME
+    phte[base + i].v = 1;
+    phte[base + i].vsid = vsid;
+    phte[base + i].h = h;
+    phte[base + i].api = api;
+    phte[base + i].rpn = pte->pfn;
+    phte[base + i].r = 0;
+    phte[base + i].c = 0;
+    phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
+    phte[base + i].pp = 2; // FIXME
 }
-/** Process Instruction/Data Storage Interrupt
+/** Process Instruction/Data Storage Exception
  *
- * @param n     Interrupt vector number.
- * @param istate    Interrupted register context.
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
 void pht_refill(int n, istate_t *istate)
 ,12 → 244,9
         lock = true;
     }
-    if (n == VECTOR_DATA_STORAGE) {
-        asm volatile (
-            "mfdar %0\n"
-            : "=r" (badvaddr)
-        );
-    } else
+    if (n == VECTOR_DATA_STORAGE)
+        badvaddr = istate->dar;
+    else
         badvaddr = istate->pc;
     page_table_lock(as, lock);
 ,12 → 266,12
             page_table_unlock(as, lock);
             return;
         default:
-            panic("Unexpected pfrc (%d)\n", pfrc);
+            panic("Unexpected pfrc (%d).", pfrc);
         }
     }
-    pte->a = 1; /* Record access to PTE */
-    pht_insert(badvaddr, pte->pfn);
+    pte->accessed = 1; /* Record access to PTE */
+    pht_insert(badvaddr, pte);
     page_table_unlock(as, lock);
     return;
 ,22 → 282,19
 }
-/** Process Instruction/Data Storage Interrupt in Real Mode
+/** Process Instruction/Data Storage Exception in Real Mode
  *
- * @param n     Interrupt vector number.
- * @param istate    Interrupted register context.
+ * @param n      Exception vector number.
+ * @param istate Interrupted register context.
  *
  */
-bool pht_real_refill(int n, istate_t *istate)
+bool pht_refill_real(int n, istate_t *istate)
 {
     uintptr_t badvaddr;
-    if (n == VECTOR_DATA_STORAGE) {
-        asm volatile (
-            "mfdar %0\n"
-            : "=r" (badvaddr)
-        );
-    } else
+    if (n == VECTOR_DATA_STORAGE)
+        badvaddr = istate->dar;
+    else
         badvaddr = istate->pc;
     uint32_t physmem;
 ,15 → 303,140
         : "=r" (physmem)
     );
-    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
-        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
-        return true;
+    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
+        return false;
+    uint32_t page = (badvaddr >> 12) & 0xffff;
+    uint32_t api = (badvaddr >> 22) & 0x3f;
+    uint32_t vsid;
+    asm volatile (
+        "mfsrin %0, %1\n"
+        : "=r" (vsid)
+        : "r" (badvaddr)
+    );
+    uint32_t sdr1;
+    asm volatile (
+        "mfsdr1 %0\n"
+        : "=r" (sdr1)
+    );
+    phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
+    /* Primary hash (xor) */
+    uint32_t h = 0;
+    uint32_t hash = vsid ^ page;
+    uint32_t base = (hash & 0x3ff) << 3;
+    uint32_t i;
+    bool found = false;
+    /* Find colliding PTE in PTEG */
+    for (i = 0; i < 8; i++) {
+        if ((phte_real[base + i].v)
+            && (phte_real[base + i].vsid == vsid)
+            && (phte_real[base + i].api == api)
+            && (phte_real[base + i].h == 0)) {
+            found = true;
+            break;
+        }
     }
-    return false;
+    if (!found) {
+        /* Find unused PTE in PTEG */
+        for (i = 0; i < 8; i++) {
+            if (!phte_real[base + i].v) {
+                found = true;
+                break;
+            }
+        }
+    }
+    if (!found) {
+        /* Secondary hash (not) */
+        uint32_t base2 = (~hash & 0x3ff) << 3;
+        /* Find colliding PTE in PTEG */
+        for (i = 0; i < 8; i++) {
+            if ((phte_real[base2 + i].v)
+                && (phte_real[base2 + i].vsid == vsid)
+                && (phte_real[base2 + i].api == api)
+                && (phte_real[base2 + i].h == 1)) {
+                found = true;
+                base = base2;
+                h = 1;
+                break;
+            }
+        }
+        if (!found) {
+            /* Find unused PTE in PTEG */
+            for (i = 0; i < 8; i++) {
+                if (!phte_real[base2 + i].v) {
+                    found = true;
+                    base = base2;
+                    h = 1;
+                    break;
+                }
+            }
+        }
+        if (!found) {
+            /* Use secondary hash to avoid collisions
+               with usual PHT refill handler. */
+            i = RANDI(seed_real) % 8;
+            base = base2;
+            h = 1;
+        }
+    }
+    phte_real[base + i].v = 1;
+    phte_real[base + i].vsid = vsid;
+    phte_real[base + i].h = h;
+    phte_real[base + i].api = api;
+    phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
+    phte_real[base + i].r = 0;
+    phte_real[base + i].c = 0;
+    phte_real[base + i].wimg = 0;
+    phte_real[base + i].pp = 2; // FIXME
+    return true;
 }
+/** Process ITLB/DTLB Miss Exception in Real Mode
+ *
+ *
+ */
+void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate)
+{
+    uint32_t badvaddr = tlbmiss & 0xfffffffc;
+    uint32_t physmem;
+    asm volatile (
+        "mfsprg3 %0\n"
+        : "=r" (physmem)
+    );
+    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
+        return; // FIXME
+    ptelo.rpn = KA2PA(badvaddr) >> 12;
+    ptelo.wimg = 0;
+    ptelo.pp = 2; // FIXME
+    uint32_t index = 0;
+    asm volatile (
+        "mtspr 981, %0\n"
+        "mtspr 982, %1\n"
+        "tlbld %2\n"
+        "tlbli %2\n"
+        : "=r" (index)
+        : "r" (ptehi),
+          "r" (ptelo)
+    );
+}
 void tlb_arch_init(void)
 {
     tlb_invalidate_all();
 ,9 → 445,87
 void tlb_invalidate_all(void)
 {
+    uint32_t index;
     asm volatile (
-        "tlbia\n"
+        "li %0, 0\n"
+        "sync\n"
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        TLB_FLUSH
+        "eieio\n"
         "tlbsync\n"
+        "sync\n"
+        : "=r" (index)
     );
 }
 ,7 → 594,7
             : "=r" (vsid)
             : "r" (sr << 28)
         );
-        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
+        printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
             sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
             ((vsid >> 30) & 1) ? " supervisor" : "",
             ((vsid >> 29) & 1) ? " user" : "");

 /branches/network/kernel/arch/ppc32/src/mm/frame.c
 ,7 → 74,7
         if (last_frame < ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE))
             last_frame = ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE);
     }
     /* First is exception vector, second is 'implementation specific',
        third and fourth is reserved, other contain real mode code */
     frame_mark_unavailable(0, 8);

 /branches/network/kernel/arch/ppc32/src/mm/page.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32mm
+/** @addtogroup ppc32mm
  * @{
  */
 /** @file
 ,7 → 49,7
 {
     if (last_frame + ALIGN_UP(size, PAGE_SIZE) >
         KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
-        panic("Unable to map physical memory %p (%" PRIs " bytes)",
+        panic("Unable to map physical memory %p (%" PRIs " bytes).",
             physaddr, size)
     uintptr_t virtaddr = PA2KA(last_frame);

 /branches/network/kernel/arch/ppc32/src/interrupt.c
 ,7 → 73,7
                 ack = true;
             }
-            irq->handler(irq, irq->arg);
+            irq->handler(irq);
             spinlock_unlock(&irq->lock);
         } else {
             /*
 ,8 → 92,8
 static void exception_decrementer(int n, istate_t *istate)
 {
+    start_decrementer();
     clock();
-    start_decrementer();
 }

 /branches/network/kernel/arch/ppc32/src/drivers/pic.c
 ,7 → 38,7
 #include <byteorder.h>
 #include <bitops.h>
-static volatile uint32_t *pic;
+static volatile uint32_t *pic = NULL;
 void pic_init(uintptr_t base, size_t size)
 {
 ,10 → 47,11
 void pic_enable_interrupt(int intnum)
 {
-    if (intnum < 32) {
-        pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] | (1 << intnum);
-    } else {
-        pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] | (1 << (intnum - 32));
+    if (pic) {
+        if (intnum < 32)
+            pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] | (1 << intnum);
+        else
+            pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] | (1 << (intnum - 32));
     }
 }
 ,34 → 58,39
 void pic_disable_interrupt(int intnum)
 {
-    if (intnum < 32) {
-        pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] & (~(1 << intnum));
-    } else {
-        pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] & (~(1 << (intnum - 32)));
+    if (pic) {
+        if (intnum < 32)
+            pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] & (~(1 << intnum));
+        else
+            pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] & (~(1 << (intnum - 32)));
     }
 }
 void pic_ack_interrupt(int intnum)
 {
-    if (intnum < 32)
-        pic[PIC_ACK_LOW] = 1 << intnum;
-    else
-        pic[PIC_ACK_HIGH] = 1 << (intnum - 32);
+    if (pic) {
+        if (intnum < 32)
+            pic[PIC_ACK_LOW] = 1 << intnum;
+        else
+            pic[PIC_ACK_HIGH] = 1 << (intnum - 32);
+    }
 }
 /** Return number of pending interrupt */
 int pic_get_pending(void)
 {
-    int pending;
-    pending = pic[PIC_PENDING_LOW];
-    if (pending)
-        return fnzb32(pending);
+    if (pic) {
+        int pending;
+        pending = pic[PIC_PENDING_LOW];
+        if (pending)
+            return fnzb32(pending);
+        pending = pic[PIC_PENDING_HIGH];
+        if (pending)
+            return fnzb32(pending) + 32;
+    }
-    pending = pic[PIC_PENDING_HIGH];
-    if (pending)
-        return fnzb32(pending) + 32;
     return -1;
 }

 /branches/network/kernel/arch/ppc32/src/drivers/cuda.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ppc32
+/** @addtogroup ppc32
  * @{
  */
 /** @file
 ,7 → 33,6
  */
 #include <arch/drivers/cuda.h>
-#include <ipc/irq.h>
 #include <arch/asm.h>
 #include <console/console.h>
 #include <console/chardev.h>
 ,6 → 40,7
 #include <sysinfo/sysinfo.h>
 #include <interrupt.h>
 #include <stdarg.h>
+#include <ddi/device.h>
 #define CUDA_IRQ 10
 #define SPECIAL     '?'
 ,101 → 205,52
 }
-/* Called from getc(). */
-static void cuda_resume(chardev_t *d)
-{
-}
-/* Called from getc(). */
-static void cuda_suspend(chardev_t *d)
-{
-}
-static char key_read(chardev_t *d)
-{
-    char ch;
-    ch = 0;
-    return ch;
-}
-static chardev_t kbrd;
-static chardev_operations_t ops = {
-    .suspend = cuda_suspend,
-    .resume = cuda_resume,
-    .read = key_read
+static indev_t kbrd;
+static indev_operations_t ops = {
+    .poll = NULL
 };
 int cuda_get_scancode(void)
 {
-    uint8_t kind;
-    uint8_t data[4];
+    if (cuda) {
+        uint8_t kind;
+        uint8_t data[4];
+        receive_packet(&kind, 4, data);
+        if ((kind == PACKET_ADB) && (data[0] == 0x40) && (data[1] == 0x2c))
+            return data[2];
+    }
-    receive_packet(&kind, 4, data);
-    if ((kind == PACKET_ADB) && (data[0] == 0x40) && (data[1] == 0x2c))
-        return data[2];
     return -1;
 }
-static void cuda_irq_handler(irq_t *irq, void *arg, ...)
+static void cuda_irq_handler(irq_t *irq)
 {
-    if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox))
-        ipc_irq_send_notif(irq);
-    else {
-        int scan_code = cuda_get_scancode();
-        if (scan_code != -1) {
-            uint8_t scancode = (uint8_t) scan_code;
-            if ((scancode & 0x80) != 0x80)
-                chardev_push_character(&kbrd, lchars[scancode & 0x7f]);
-        }
+    int scan_code = cuda_get_scancode();
+    if (scan_code != -1) {
+        uint8_t scancode = (uint8_t) scan_code;
+        if ((scancode & 0x80) != 0x80)
+            indev_push_character(&kbrd, lchars[scancode & 0x7f]);
     }
 }
-static irq_ownership_t cuda_claim(void)
+static irq_ownership_t cuda_claim(irq_t *irq)
 {
     return IRQ_ACCEPT;
 }
-/** Initialize keyboard and service interrupts using kernel routine */
-void cuda_grab(void)
+void cuda_init(uintptr_t base, size_t size)
 {
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&cuda_irq.lock);
-    cuda_irq.notif_cfg.notify = false;
-    spinlock_unlock(&cuda_irq.lock);
-    interrupts_restore(ipl);
-}
-/** Resume the former interrupt vector */
-void cuda_release(void)
-{
-    ipl_t ipl = interrupts_disable();
-    spinlock_lock(&cuda_irq.lock);
-    if (cuda_irq.notif_cfg.answerbox)
-        cuda_irq.notif_cfg.notify = true;
-    spinlock_unlock(&cuda_irq.unlock);
-    interrupts_restore(ipl);
-}
-void cuda_init(devno_t devno, uintptr_t base, size_t size)
-{
-    cuda = (uint8_t *) hw_map(base, size);
+    cuda = (uint8_t *) hw_map(base, size);
-    chardev_initialize("cuda_kbd", &kbrd, &ops);
+    indev_initialize("cuda_kbd", &kbrd, &ops);
     stdin = &kbrd;
     irq_initialize(&cuda_irq);
-    cuda_irq.devno = devno;
+    cuda_irq.devno = device_assign_devno();
     cuda_irq.inr = CUDA_IRQ;
     cuda_irq.claim = cuda_claim;
     cuda_irq.handler = cuda_irq_handler;
 ,9 → 257,8
     irq_register(&cuda_irq);
     pic_enable_interrupt(CUDA_IRQ);
     sysinfo_set_item_val("kbd", NULL, true);
-    sysinfo_set_item_val("kbd.devno", NULL, devno);
     sysinfo_set_item_val("kbd.inr", NULL, CUDA_IRQ);
     sysinfo_set_item_val("kbd.address.virtual", NULL, base);
 }
 ,7 → 295,9
 }
 void arch_reboot(void) {
-    send_packet(PACKET_CUDA, 1, CUDA_RESET);
+    if (cuda)
+        send_packet(PACKET_CUDA, 1, CUDA_RESET);
     asm volatile (
         "b 0\n"
     );

/branches/network/kernel/arch/amd64/include/drivers/i8254.h
File deleted
\ No newline at end of file
Property changes:
Deleted: svn:special
-*
\ No newline at end of property

/branches/network/kernel/arch/amd64/include/drivers/ega.h
File deleted
\ No newline at end of file
Property changes:
Deleted: svn:special
-*
\ No newline at end of property

/branches/network/kernel/arch/amd64/include/drivers/i8259.h
File deleted
\ No newline at end of file
Property changes:
Deleted: svn:special
-*
\ No newline at end of property

/branches/network/kernel/arch/amd64/include/drivers/i8042.h
File deleted
\ No newline at end of file
Property changes:
Deleted: svn:special
-*
\ No newline at end of property

 /branches/network/kernel/arch/amd64/include/interrupt.h
 ,7 → 71,6
 /** This is passed to interrupt handlers */
 typedef struct {
     uint64_t rax;
-    uint64_t rbx;
     uint64_t rcx;
     uint64_t rdx;
     uint64_t rsi;
 ,11 → 79,6
     uint64_t r9;
     uint64_t r10;
     uint64_t r11;
-    uint64_t r12;
-    uint64_t r13;
-    uint64_t r14;
-    uint64_t r15;
-    uint64_t rbp;
     uint64_t error_word;
     uint64_t rip;
     uint64_t cs;

 /branches/network/kernel/arch/amd64/include/types.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64
+/** @addtogroup amd64
  * @{
  */
 /** @file
 ,6 → 57,9
 typedef uint64_t unative_t;
 typedef int64_t native_t;
+typedef struct {
+} fncptr_t;
 /**< Formats for uintptr_t, size_t, count_t and index_t */
 #define PRIp "llx"
 #define PRIs "llu"

 /branches/network/kernel/arch/amd64/include/syscall.h
 ,8 → 35,6
 #ifndef KERN_amd64_SYSCALL_H_
 #define KERN_amd64_SYSCALL_H_
-#include <arch/types.h>
 extern void syscall_setup_cpu(void);
 #endif

 /branches/network/kernel/arch/amd64/include/atomic.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64
+/** @addtogroup amd64
  * @{
  */
 /** @file
 ,17 → 41,29
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-    asm volatile ("lock incq %0\n" : "+m" (val->count));
+    asm volatile (
+        "lock incq %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #else
-    asm volatile ("incq %0\n" : "+m" (val->count));
+    asm volatile (
+        "incq %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #endif /* CONFIG_SMP */
 }
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-    asm volatile ("lock decq %0\n" : "+m" (val->count));
+    asm volatile (
+        "lock decq %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #else
-    asm volatile ("decq %0\n" : "+m" (val->count));
+    asm volatile (
+        "decq %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #endif /* CONFIG_SMP */
 }
 ,12 → 70,12
 static inline long atomic_postinc(atomic_t *val)
 {
     long r = 1;
     asm volatile (
-        "lock xaddq %1, %0\n"
-        : "+m" (val->count), "+r" (r)
+        "lock xaddq %[r], %[count]\n"
+        : [count] "+m" (val->count), [r] "+r" (r)
     );
     return r;
 }
 ,23 → 84,23
     long r = -1;
     asm volatile (
-        "lock xaddq %1, %0\n"
-        : "+m" (val->count), "+r" (r)
+        "lock xaddq %[r], %[count]\n"
+        : [count] "+m" (val->count), [r] "+r" (r)
     );
     return r;
 }
-#define atomic_preinc(val) (atomic_postinc(val) + 1)
-#define atomic_predec(val) (atomic_postdec(val) - 1)
+#define atomic_preinc(val)  (atomic_postinc(val) + 1)
+#define atomic_predec(val)  (atomic_postdec(val) - 1)
 static inline uint64_t test_and_set(atomic_t *val) {
     uint64_t v;
     asm volatile (
-        "movq $1, %0\n"
-        "xchgq %0, %1\n"
-        : "=r" (v), "+m" (val->count)
+        "movq $1, %[v]\n"
+        "xchgq %[v], %[count]\n"
+        : [v] "=r" (v), [count] "+m" (val->count)
     );
     return v;
 ,7 → 111,7
 static inline void atomic_lock_arch(atomic_t *val)
 {
     uint64_t tmp;
     preemption_disable();
     asm volatile (
         "0:\n"
 ,15 → 118,15
 #ifdef CONFIG_HT
         "pause\n"
 #endif
-        "mov %0, %1\n"
-        "testq %1, %1\n"
+        "mov %[count], %[tmp]\n"
+        "testq %[tmp], %[tmp]\n"
         "jnz 0b\n"       /* lightweight looping on locked spinlock */
-        "incq %1\n"      /* now use the atomic operation */
-        "xchgq %0, %1\n"
-        "testq %1, %1\n"
+        "incq %[tmp]\n"  /* now use the atomic operation */
+        "xchgq %[count], %[tmp]\n"
+        "testq %[tmp], %[tmp]\n"
         "jnz 0b\n"
-                : "+m" (val->count), "=&r" (tmp)
+        : [count] "+m" (val->count), [tmp] "=&r" (tmp)
     );
     /*
      * Prevent critical section code from bleeding out this way up.

 /branches/network/kernel/arch/amd64/include/pm.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64
+/** @addtogroup amd64
  * @{
  */
 /** @file
 ,63 → 36,60
 #define KERN_amd64_PM_H_
 #ifndef __ASM__
-#   include <arch/types.h>
-#   include <arch/context.h>
+    #include <arch/types.h>
+    #include <arch/context.h>
 #endif
-#define IDT_ITEMS 64
-#define GDT_ITEMS 8
+#define IDT_ITEMS  64
+#define GDT_ITEMS  8
-#define NULL_DES    0
-/* Warning: Do not reorder next items, unless you look into syscall.c!!! */
-#define KTEXT_DES   1
-#define KDATA_DES   2
-#define UDATA_DES   3
-#define UTEXT_DES   4
-#define KTEXT32_DES     5
-/* EndOfWarning */
-#define TSS_DES     6
+#define NULL_DES     0
+/* Warning: Do not reorder the following items, unless you look into syscall.c! */
+#define KTEXT_DES    1
+#define KDATA_DES    2
+#define UDATA_DES    3
+#define UTEXT_DES    4
+#define KTEXT32_DES  5
+/* End of warning */
+#define TSS_DES      6
 #ifdef CONFIG_FB
-#define VESA_INIT_DES       8
-#define VESA_INIT_SEGMENT 0x8000
-#undef GDT_ITEMS
-#define GDT_ITEMS 9
+#define VESA_INIT_DES      8
+#define VESA_INIT_SEGMENT  0x8000
-#endif /*CONFIG_FB*/
+#undef GDT_ITEMS
+#define GDT_ITEMS  9
+#endif /* CONFIG_FB */
+#define gdtselector(des)  ((des) << 3)
+#define idtselector(des)  ((des) << 4)
-#define gdtselector(des)    ((des) << 3)
-#define idtselector(des)    ((des) << 4)
+#define PL_KERNEL  0
+#define PL_USER    3
-#define PL_KERNEL   0
-#define PL_USER     3
+#define AR_PRESENT   ( 1 << 7)
+#define AR_DATA       (2 << 3)
+#define AR_CODE       (3 << 3)
+#define AR_WRITABLE   (1 << 1)
+#define AR_READABLE   (1 << 1)
+#define AR_TSS        (0x09)
+#define AR_INTERRUPT  (0x0e)
+#define AR_TRAP       (0x0f)
-#define AR_PRESENT  (1<<7)
-#define AR_DATA     (2<<3)
-#define AR_CODE     (3<<3)
-#define AR_WRITABLE (1<<1)
-#define AR_READABLE     (1<<1)
-#define AR_TSS      (0x9)
-#define AR_INTERRUPT    (0xe)
-#define AR_TRAP         (0xf)
+#define DPL_KERNEL  (PL_KERNEL << 5)
+#define DPL_USER    (PL_USER << 5)
-#define DPL_KERNEL  (PL_KERNEL<<5)
-#define DPL_USER    (PL_USER<<5)
+#define TSS_BASIC_SIZE  104
+#define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
-#define TSS_BASIC_SIZE  104
-#define TSS_IOMAP_SIZE  (16*1024+1) /* 16K for bitmap + 1 terminating byte for convenience */
+#define IO_PORTS  (64 * 1024)
-#define IO_PORTS    (64*1024)
 #ifndef __ASM__
-struct descriptor {
+typedef struct {
     unsigned limit_0_15: 16;
     unsigned base_0_15: 16;
     unsigned base_16_23: 8;
 ,10 → 100,9
     unsigned special: 1;
     unsigned granularity : 1;
     unsigned base_24_31: 8;
-} __attribute__ ((packed));
-typedef struct descriptor descriptor_t;
+} __attribute__ ((packed)) descriptor_t;
-struct tss_descriptor {
+typedef struct {
     unsigned limit_0_15: 16;
     unsigned base_0_15: 16;
     unsigned base_16_23: 8;
 ,10 → 117,9
     unsigned base_24_31: 8;
     unsigned base_32_63 : 32;
     unsigned  : 32;
-} __attribute__ ((packed));
-typedef struct tss_descriptor tss_descriptor_t;
+} __attribute__ ((packed)) tss_descriptor_t;
-struct idescriptor {
+typedef struct {
     unsigned offset_0_15: 16;
     unsigned selector: 16;
     unsigned ist:3;
 ,22 → 130,19
     unsigned offset_16_31: 16;
     unsigned offset_32_63: 32;
     unsigned  : 32;
-} __attribute__ ((packed));
-typedef struct idescriptor idescriptor_t;
+} __attribute__ ((packed)) idescriptor_t;
-struct ptr_16_64 {
+typedef struct {
     uint16_t limit;
     uint64_t base;
-} __attribute__ ((packed));
-typedef struct ptr_16_64 ptr_16_64_t;
+} __attribute__ ((packed)) ptr_16_64_t;
-struct ptr_16_32 {
+typedef struct {
     uint16_t limit;
     uint32_t base;
-} __attribute__ ((packed));
-typedef struct ptr_16_32 ptr_16_32_t;
+} __attribute__ ((packed)) ptr_16_32_t;
-struct tss {
+typedef struct {
     uint32_t reserve1;
     uint64_t rsp0;
     uint64_t rsp1;
 ,8 → 159,7
     uint16_t reserve4;
     uint16_t iomap_base;
     uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed));
-typedef struct tss tss_t;
+} __attribute__ ((packed)) tss_t;
 extern tss_t *tss_p;

 /branches/network/kernel/arch/amd64/include/boot/boot.h
 ,8 → 42,17
 #define MULTIBOOT_HEADER_MAGIC  0x1BADB002
 #define MULTIBOOT_HEADER_FLAGS  0x00010003
-#define MULTIBOOT_LOADER_MAGIC  0x2BADB002
+#ifndef __ASM__
+#ifdef CONFIG_SMP
+/* This is only a symbol so the type is dummy. Obtain the value using &. */
+extern int _hardcoded_unmapped_size;
+#endif /* CONFIG_SMP */
+#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/amd64/include/arch.h
 ,6 → 35,10
 #ifndef KERN_amd64_ARCH_H_
 #define KERN_amd64_ARCH_H_
+#include <genarch/multiboot/multiboot.h>
+extern void arch_pre_main(uint32_t, const multiboot_info_t *);
 #endif
 /** @}

 /branches/network/kernel/arch/amd64/include/asm.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64
+/** @addtogroup amd64
  * @{
  */
 /** @file
 ,6 → 36,8
 #define KERN_amd64_ASM_H_
 #include <config.h>
+#include <arch/types.h>
+#include <typedefs.h>
 extern void asm_delay_loop(uint32_t t);
 extern void asm_fake_loop(uint32_t t);
 ,12 → 47,17
  * Return the base address of the current stack.
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
 {
     uintptr_t v;
-    asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
+    asm volatile (
+        "andq %%rsp, %[v]\n"
+        : [v] "=r" (v)
+        : "0" (~((uint64_t) STACK_SIZE-1))
+    );
     return v;
 }
 ,7 → 69,11
 static inline void cpu_halt(void)
 {
-    asm volatile ("hlt\n");
+    asm volatile (
+        "0:\n"
+        "   hlt\n"
+        "   jmp 0b\n"
+    );
 }
 ,15 → 83,63
  *
  * @param port Port to read from
  * @return Value read
+ *
  */
-static inline uint8_t inb(uint16_t port)
+static inline uint8_t pio_read_8(ioport8_t *port)
 {
     uint8_t val;
+    asm volatile (
+        "inb %w[port], %b[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
+    return val;
+}
-    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
+/** Word from port
+ *
+ * Get word from port
+ *
+ * @param port Port to read from
+ * @return Value read
+ *
+ */
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    uint16_t val;
+    asm volatile (
+        "inw %w[port], %w[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
     return val;
 }
+/** Double word from port
+ *
+ * Get double word from port
+ *
+ * @param port Port to read from
+ * @return Value read
+ *
+ */
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    uint32_t val;
+    asm volatile (
+        "inl %w[port], %[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
+    return val;
+}
 /** Byte to port
  *
  * Output byte to port
 ,12 → 146,48
  *
  * @param port Port to write to
  * @param val Value to write
+ *
  */
-static inline void outb(uint16_t port, uint8_t val)
+static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
-    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
+    asm volatile (
+        "outb %b[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
 }
+/** Word to port
+ *
+ * Output word to port
+ *
+ * @param port Port to write to
+ * @param val Value to write
+ *
+ */
+static inline void pio_write_16(ioport16_t *port, uint16_t val)
+{
+    asm volatile (
+        "outw %w[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
+}
+/** Double word to port
+ *
+ * Output double word to port
+ *
+ * @param port Port to write to
+ * @param val Value to write
+ *
+ */
+static inline void pio_write_32(ioport32_t *port, uint32_t val)
+{
+    asm volatile (
+        "outl %[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
+}
 /** Swap Hidden part of GS register with visible one */
 static inline void swapgs(void)
 {
 ,15 → 200,18
  * value of EFLAGS.
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
+        "popq %[v]\n"
         "sti\n"
-        : "=r" (v)
+        : [v] "=r" (v)
     );
     return v;
 }
 ,15 → 221,18
  * value of EFLAGS.
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
+        "popq %[v]\n"
         "cli\n"
-        : "=r" (v)
-        );
+        : [v] "=r" (v)
+    );
     return v;
 }
 ,13 → 241,14
  * Restore EFLAGS.
  *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl) {
-    __asm__ volatile (
-        "pushq %0\n"
+    asm volatile (
+        "pushq %[ipl]\n"
         "popfq\n"
-        : : "r" (ipl)
-        );
+        :: [ipl] "r" (ipl)
+    );
 }
 /** Return interrupt priority level.
 ,14 → 256,17
  * Return EFLAFS.
  *
  * @return Current interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_read(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
-        : "=r" (v)
+        "popq %[v]\n"
+        : [v] "=r" (v)
     );
     return v;
 }
 ,21 → 273,25
 /** Write to MSR */
 static inline void write_msr(uint32_t msr, uint64_t value)
 {
-    __asm__ volatile (
-        "wrmsr;" : : "c" (msr),
-        "a" ((uint32_t)(value)),
-        "d" ((uint32_t)(value >> 32))
-        );
+    asm volatile (
+        "wrmsr\n"
+        :: "c" (msr),
+           "a" ((uint32_t) (value)),
+           "d" ((uint32_t) (value >> 32))
+    );
 }
 static inline unative_t read_msr(uint32_t msr)
 {
     uint32_t ax, dx;
-    __asm__ volatile (
-        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
-        );
-    return ((uint64_t)dx << 32) | ax;
+    asm volatile (
+        "rdmsr\n"
+        : "=a" (ax), "=d" (dx)
+        : "c" (msr)
+    );
+    return ((uint64_t) dx << 32) | ax;
 }
 ,29 → 298,29
 /** Enable local APIC
  *
  * Enable local APIC in MSR.
+ *
  */
 static inline void enable_l_apic_in_msr()
 {
-    __asm__ volatile (
+    asm volatile (
         "movl $0x1b, %%ecx\n"
         "rdmsr\n"
-        "orl $(1<<11),%%eax\n"
+        "orl $(1 << 11),%%eax\n"
         "orl $(0xfee00000),%%eax\n"
         "wrmsr\n"
-        :
-        :
-        :"%eax","%ecx","%edx"
-        );
+        ::: "%eax","%ecx","%edx"
+    );
 }
 static inline uintptr_t * get_ip()
 {
     uintptr_t *ip;
-    __asm__ volatile (
-        "mov %%rip, %0"
-        : "=r" (ip)
-        );
+    asm volatile (
+        "mov %%rip, %[ip]"
+        : [ip] "=r" (ip)
+    );
     return ip;
 }
 ,59 → 327,84
 /** Invalidate TLB Entry.
  *
  * @param addr Address on a page whose TLB entry is to be invalidated.
+ *
  */
 static inline void invlpg(uintptr_t addr)
 {
-    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
+    asm volatile (
+        "invlpg %[addr]\n"
+        :: [addr] "m" (*((unative_t *) addr))
+    );
 }
 /** Load GDTR register from memory.
  *
  * @param gdtr_reg Address of memory from where to load GDTR.
+ *
  */
-static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
+static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
 {
-    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
+    asm volatile (
+        "lgdtq %[gdtr_reg]\n"
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
 }
 /** Store GDTR register to memory.
  *
  * @param gdtr_reg Address of memory to where to load GDTR.
+ *
  */
-static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
+static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
 {
-    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
+    asm volatile (
+        "sgdtq %[gdtr_reg]\n"
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
 }
 /** Load IDTR register from memory.
  *
  * @param idtr_reg Address of memory from where to load IDTR.
+ *
  */
-static inline void idtr_load(struct ptr_16_64 *idtr_reg)
+static inline void idtr_load(ptr_16_64_t *idtr_reg)
 {
-    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
+    asm volatile (
+        "lidtq %[idtr_reg]\n"
+        :: [idtr_reg] "m" (*idtr_reg));
 }
 /** Load TR from descriptor table.
  *
  * @param sel Selector specifying descriptor of TSS segment.
+ *
  */
 static inline void tr_load(uint16_t sel)
 {
-    __asm__ volatile ("ltr %0" : : "r" (sel));
+    asm volatile (
+        "ltr %[sel]"
+        :: [sel] "r" (sel)
+    );
 }
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
-    { \
-    unative_t res; \
-    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
-    return res; \
-    }
+    { \
+        unative_t res; \
+        asm volatile ( \
+            "movq %%" #reg ", %[res]" \
+            : [res] "=r" (res) \
+        ); \
+        return res; \
+    }
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
-    { \
-    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
-    }
+    { \
+        asm volatile ( \
+            "movq %[regn], %%" #reg \
+            :: [regn] "r" (regn) \
+        ); \
+    }
 GEN_READ_REG(cr0)
 GEN_READ_REG(cr2)

 /branches/network/kernel/arch/amd64/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64mm
+/** @addtogroup amd64mm
  * @{
  */
 /** @file
 ,8 → 39,8
 #include <arch/types.h>
 #endif /* __ASM__ */
-#define FRAME_WIDTH     12  /* 4K */
-#define FRAME_SIZE      (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  12  /* 4K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifndef __ASM__
 extern uintptr_t last_frame;

 /branches/network/kernel/arch/amd64/include/mm/tlb.h
 ,9 → 35,6
 #ifndef KERN_amd64_TLB_H_
 #define KERN_amd64_TLB_H_
-#define tlb_arch_init()
-#define tlb_print()
 #endif
 /** @}

 /branches/network/kernel/arch/amd64/include/cpu.h
 ,9 → 35,9
 #ifndef KERN_amd64_CPU_H_
 #define KERN_amd64_CPU_H_
-#define RFLAGS_IF   (1 << 9)
-#define RFLAGS_DF   (1 << 10)
-#define RFLAGS_RF   (1 << 16)
+#define RFLAGS_IF  (1 << 9)
+#define RFLAGS_DF  (1 << 10)
+#define RFLAGS_RF  (1 << 16)
 #define EFER_MSR_NUM    0xc0000080
 #define AMD_SCE_FLAG    0
 ,17 → 62,15
     int family;
     int model;
     int stepping;
-    struct tss *tss;
+    tss_t *tss;
-    count_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
+    count_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;
 struct star_msr {
 };
 struct lstar_msr {
 };
 extern void set_efer_flag(int flag);

 /branches/network/kernel/arch/amd64/Makefile.inc
 ,10 → 29,6
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf64-x86-64
 BFD_ARCH = i386:x86-64
 BFD = binary
 ,83 → 41,50
 ICC_CFLAGS += $(CMN1)
 SUNCC_CFLAGS += -m64 -xmodel=kernel
-DEFS += -DMACHINE=$(MACHINE) -D__64_BITS__
+DEFS += -D__64_BITS__
 ## Accepted CPUs
 #
-ifeq ($(MACHINE),opteron)
+ifeq ($(PROCESSOR),opteron)
     CMN2 := -march=opteron
     GCC_CFLAGS += $(CMN2)
     ICC_CFLAGS += $(CMN2)
     SUNCC_CFLAGS += -xtarget=opteron
-    DEFS += -DFENCES=p4
 endif
-## Own configuration directives
-#
-CONFIG_ACPI = y
-## Compile with hierarchical page tables support.
-#
-CONFIG_PAGE_PT = y
-DEFS += -DCONFIG_PAGE_PT
-## Compile with i8042 support.
-#
-CONFIG_I8042 = y
-DEFS += -DCONFIG_I8042
-## Accepted configuration directives
-#
-ifeq ($(CONFIG_SMP),y)
-    DEFS += -DCONFIG_SMP
-endif
-ifeq ($(CONFIG_HT),y)
-    DEFS += -DCONFIG_HT
-endif
-ifeq ($(CONFIG_SIMICS_FIX),y)
-    DEFS += -DCONFIG_SIMICS_FIX
-endif
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/fpu_context.c \
-    arch/$(ARCH)/src/boot/boot.S \
-    arch/$(ARCH)/src/boot/memmap.c \
-    arch/$(ARCH)/src/pm.c \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/ega.c \
-    arch/$(ARCH)/src/drivers/vesa.c \
-    arch/$(ARCH)/src/drivers/i8254.c \
-    arch/$(ARCH)/src/drivers/i8259.c \
-    arch/$(ARCH)/src/delay.S \
-    arch/$(ARCH)/src/amd64.c \
-    arch/$(ARCH)/src/bios/bios.c \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/asm_utils.S \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/proc/scheduler.c \
-    arch/$(ARCH)/src/proc/task.c \
-    arch/$(ARCH)/src/proc/thread.c \
-    arch/$(ARCH)/src/userspace.c \
-    arch/$(ARCH)/src/syscall.c \
-    arch/$(ARCH)/src/debugger.c
+    arch/$(KARCH)/src/fpu_context.c \
+    arch/$(KARCH)/src/boot/boot.S \
+    arch/$(KARCH)/src/boot/memmap.c \
+    arch/$(KARCH)/src/pm.c \
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/drivers/vesa.c \
+    arch/$(KARCH)/src/drivers/i8254.c \
+    arch/$(KARCH)/src/drivers/i8259.c \
+    arch/$(KARCH)/src/delay.S \
+    arch/$(KARCH)/src/amd64.c \
+    arch/$(KARCH)/src/bios/bios.c \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/asm_utils.S \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/proc/scheduler.c \
+    arch/$(KARCH)/src/proc/task.c \
+    arch/$(KARCH)/src/proc/thread.c \
+    arch/$(KARCH)/src/userspace.c \
+    arch/$(KARCH)/src/syscall.c \
+    arch/$(KARCH)/src/debugger.c
 ifeq ($(CONFIG_SMP),y)
     ARCH_SOURCES += \
-        arch/$(ARCH)/src/smp/ap.S \
-        arch/$(ARCH)/src/smp/apic.c \
-        arch/$(ARCH)/src/smp/ipi.c \
-        arch/$(ARCH)/src/smp/mps.c \
-        arch/$(ARCH)/src/smp/smp.c
+        arch/$(KARCH)/src/smp/ap.S \
+        arch/$(KARCH)/src/smp/apic.c \
+        arch/$(KARCH)/src/smp/ipi.c \
+        arch/$(KARCH)/src/smp/mps.c \
+        arch/$(KARCH)/src/smp/smp.c
 endif

 /branches/network/kernel/arch/amd64/src/fpu_context.c
 ,9 → 39,9
 void fpu_context_save(fpu_context_t *fctx)
 {
     asm volatile (
-        "fxsave %0"
-        : "=m"(*fctx)
-        );
+        "fxsave %[fctx]\n"
+        : [fctx] "=m" (*fctx)
+    );
 }
 /** Restore FPU (mmx,sse) context using fxrstor instruction */
 ,9 → 48,9
 void fpu_context_restore(fpu_context_t *fctx)
 {
     asm volatile (
-        "fxrstor %0"
-        : "=m"(*fctx)
-        );
+        "fxrstor %[fctx]\n"
+        : [fctx] "=m" (*fctx)
+    );
 }
 void fpu_init()
 ,7 → 57,7
 {
     /* TODO: Zero all SSE, MMX etc. registers */
     asm volatile (
-        "fninit;"
+        "fninit\n"
     );
 }

 /branches/network/kernel/arch/amd64/src/cpu/cpu.c
 ,21 → 77,19
 void cpu_setup_fpu(void)
 {
     asm volatile (
-        "movq %%cr0, %%rax;"
-        "btsq $1, %%rax;" /* cr0.mp */
-        "btrq $2, %%rax;"  /* cr0.em */
-        "movq %%rax, %%cr0;"
-        "movq %%cr4, %%rax;"
-        "bts $9, %%rax;" /* cr4.osfxsr */
-        "movq %%rax, %%cr4;"
-        :
-        :
-        :"%rax"
-        );
+        "movq %%cr0, %%rax\n"
+        "btsq $1, %%rax\n"  /* cr0.mp */
+        "btrq $2, %%rax\n"  /* cr0.em */
+        "movq %%rax, %%cr0\n"
+        "movq %%cr4, %%rax\n"
+        "bts $9, %%rax\n"   /* cr4.osfxsr */
+        "movq %%rax, %%cr4\n"
+        ::: "%rax"
+    );
 }
-/** Set the TS flag to 1.
+/** Set the TS flag to 1.
  *
  * If a thread accesses coprocessor, exception is run, which
  * does a lazy fpu context switch.
 ,26 → 97,22
  */
 void fpu_disable(void)
 {
-    asm volatile (
-        "mov %%cr0,%%rax;"
-        "bts $3,%%rax;"
-        "mov %%rax,%%cr0;"
-        :
-        :
-        :"%rax"
-        );
+    asm volatile (
+        "mov %%cr0, %%rax\n"
+        "bts $3, %%rax\n"
+        "mov %%rax, %%cr0\n"
+        ::: "%rax"
+    );
 }
 void fpu_enable(void)
 {
-    asm volatile (
-        "mov %%cr0,%%rax;"
-        "btr $3,%%rax;"
-        "mov %%rax,%%cr0;"
-        :
-        :
-        :"%rax"
-        );
+    asm volatile (
+        "mov %%cr0, %%rax\n"
+        "btr $3, %%rax\n"
+        "mov %%rax, %%cr0\n"
+        ::: "%rax"
+    );
 }
 void cpu_arch_init(void)

 /branches/network/kernel/arch/amd64/src/amd64.c
 ,11 → 39,15
 #include <config.h>
 #include <proc/thread.h>
-#include <arch/drivers/ega.h>
+#include <genarch/multiboot/multiboot.h>
+#include <genarch/drivers/legacy/ia32/io.h>
+#include <genarch/drivers/ega/ega.h>
 #include <arch/drivers/vesa.h>
-#include <genarch/kbd/i8042.h>
+#include <genarch/drivers/i8042/i8042.h>
+#include <genarch/kbrd/kbrd.h>
 #include <arch/drivers/i8254.h>
 #include <arch/drivers/i8259.h>
+#include <arch/boot/boot.h>
 #ifdef CONFIG_SMP
 #include <arch/smp/apic.h>
 ,9 → 65,8
 #include <syscall/syscall.h>
 #include <console/console.h>
 #include <ddi/irq.h>
-#include <ddi/device.h>
+#include <sysinfo/sysinfo.h>
 /** Disable I/O on non-privileged levels
  *
  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
 ,15 → 73,13
  */
 static void clean_IOPL_NT_flags(void)
 {
-    asm (
+    asm volatile (
         "pushfq\n"
         "pop %%rax\n"
         "and $~(0x7000), %%rax\n"
         "pushq %%rax\n"
         "popfq\n"
-        :
-        :
-        : "%rax"
+        ::: "%rax"
     );
 }
 ,16 → 89,31
  */
 static void clean_AM_flag(void)
 {
-    asm (
+    asm volatile (
         "mov %%cr0, %%rax\n"
         "and $~(0x40000), %%rax\n"
         "mov %%rax, %%cr0\n"
-        :
-        :
-        : "%rax"
+        ::: "%rax"
     );
 }
+/** Perform amd64-specific initialization before main_bsp() is called.
+ *
+ * @param signature Should contain the multiboot signature.
+ * @param mi        Pointer to the multiboot information structure.
+ */
+void arch_pre_main(uint32_t signature, const multiboot_info_t *mi)
+{
+    /* Parse multiboot information obtained from the bootloader. */
+    multiboot_info_parse(signature, mi);
+#ifdef CONFIG_SMP
+    /* Copy AP bootstrap routines below 1 MB. */
+    memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
+        (size_t) &_hardcoded_unmapped_size);
+#endif
+}
 void arch_pre_mm_init(void)
 {
     /* Enable no-execute pages */
 ,13 → 149,17
         /* hard clock */
         i8254_init();
 #ifdef CONFIG_FB
         if (vesa_present())
             vesa_init();
         else
 #endif
-            ega_init(); /* video */
+#ifdef CONFIG_EGA
+            ega_init(EGA_BASE, EGA_VIDEORAM);  /* video */
+#else
+            {}
+#endif
         /* Enable debugger */
         debugger_init();
 ,8 → 192,28
 void arch_post_smp_init(void)
 {
-    /* keyboard controller */
-    i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);
+#ifdef CONFIG_PC_KBD
+    /*
+     * Initialize the i8042 controller. Then initialize the keyboard
+     * module and connect it to i8042. Enable keyboard interrupts.
+     */
+    indev_t *kbrdin = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
+    if (kbrdin) {
+        kbrd_init(kbrdin);
+        trap_virtual_enable_irqs(1 << IRQ_KBD);
+    }
+    /*
+     * This is the necessary evil until the userspace driver is entirely
+     * self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
+    sysinfo_set_item_val("kbd.address.physical", NULL,
+        (uintptr_t) I8042_BASE);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) I8042_BASE);
+#endif
 }
 void calibrate_delay_loop(void)
 ,15 → 248,38
  */
 void arch_grab_console(void)
 {
-    i8042_grab();
+#ifdef CONFIG_FB
+    if (vesa_present())
+        vesa_redraw();
+    else
+#endif
+#ifdef CONFIG_EGA
+        ega_redraw();
+#else
+        {}
+#endif
 }
 /** Return console to userspace
  *
  */
 void arch_release_console(void)
 {
-    i8042_release();
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/amd64/src/pm.c
 ,8 → 137,8
 void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
 {
-    struct tss_descriptor *td = (tss_descriptor_t *) d;
+    tss_descriptor_t *td = (tss_descriptor_t *) d;
     td->limit_0_15 = limit & 0xffff;
     td->limit_16_19 = (limit >> 16) & 0xf;
 }
 ,14 → 185,14
  */
 void pm_init(void)
 {
-    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
+    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
     tss_descriptor_t *tss_desc;
     /*
      * Each CPU has its private GDT and TSS.
      * All CPUs share one IDT.
      */
     if (config.cpu_active == 1) {
         idt_init();
         /*
 ,20 → 200,19
          * the heap hasn't been initialized so far.
          */
         tss_p = &tss;
-    }
-    else {
+    } else {
         /* We are going to use malloc, which may return
          * non boot-mapped pointer, initialize the CR3 register
          * ahead of page_init */
         write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
-        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
+        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
         if (!tss_p)
-            panic("could not allocate TSS\n");
+            panic("Cannot allocate TSS.");
     }
     tss_initialize(tss_p);
     tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
     tss_desc->present = 1;
     tss_desc->type = AR_TSS;
 ,7 → 220,7
     gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
     gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
     gdtr_load(&gdtr);
     idtr_load(&idtr);
     /*

 /branches/network/kernel/arch/amd64/src/ddi/ddi.c
 ,15 → 57,15
 int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size)
 {
     count_t bits;
     bits = ioaddr + size;
     if (bits > IO_PORTS)
         return ENOENT;
     if (task->arch.iomap.bits < bits) {
         bitmap_t oldiomap;
         uint8_t *newmap;
         /*
          * The I/O permission bitmap is too small and needs to be grown.
          */
 ,17 → 77,17
         bitmap_initialize(&oldiomap, task->arch.iomap.map,
             task->arch.iomap.bits);
         bitmap_initialize(&task->arch.iomap, newmap, bits);
         /*
          * Mark the new range inaccessible.
          */
         bitmap_set_range(&task->arch.iomap, oldiomap.bits,
             bits - oldiomap.bits);
         /*
          * In case there really existed smaller iomap,
          * copy its contents and deallocate it.
-         */
+         */
         if (oldiomap.bits) {
             bitmap_copy(&task->arch.iomap, &oldiomap,
                 oldiomap.bits);
 ,17 → 94,17
             free(oldiomap.map);
         }
     }
     /*
      * Enable the range and we are done.
      */
     bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
     /*
      * Increment I/O Permission bitmap generation counter.
      */
     task->arch.iomapver++;
     return 0;
 }
 ,7 → 122,7
     descriptor_t *gdt_p;
     tss_descriptor_t *tss_desc;
     count_t ver;
     /* First, copy the I/O Permission Bitmap. */
     spinlock_lock(&TASK->lock);
     ver = TASK->arch.iomapver;
 ,7 → 140,7
         bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8);
     }
     spinlock_unlock(&TASK->lock);
     /*
      * Second, adjust TSS segment limit.
      * Take the extra ending byte will all bits set into account.
 ,10 → 151,10
     gdtr_load(&cpugdtr);
     /*
-         * Before we load new TSS limit, the current TSS descriptor
-         * type must be changed to describe inactive TSS.
-         */
-    tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
+     * Before we load new TSS limit, the current TSS descriptor
+     * type must be changed to describe inactive TSS.
+     */
+    tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
     tss_desc->type = AR_TSS;
     tr_load(gdtselector(TSS_DES));

 /branches/network/kernel/arch/amd64/src/asm_utils.S
 ,23 → 26,17
 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-#define IREGISTER_SPACE 120
+#define IREGISTER_SPACE 72
-#define IOFFSET_RAX 0x0
-#define IOFFSET_RBX 0x8
-#define IOFFSET_RCX 0x10
-#define IOFFSET_RDX 0x18
-#define IOFFSET_RSI 0x20
-#define IOFFSET_RDI 0x28
-#define IOFFSET_R8 0x30
-#define IOFFSET_R9 0x38
-#define IOFFSET_R10 0x40
-#define IOFFSET_R11 0x48
-#define IOFFSET_R12 0x50
-#define IOFFSET_R13 0x58
-#define IOFFSET_R14 0x60
-#define IOFFSET_R15 0x68
-#define IOFFSET_RBP 0x70
+#define IOFFSET_RAX 0x0
+#define IOFFSET_RCX 0x8
+#define IOFFSET_RDX 0x10
+#define IOFFSET_RSI 0x18
+#define IOFFSET_RDI 0x20
+#define IOFFSET_R8  0x28
+#define IOFFSET_R9  0x30
+#define IOFFSET_R10 0x38
+#define IOFFSET_R11 0x40
 #  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
 # and 1 means interrupt with error word
 ,7 → 167,7
     rdmsr
     ret
-# Push all general purpose registers on stack except %rbp, %rsp
+# Push all volatile general purpose registers on stack
 .macro save_all_gpr
     movq %rax, IOFFSET_RAX(%rsp)
     movq %rcx, IOFFSET_RCX(%rsp)
 ,14 → 178,6
     movq %r9, IOFFSET_R9(%rsp)
     movq %r10, IOFFSET_R10(%rsp)
     movq %r11, IOFFSET_R11(%rsp)
-#ifdef CONFIG_DEBUG_ALLREGS
-    movq %rbx, IOFFSET_RBX(%rsp)
-    movq %rbp, IOFFSET_RBP(%rsp)
-    movq %r12, IOFFSET_R12(%rsp)
-    movq %r13, IOFFSET_R13(%rsp)
-    movq %r14, IOFFSET_R14(%rsp)
-    movq %r15, IOFFSET_R15(%rsp)
-#endif
 .endm
 .macro restore_all_gpr
 ,21 → 190,9
     movq IOFFSET_R9(%rsp), %r9
     movq IOFFSET_R10(%rsp), %r10
     movq IOFFSET_R11(%rsp), %r11
-#ifdef CONFIG_DEBUG_ALLREGS
-    movq IOFFSET_RBX(%rsp), %rbx
-    movq IOFFSET_RBP(%rsp), %rbp
-    movq IOFFSET_R12(%rsp), %r12
-    movq IOFFSET_R13(%rsp), %r13
-    movq IOFFSET_R14(%rsp), %r14
-    movq IOFFSET_R15(%rsp), %r15
-#endif
 .endm
-#ifdef CONFIG_DEBUG_ALLREGS
-# define INTERRUPT_ALIGN 256
-#else
-# define INTERRUPT_ALIGN 128
-#endif
+#define INTERRUPT_ALIGN 128
 ## Declare interrupt handlers
 #

 /branches/network/kernel/arch/amd64/src/proc/scheduler.c
 ,7 → 39,6
 #include <arch.h>
 #include <arch/context.h>   /* SP_DELTA */
 #include <arch/asm.h>
-#include <arch/debugger.h>
 #include <print.h>
 #include <arch/pm.h>
 #include <arch/ddi/ddi.h>
 ,13 → 67,6
     /* TLS support - set FS to thread local storage */
     write_msr(AMD_MSR_FS, THREAD->arch.tls);
-#ifdef CONFIG_DEBUG_AS_WATCHPOINT
-    /* Set watchpoint on AS to ensure that nobody sets it to zero */
-    if (CPU->id < BKPOINTS_MAX)
-        breakpoint_add(&((the_t *) THREAD->kstack)->as,
-            BKPOINT_WRITE | BKPOINT_CHECK_ZERO, CPU->id);
-#endif
 }
 void after_thread_ran_arch(void)

 /branches/network/kernel/arch/amd64/src/boot/vesa_ret.inc
 ,0 → 1,19
+.code32
+vesa_init_protected:
+    movw $gdtselector(KDATA_DES), %cx
+    movw %cx, %es
+    movw %cx, %ds                       # kernel data + stack
+    movw %cx, %ss
+    #
+    # Simics seems to remove hidden part of GS on entering user mode
+    # when _visible_ part of GS does not point to user-mode segment.
+    #
+    movw $gdtselector(UDATA_DES), %cx
+    movw %cx, %fs
+    movw %cx, %gs
+    movl $START_STACK, %esp             # initialize stack pointer
+    jmpl $gdtselector(KTEXT32_DES), $vesa_meeting_point

 /branches/network/kernel/arch/amd64/src/boot/boot.S
 ,4 → 1,4
+#
 # Copyright (c) 2005 Ondrej Palkovsky
 # Copyright (c) 2006 Martin Decky
 # Copyright (c) 2008 Jakub Jermar
 ,7 → 37,7
 #include <arch/cpuid.h>
 #define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE)
 .section K_TEXT_START, "ax"
 .code32
 ,7 → 46,7
 multiboot_header:
     .long MULTIBOOT_HEADER_MAGIC
     .long MULTIBOOT_HEADER_FLAGS
-    .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)    # checksum
+    .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)  # checksum
     .long multiboot_header
     .long unmapped_ktext_start
     .long 0
 ,15 → 55,19
 multiboot_image_start:
     cld
-    movl $START_STACK, %esp         # initialize stack pointer
-    lgdtl bootstrap_gdtr            # initialize Global Descriptor Table register
+    movl $START_STACK, %esp             # initialize stack pointer
+    lgdtl bootstrap_gdtr                # initialize Global Descriptor Table register
     movw $gdtselector(KDATA_DES), %cx
     movw %cx, %es
-    movw %cx, %ds                           # kernel data + stack
+    movw %cx, %ds                       # kernel data + stack
     movw %cx, %ss
+    #
     # Simics seems to remove hidden part of GS on entering user mode
-    #  when _visible_ part of GS does not point to user-mode segment
+    # when _visible_ part of GS does not point to user-mode segment.
+    #
     movw $gdtselector(UDATA_DES), %cx
     movw %cx, %fs
     movw %cx, %gs
 ,17 → 75,19
     jmpl $gdtselector(KTEXT32_DES), $multiboot_meeting_point
     multiboot_meeting_point:
-    movl %eax, grub_eax                     # save parameters from GRUB
+    movl %eax, grub_eax                 # save parameters from GRUB
     movl %ebx, grub_ebx
+    #
     # Protected 32-bit. We want to reuse the code-seg descriptor,
-    # the Default operand size must not be 1 when entering long mode
+    # the Default operand size must not be 1 when entering long mode.
+    #
-    movl $(INTEL_CPUID_EXTENDED), %eax
-    cpuid
-    cmp $(INTEL_CPUID_EXTENDED), %eax
+    movl $(INTEL_CPUID_EXTENDED), %eax
+    cpuid
+    cmp $(INTEL_CPUID_EXTENDED), %eax
     ja extended_cpuid_supported
         movl $extended_cpuid_msg, %esi
         jmp error_halt
 ,11 → 96,11
     movl $(AMD_CPUID_EXTENDED), %eax
     cpuid
     bt $(AMD_EXT_LONG_MODE), %edx
-    jc long_mode_supported
+    jc long_mode_supported
         movl $long_mode_msg, %esi
         jmp error_halt
     long_mode_supported:
     bt $(AMD_EXT_NOEXECUTE), %edx
 ,7 → 114,7
     movl $(INTEL_CPUID_STANDARD), %eax
     cpuid
     bt $(INTEL_FXSAVE), %edx
-    jc fx_supported
+    jc fx_supported
         movl $fx_msg, %esi
         jmp error_halt
 ,59 → 122,43
     fx_supported:
     bt $(INTEL_SSE2), %edx
-    jc sse2_supported
+    jc sse2_supported
         movl $sse2_msg, %esi
         jmp error_halt
     sse2_supported:
-#ifdef CONFIG_FB
-    mov $vesa_init, %esi
-    mov $VESA_INIT_SEGMENT << 4, %edi
-    mov $e_vesa_init - vesa_init, %ecx
-    rep movsb
-    mov $VESA_INIT_SEGMENT << 4, %edi
-    jmpl *%edi
-    vesa_meeting_point:
-    mov %esi, KA2PA(vesa_ph_addr)
-    mov %di, KA2PA(vesa_height)
-    shr $16, %edi
-    mov %di, KA2PA(vesa_width)
-    mov %bx, KA2PA(vesa_scanline)
-    shr $16, %ebx
-    mov %bx, KA2PA(vesa_bpp)
-#endif
+#include "vesa_prot.inc"
+    #
     # Enable 64-bit page translation entries - CR4.PAE = 1.
-    # Paging is not enabled until after long mode is enabled
+    # Paging is not enabled until after long mode is enabled.
+    #
     movl %cr4, %eax
     btsl $5, %eax
     movl %eax, %cr4
-    # Set up paging tables
+    # set up paging tables
     leal ptl_0, %eax
     movl %eax, %cr3
-    # Enable long mode
+    # enable long mode
-    movl $EFER_MSR_NUM, %ecx            # EFER MSR number
-    rdmsr                       # Read EFER
-    btsl $AMD_LME_FLAG, %eax            # Set LME = 1
-    wrmsr                       # Write EFER
+    movl $EFER_MSR_NUM, %ecx            # EFER MSR number
+    rdmsr                               # read EFER
+    btsl $AMD_LME_FLAG, %eax            # set LME = 1
+    wrmsr                               # write EFER
-    # Enable paging to activate long mode (set CR0.PG = 1)
+    # enable paging to activate long mode (set CR0.PG = 1)
     movl %cr0, %eax
     btsl $31, %eax
     movl %eax, %cr0
-    # At this point we are in compatibility mode
+    # at this point we are in compatibility mode
     jmpl $gdtselector(KTEXT_DES), $start64
 ,362 → 165,29
 .code64
 start64:
     movq $(PA2KA(START_STACK)), %rsp
-    movl grub_eax, %eax
-    movl grub_ebx, %ebx
-    cmpl $MULTIBOOT_LOADER_MAGIC, %eax          # compare GRUB signature
-    je valid_boot
-        xorl %ecx, %ecx                 # no memory size or map available
-        movl %ecx, e820counter
-        jmp invalid_boot
-    valid_boot:
-        movl (%ebx), %eax               # ebx = physical address of struct multiboot_info
-        bt $3, %eax                 # mbi->flags[3] (mods_count, mods_addr valid)
-        jc mods_valid
-            xorq %rcx, %rcx
-            movq %rcx, init
-            jmp mods_end
-        mods_valid:
-        xorq %rcx, %rcx
-        movl 20(%ebx), %ecx             # mbi->mods_count
-        movq %rcx, init
-        cmpl $0, %ecx
-        je mods_end
-        movl 24(%ebx), %esi             # mbi->mods_addr
-        movq $init, %rdi
-        mods_loop:
-            xorq %rdx, %rdx
-            movl 0(%esi), %edx          # mods->mod_start
-            movq $0xffff800000000000, %r10
-            addq %r10, %rdx
-            movq %rdx, 8(%rdi)
-            xorq %rdx, %rdx
-            movl 4(%esi), %edx
-            subl 0(%esi), %edx          # mods->mod_end - mods->mod_start
-            movq %rdx, 16(%rdi)
-            addl $16, %esi
-            addq $16, %rdi
-            loop mods_loop
-        mods_end:
-        bt $6, %eax                 # mbi->flags[6] (mmap_length, mmap_addr valid)
-        jc mmap_valid
-            xorl %edx, %edx
-            jmp mmap_invalid
-        mmap_valid:
-        movl 44(%ebx), %ecx             # mbi->mmap_length
-        movl 48(%ebx), %esi             # mbi->mmap_addr
-        movq $e820table, %rdi
-        xorl %edx, %edx
-        mmap_loop:
-            cmpl $0, %ecx
-            jle mmap_end
-            movl 4(%esi), %eax          # mmap->base_addr_low
-            movl %eax, (%rdi)
-            movl 8(%esi), %eax          # mmap->base_addr_high
-            movl %eax, 4(%rdi)
-            movl 12(%esi), %eax         # mmap->length_low
-            movl %eax, 8(%rdi)
-            movl 16(%esi), %eax         # mmap->length_high
-            movl %eax, 12(%rdi)
-            movl 20(%esi), %eax         # mmap->type
-            movl %eax, 16(%rdi)
-            movl (%esi), %eax           # mmap->size
-            addl $0x4, %eax
-            addl %eax, %esi
-            subl %eax, %ecx
-            addq $MEMMAP_E820_RECORD_SIZE, %rdi
-            incl %edx
-            jmp mmap_loop
-        mmap_end:
-        mmap_invalid:
-        movl %edx, e820counter
-    invalid_boot:
+    # call arch_pre_main(grub_eax, grub_ebx)
+    xorq %rdi, %rdi
+    movl grub_eax, %edi
+    xorq %rsi, %rsi
+    movl grub_ebx, %esi
+    call arch_pre_main
-#ifdef CONFIG_SMP
+    call main_bsp
-    # copy AP bootstrap routines below 1 MB
+    # not reached
-    movq $BOOT_OFFSET, %rsi
-    movq $AP_BOOT_OFFSET, %rdi
-    movq $_hardcoded_unmapped_size, %rcx
-    rep movsb
-#endif
-    call main_bsp   # never returns
     cli
-    hlt
+    hlt0:
+        hlt
+        jmp hlt0
-#ifdef CONFIG_FB
-.code32
-vesa_init:
-    jmp $gdtselector(VESA_INIT_DES), $vesa_init_real - vesa_init
-.code16
-vesa_init_real:
-    mov %cr0, %eax
-    and $~1, %eax
-    mov %eax, %cr0
-    jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
-vesa_init_real2:
-    mov $VESA_INIT_SEGMENT, %bx
-    mov %bx, %es
-    mov %bx, %fs
-    mov %bx, %gs
-    mov %bx, %ds
-    mov %bx, %ss
-    movl $0x0000fffc, %esp
-    movl $0x0000fffc, %ebp
-#define VESA_INFO_SIZE 1024
-#define VESA_MODE_ATTRIBUTES_OFFSET 0
-#define VESA_MODE_LIST_PTR_OFFSET 14
-#define VESA_MODE_SCANLINE_OFFSET 16
-#define VESA_MODE_WIDTH_OFFSET 18
-#define VESA_MODE_HEIGHT_OFFSET 20
-#define VESA_MODE_BPP_OFFSET 25
-#define VESA_MODE_PHADDR_OFFSET 40
-#define VESA_END_OF_MODES 0xffff
-#define VESA_OK 0x4f
-#define VESA_GET_INFO 0x4f00
-#define VESA_GET_MODE_INFO 0x4f01
-#define VESA_SET_MODE 0x4f02
-#define VESA_SET_PALETTE 0x4f09
-#define CONFIG_VESA_BPP_a 255
-#if CONFIG_VESA_BPP == 24
-#define CONFIG_VESA_BPP_VARIANT 32
-#endif
-    mov $VESA_GET_INFO, %ax
-    mov $e_vesa_init - vesa_init, %di
-    push %di
-    int $0x10
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 0f
-    mov 2 + VESA_MODE_LIST_PTR_OFFSET(%di), %si
-    mov %si, %gs
-    mov VESA_MODE_LIST_PTR_OFFSET(%di), %si
-    add $VESA_INFO_SIZE, %di
-:# Try next mode
-    mov %gs:(%si), %cx
-    cmp $VESA_END_OF_MODES, %cx
-    jz 0f
-    inc %si
-    inc %si
-    push %cx
-    push %di
-    push %si
-    mov $VESA_GET_MODE_INFO, %ax
-    int $0x10
-    pop %si
-    pop %di
-    pop %cx
-    cmp $VESA_OK, %al
-    jnz 0f
-    mov $CONFIG_VESA_WIDTH, %ax
-    cmp VESA_MODE_WIDTH_OFFSET(%di), %ax
-    jnz 1b
-    mov $CONFIG_VESA_HEIGHT, %ax
-    cmp VESA_MODE_HEIGHT_OFFSET(%di), %ax
-    jnz 1b
-    mov $CONFIG_VESA_BPP, %al
-    cmp VESA_MODE_BPP_OFFSET(%di), %al
-#ifdef CONFIG_VESA_BPP_VARIANT
-    jz 2f
-    mov $CONFIG_VESA_BPP_VARIANT, %al
-    cmp VESA_MODE_BPP_OFFSET(%di), %al
-#endif
-    jnz 1b
-:
-    mov %cx, %bx
-    or $0xc000, %bx
-    push %di
-    mov $VESA_SET_MODE, %ax
-    int $0x10
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 0f
-#if CONFIG_VESA_BPP == 8
-    # Set 3:2:3 VGA palette
-    mov VESA_MODE_ATTRIBUTES_OFFSET(%di), %ax
-    push %di
-    mov $vga323 - vesa_init, %di
-    mov $0x100, %ecx
-    bt $5, %ax                      # Test if VGA compatible registers are present
-    jnc vga_compat
-        # Try VESA routine to set palette
-        mov $VESA_SET_PALETTE, %ax
-        xor %bl, %bl
-        xor %dx, %dx
-        int $0x10
-        jmp vga_not_compat
-    vga_compat:
-        # Try VGA registers to set palette
-        movw $0x3c6, %dx                # Set palette mask
-        movb $0xff, %al
-        outb %al, %dx
-        movw $0x3c8, %dx                # First index to set
-        xor %al, %al
-        outb %al, %dx
-        movw $0x3c9, %dx                # Data port
-        vga_loop:
-            movb %es:2(%di), %al
-            outb %al, %dx
-            movb %es:1(%di), %al
-            outb %al, %dx
-            movb %es:(%di), %al
-            outb %al, %dx
-            addw $4, %di
-            loop vga_loop
-    vga_not_compat:
-    pop %di
-#endif
-    mov VESA_MODE_PHADDR_OFFSET(%di), %esi
-    mov VESA_MODE_WIDTH_OFFSET(%di), %ax
-    shl $16, %eax
-    mov VESA_MODE_HEIGHT_OFFSET(%di), %ax
-    mov VESA_MODE_BPP_OFFSET(%di), %bl
-    xor %bh, %bh
-    shl $16, %ebx
-    mov VESA_MODE_SCANLINE_OFFSET(%di), %bx
-    mov %eax, %edi
-:
-    mov %cr0, %eax
-    or $1, %eax
-    mov %eax, %cr0
-    jmp 9f
-:
-    ljmpl $gdtselector(KTEXT32_DES), $(vesa_init_protect - vesa_init + VESA_INIT_SEGMENT << 4)
-:# No prefered mode found
-    mov $0x111, %cx
-    push %di
-    push %cx
-    mov $VESA_GET_MODE_INFO, %ax
-    int $0x10
-    pop %cx
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 1f
-    jz 2b                       # Force relative jump
-:
-    mov $0x0003, %ax
-    int $0x10
-    mov $0xffffffff, %edi               # EGA text mode used, because of problems with VESA
-    xor %ax, %ax
-    jz 8b                       # Force relative jump
-vga323:
-#include "vga323.pal"
-.code32
-vesa_init_protect:
-    movw $gdtselector(KDATA_DES), %cx
-    movw %cx, %es
-    movw %cx, %ds                   # kernel data + stack
-    movw %cx, %ss
-    # Simics seems to remove hidden part of GS on entering user mode
-    #  when _visible_ part of GS does not point to user-mode segment
-    movw $gdtselector(UDATA_DES), %cx
-    movw %cx, %fs
-    movw %cx, %gs
-    movl $START_STACK, %esp             # initialize stack pointer
-    jmpl $gdtselector(KTEXT32_DES), $vesa_meeting_point
-.align 4
-e_vesa_init:
-#endif
 # Print string from %esi to EGA display (in red) and halt
 error_halt:
-    movl $0xb8000, %edi             # base of EGA text mode memory
+    movl $0xb8000, %edi       # base of EGA text mode memory
     xorl %eax, %eax
-    movw $0x3d4, %dx                # read bits 8 - 15 of the cursor address
+    movw $0x3d4, %dx          # read bits 8 - 15 of the cursor address
     movb $0xe, %al
     outb %al, %dx
 ,7 → 195,7
     inb %dx, %al
     shl $8, %ax
-    movw $0x3d4, %dx                # read bits 0 - 7 of the cursor address
+    movw $0x3d4, %dx          # read bits 0 - 7 of the cursor address
     movb $0xf, %al
     outb %al, %dx
 ,7 → 204,9
     cmp $1920, %ax
     jbe cursor_ok
-        movw $1920, %ax             # sanity check for the cursor on the last line
+        movw $1920, %ax       # sanity check for the cursor on the last line
     cursor_ok:
     movw %ax, %bx
 ,7 → 213,7
     shl $1, %eax
     addl %eax, %edi
-    movw $0x0c00, %ax               # black background, light red foreground
+    movw $0x0c00, %ax         # black background, light red foreground
     ploop:
         lodsb
 ,11 → 220,11
         cmp $0, %al
         je ploop_end
         stosw
-        inc %bx
+        inc %bx
         jmp ploop
     ploop_end:
-    movw $0x3d4, %dx                # write bits 8 - 15 of the cursor address
+    movw $0x3d4, %dx          # write bits 8 - 15 of the cursor address
     movb $0xe, %al
     outb %al, %dx
 ,7 → 232,7
     movb %bh, %al
     outb %al, %dx
-    movw $0x3d4, %dx                # write bits 0 - 7 of the cursor address
+    movw $0x3d4, %dx          # write bits 0 - 7 of the cursor address
     movb $0xf, %al
     outb %al, %dx
 ,17 → 239,20
     movw $0x3d5, %dx
     movb %bl, %al
     outb %al, %dx
     cli
-    hlt
+    hlt1:
+        hlt
+        jmp hlt1
+#include "vesa_real.inc"
 .section K_INI_PTLS, "aw", @progbits
 #
 # Macro for generating initial page table contents.
-# @param cnt    Number of entries to generat. Must be multiple of 8.
-# @param g  Number of GB that will be added to the mapping.
+# @param cnt Number of entries to generat. Must be multiple of 8.
+# @param g   Number of GB that will be added to the mapping.
 #
 .macro ptl2gen cnt g
 .if \cnt
 ,7 → 304,7
     # Mapping of [0; 1G) at -2G
     .quad ptl_2_0g + (PTL_WRITABLE | PTL_PRESENT)
     .fill 1, 8, 0
 .align 4096
 .global ptl_0
 ptl_0:

/branches/network/kernel/arch/amd64/src/boot/vesa_real.inc
0,0 → 1,0
link ../../../ia32/src/boot/vesa_real.inc
Property changes:
Added: svn:special
+*
\ No newline at end of property

/branches/network/kernel/arch/amd64/src/boot/vesa_prot.inc
0,0 → 1,0
link ../../../ia32/src/boot/vesa_prot.inc
Property changes:
Added: svn:special
+*
\ No newline at end of property

 /branches/network/kernel/arch/amd64/src/boot/memmap.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64mm
+/** @addtogroup amd64mm
  * @{
  */
 /** @file

 /branches/network/kernel/arch/amd64/src/debugger.c
 ,7 → 35,6
 #include <arch/debugger.h>
 #include <console/kconsole.h>
 #include <console/cmd.h>
-#include <symtab.h>
 #include <print.h>
 #include <panic.h>
 #include <interrupt.h>
 ,6 → 43,7
 #include <debug.h>
 #include <func.h>
 #include <smp/ipi.h>
+#include <symtab.h>
 typedef struct  {
     uintptr_t address;      /**< Breakpoint address */
 ,6 → 54,8
 static bpinfo_t breakpoints[BKPOINTS_MAX];
 SPINLOCK_INITIALIZE(bkpoint_lock);
+#ifdef CONFIG_KCONSOLE
 static int cmd_print_breakpoints(cmd_arg_t *argv);
 static cmd_info_t bkpts_info = {
     .name = "bkpts",
 ,8 → 64,6
     .argc = 0,
 };
-#ifndef CONFIG_DEBUG_AS_WATCHPOINT
 static int cmd_del_breakpoint(cmd_arg_t *argv);
 static cmd_arg_t del_argv = {
     .type = ARG_TYPE_INT
 ,44 → 99,8
     .argv = &addw_argv
 };
-#endif
+#endif /* CONFIG_KCONSOLE */
-/** Print table of active breakpoints */
-int cmd_print_breakpoints(cmd_arg_t *argv __attribute__((unused)))
-{
-    unsigned int i;
-    char *symbol;
-#ifdef __32_BITS__
-    printf("#  Count Address    In symbol\n");
-    printf("-- ----- ---------- ---------\n");
-#endif
-#ifdef __64_BITS__
-    printf("#  Count Address            In symbol\n");
-    printf("-- ----- ------------------ ---------\n");
-#endif
-    for (i = 0; i < BKPOINTS_MAX; i++)
-        if (breakpoints[i].address) {
-            symbol = get_symtab_entry(breakpoints[i].address);
-#ifdef __32_BITS__
-            printf("%-2u %-5d %#10zx %s\n", i,
-                breakpoints[i].counter, breakpoints[i].address,
-                symbol);
-#endif
-#ifdef __64_BITS__
-            printf("%-2u %-5d %#18zx %s\n", i,
-                breakpoints[i].counter, breakpoints[i].address,
-                symbol);
-#endif
-        }
-    return 1;
-}
 /* Setup DR register according to table */
 static void setup_dr(int curidx)
 {
 ,16 → 201,16
     /* Send IPI */
 #ifdef CONFIG_SMP
-//  ipi_broadcast(VECTOR_DEBUG_IPI);
+//  ipi_broadcast(VECTOR_DEBUG_IPI);
 #endif
     return curidx;
 }
-#ifdef amd64
-#   define getip(x) ((x)->rip)
+#ifdef __64_BITS__
+    #define getip(x)  ((x)->rip)
 #else
-#   define getip(x) ((x)->eip)
+    #define getip(x)  ((x)->eip)
 #endif
 static void handle_exception(int slot, istate_t *istate)
 ,12 → 229,15
                 *((unative_t *) breakpoints[slot].address));
         }
     }
-    printf("Reached breakpoint %d:%lx(%s)\n", slot, getip(istate),
-        get_symtab_entry(getip(istate)));
-    printf("***Type 'exit' to exit kconsole.\n");
-    atomic_set(&haltstate,1);
-    kconsole((void *) "debug");
-    atomic_set(&haltstate,0);
+    printf("Reached breakpoint %d:%lx (%s)\n", slot, getip(istate),
+        symtab_fmt_name_lookup(getip(istate)));
+#ifdef CONFIG_KCONSOLE
+    atomic_set(&haltstate, 1);
+    kconsole("debug", "Debug console ready.\n", false);
+    atomic_set(&haltstate, 0);
+#endif
 }
 void breakpoint_del(int slot)
 ,42 → 266,8
 #endif
 }
-#ifndef CONFIG_DEBUG_AS_WATCHPOINT
-/** Remove breakpoint from table */
-int cmd_del_breakpoint(cmd_arg_t *argv)
-{
-    unative_t bpno = argv->intval;
-    if (bpno > BKPOINTS_MAX) {
-        printf("Invalid breakpoint number.\n");
-        return 0;
-    }
-    breakpoint_del(argv->intval);
-    return 1;
-}
-/** Add new breakpoint to table */
-static int cmd_add_breakpoint(cmd_arg_t *argv)
-{
-    int flags;
-    int id;
-    if (argv == &add_argv) {
-        flags = BKPOINT_INSTR;
-    } else { /* addwatchp */
-        flags = BKPOINT_WRITE;
-    }
-    printf("Adding breakpoint on address: %p\n", argv->intval);
-    id = breakpoint_add((void *)argv->intval, flags, -1);
-    if (id < 0)
-        printf("Add breakpoint failed.\n");
-    else
-        printf("Added breakpoint %d.\n", id);
-    return 1;
-}
-#endif
 static void debug_exception(int n __attribute__((unused)), istate_t *istate)
 {
     unative_t dr6;
 ,7 → 274,7
     int i;
     /* Set RF to restart the instruction  */
-#ifdef amd64
+#ifdef __64_BITS__
     istate->rflags |= RFLAGS_RF;
 #else
     istate->eflags |= EFLAGS_RF;
 ,24 → 312,24
     for (i = 0; i < BKPOINTS_MAX; i++)
         breakpoints[i].address = NULL;
+#ifdef CONFIG_KCONSOLE
     cmd_initialize(&bkpts_info);
     if (!cmd_register(&bkpts_info))
-        panic("could not register command %s\n", bkpts_info.name);
+        printf("Cannot register command %s\n", bkpts_info.name);
-#ifndef CONFIG_DEBUG_AS_WATCHPOINT
     cmd_initialize(&delbkpt_info);
     if (!cmd_register(&delbkpt_info))
-        panic("could not register command %s\n", delbkpt_info.name);
+        printf("Cannot register command %s\n", delbkpt_info.name);
     cmd_initialize(&addbkpt_info);
     if (!cmd_register(&addbkpt_info))
-        panic("could not register command %s\n", addbkpt_info.name);
+        printf("Cannot register command %s\n", addbkpt_info.name);
     cmd_initialize(&addwatchp_info);
     if (!cmd_register(&addwatchp_info))
-        panic("could not register command %s\n", addwatchp_info.name);
-#endif
+        printf("Cannot register command %s\n", addwatchp_info.name);
+#endif /* CONFIG_KCONSOLE */
     exc_register(VECTOR_DEBUG, "debugger", debug_exception);
 #ifdef CONFIG_SMP
 ,5 → 337,77
 #endif
 }
+#ifdef CONFIG_KCONSOLE
+/** Print table of active breakpoints */
+int cmd_print_breakpoints(cmd_arg_t *argv __attribute__((unused)))
+{
+    unsigned int i;
+    char *symbol;
+#ifdef __32_BITS__
+    printf("#  Count Address    In symbol\n");
+    printf("-- ----- ---------- ---------\n");
+#endif
+#ifdef __64_BITS__
+    printf("#  Count Address            In symbol\n");
+    printf("-- ----- ------------------ ---------\n");
+#endif
+    for (i = 0; i < BKPOINTS_MAX; i++)
+        if (breakpoints[i].address) {
+            symbol = symtab_fmt_name_lookup(
+                breakpoints[i].address);
+#ifdef __32_BITS__
+            printf("%-2u %-5d %#10zx %s\n", i,
+                breakpoints[i].counter, breakpoints[i].address,
+                symbol);
+#endif
+#ifdef __64_BITS__
+            printf("%-2u %-5d %#18zx %s\n", i,
+                breakpoints[i].counter, breakpoints[i].address,
+                symbol);
+#endif
+        }
+    return 1;
+}
+/** Remove breakpoint from table */
+int cmd_del_breakpoint(cmd_arg_t *argv)
+{
+    unative_t bpno = argv->intval;
+    if (bpno > BKPOINTS_MAX) {
+        printf("Invalid breakpoint number.\n");
+        return 0;
+    }
+    breakpoint_del(argv->intval);
+    return 1;
+}
+/** Add new breakpoint to table */
+static int cmd_add_breakpoint(cmd_arg_t *argv)
+{
+    int flags;
+    int id;
+    if (argv == &add_argv) {
+        flags = BKPOINT_INSTR;
+    } else { /* addwatchp */
+        flags = BKPOINT_WRITE;
+    }
+    printf("Adding breakpoint on address: %p\n", argv->intval);
+    id = breakpoint_add((void *)argv->intval, flags, -1);
+    if (id < 0)
+        printf("Add breakpoint failed.\n");
+    else
+        printf("Added breakpoint %d.\n", id);
+    return 1;
+}
+#endif /* CONFIG_KCONSOLE */
 /** @}
  */

 /branches/network/kernel/arch/amd64/src/mm/page.c
 ,7 → 180,7
     page = read_cr2();
     if (istate->error_word & PFERR_CODE_RSVD)
-        panic("Reserved bit set in page table entry.\n");
+        panic("Reserved bit set in page table entry.");
     if (istate->error_word & PFERR_CODE_RW)
         access = PF_ACCESS_WRITE;
 ,11 → 190,11
         access = PF_ACCESS_READ;
     if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
-        fault_if_from_uspace(istate, "Page fault: %#x", page);
+        fault_if_from_uspace(istate, "Page fault: %#x.", page);
         decode_istate(n, istate);
-        printf("Page fault address: %llx\n", page);
-        panic("page fault\n");
+        printf("Page fault address: %llx.\n", page);
+        panic("Page fault.");
     }
 }
 ,7 → 202,7
 uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
     if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
-        panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
+        panic("Unable to map physical memory %p (%d bytes).", physaddr, size)
     uintptr_t virtaddr = PA2KA(last_frame);
     pfn_t i;

 /branches/network/kernel/arch/amd64/src/userspace.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup amd64
+/** @addtogroup amd64
  * @{
  */
 /** @file
 ,36 → 47,33
  */
 void userspace(uspace_arg_t *kernel_uarg)
 {
-    ipl_t ipl;
+    ipl_t ipl = interrupts_disable();
-    ipl = interrupts_disable();
-    /* Clear CF,PF,AF,ZF,SF,DF,OF */
+    /* Clear CF, PF, AF, ZF, SF, DF, OF */
     ipl &= ~(0xcd4);
-    asm volatile (""
-              "pushq %0\n"
-              "pushq %1\n"
-              "pushq %2\n"
-              "pushq %3\n"
-              "pushq %4\n"
-              "movq %5, %%rax\n"
-              /* %rdi is defined to hold pcb_ptr - set it to 0 */
-              "xorq %%rdi, %%rdi\n"
-              "iretq\n"
-              : :
-              "i" (gdtselector(UDATA_DES) | PL_USER),
-              "r" (kernel_uarg->uspace_stack+THREAD_STACK_SIZE),
-              "r" (ipl),
-              "i" (gdtselector(UTEXT_DES) | PL_USER),
-              "r" (kernel_uarg->uspace_entry),
-              "r" (kernel_uarg->uspace_uarg)
-              : "rax"
-              );
+    asm volatile (
+            "pushq %[udata_des]\n"
+            "pushq %[stack_size]\n"
+            "pushq %[ipl]\n"
+            "pushq %[utext_des]\n"
+            "pushq %[entry]\n"
+            "movq %[uarg], %%rax\n"
+            /* %rdi is defined to hold pcb_ptr - set it to 0 */
+            "xorq %%rdi, %%rdi\n"
+            "iretq\n"
+            :: [udata_des] "i" (gdtselector(UDATA_DES) | PL_USER),
+               [stack_size] "r" (kernel_uarg->uspace_stack + THREAD_STACK_SIZE),
+               [ipl] "r" (ipl),
+               [utext_des] "i" (gdtselector(UTEXT_DES) | PL_USER),
+               [entry] "r" (kernel_uarg->uspace_entry),
+               [uarg] "r" (kernel_uarg->uspace_uarg)
+            : "rax"
+        );
     /* Unreachable */
-    for(;;)
-        ;
+    while (1);
 }
 /** @}

 /branches/network/kernel/arch/amd64/src/interrupt.c
 ,7 → 43,6
 #include <mm/tlb.h>
 #include <mm/as.h>
 #include <arch.h>
-#include <symtab.h>
 #include <arch/asm.h>
 #include <proc/scheduler.h>
 #include <proc/thread.h>
 ,6 → 51,7
 #include <arch/ddi/ddi.h>
 #include <interrupt.h>
 #include <ddi/irq.h>
+#include <symtab.h>
 /*
  * Interrupt and exception dispatching.
 ,10 → 64,8
 void decode_istate(int n, istate_t *istate)
 {
     char *symbol;
-/*  uint64_t *x = &istate->stack[0]; */
-    if (!(symbol = get_symtab_entry(istate->rip)))
-        symbol = "";
+    symbol = symtab_fmt_name_lookup(istate->rip);
     printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n", n, __func__);
     printf("%%rip: %#llx (%s)\n", istate->rip, symbol);
 ,12 → 78,6
         istate->rdi, istate->r8);
     printf("%%r9=%#llx, %%r10=%#llx, %%r11=%#llx\n", istate->r9,
         istate->r10, istate->r11);
-#ifdef CONFIG_DEBUG_ALLREGS
-    printf("%%r12=%#llx, %%r13=%#llx, %%r14=%#llx\n", istate->r12,
-        istate->r13, istate->r14);
-    printf("%%r15=%#llx, %%rbx=%#llx, %%rbp=%#llx\n", istate->r15,
-        istate->rbx, &istate->rbp);
-#endif
     printf("%%rsp=%#llx\n", &istate->stack[0]);
 }
 ,15 → 86,15
     if (eoi_function)
         eoi_function();
     else
-        panic("no eoi_function\n");
+        panic("No eoi_function.");
 }
 static void null_interrupt(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "unserviced interrupt: %d", n);
+    fault_if_from_uspace(istate, "Unserviced interrupt: %d.", n);
     decode_istate(n, istate);
-    panic("unserviced interrupt\n");
+    panic("Unserviced interrupt.");
 }
 /** General Protection Fault. */
 ,35 → 118,37
             io_perm_bitmap_install();
             return;
         }
-        fault_if_from_uspace(istate, "general protection fault");
+        fault_if_from_uspace(istate, "General protection fault.");
     }
     decode_istate(n, istate);
-    panic("general protection fault\n");
+    panic("General protection fault.");
 }
 static void ss_fault(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "stack fault");
+    fault_if_from_uspace(istate, "Stack fault.");
     decode_istate(n, istate);
-    panic("stack fault\n");
+    panic("Stack fault.");
 }
 static void nm_fault(int n, istate_t *istate)
 {
-#ifdef CONFIG_FPU_LAZY
+#ifdef CONFIG_FPU_LAZY
     scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "fpu fault");
-    panic("fpu fault");
+    fault_if_from_uspace(istate, "FPU fault.");
+    panic("FPU fault.");
 #endif
 }
+#ifdef CONFIG_SMP
 static void tlb_shootdown_ipi(int n, istate_t *istate)
 {
     trap_virtual_eoi();
     tlb_shootdown_ipi_recv();
 }
+#endif
 /** Handler of IRQ exceptions */
 static void irq_interrupt(int n, istate_t *istate)
 ,7 → 171,7
             trap_virtual_eoi();
             ack = true;
         }
-        irq->handler(irq, irq->arg);
+        irq->handler(irq);
         spinlock_unlock(&irq->lock);
     } else {
         /*
 ,7 → 215,7
     if (enable_irqs_function)
         enable_irqs_function(irqmask);
     else
-        panic("no enable_irqs_function\n");
+        panic("No enable_irqs_function.");
 }
 void trap_virtual_disable_irqs(uint16_t irqmask)
 ,7 → 223,7
     if (disable_irqs_function)
         disable_irqs_function(irqmask);
     else
-        panic("no disable_irqs_function\n");
+        panic("No disable_irqs_function.");
 }
 /** @}

 /branches/network/kernel/arch/mips32/_link.ld.in
 ,15 → 1,17
 /*
- *  MIPS32 linker script
- *
+ * MIPS32 linker script
+ *
  *  kernel text
  *  kernel data
- *
+ *
  */
 #undef mips
 #define mips mips
+#define KERNEL_LOAD_ADDRESS 0x80100000
 OUTPUT_ARCH(mips)
 ENTRY(kernel_image_start)
 SECTIONS {
 ,9 → 23,9
     }
     .data : {
         kdata_start = .;
-        *(.data);       /* initialized data */
+        *(.data);                       /* initialized data */
         hardcoded_ktext_size = .;
-        LONG(ktext_end - ktext_start);
+        LONG(ktext_end - ktext_start);
         hardcoded_kdata_size = .;
         LONG(kdata_end - kdata_start);
         hardcoded_load_address = .;
 ,21 → 35,21
         *(.reginfo);
         *(.sbss);
         *(.scommon);
-        *(.bss);        /* uninitialized static variables */
-        *(COMMON);      /* global variables */
+        *(.bss);                        /* uninitialized static variables */
+        *(COMMON);                      /* global variables */
         symbol_table = .;
-        *(symtab.*);
+        *(symtab.*);
     }
     _gp = . + 0x8000;
     .lit8 : { *(.lit8) }
     .lit4 : { *(.lit4) }
     kdata_end = .;
     /DISCARD/ : {
-      *(.mdebug*);
-      *(.pdr);
-      *(.comment);
-      *(.note);
+        *(.mdebug*);
+        *(.pdr);
+        *(.comment);
+        *(.note);
     }
 }

 /branches/network/kernel/arch/mips32/include/context_offset.h
 ,26 → 76,17
 #define EOFFSET_T5     0x30
 #define EOFFSET_T6     0x34
 #define EOFFSET_T7     0x38
-#define EOFFSET_S0     0x3c
-#define EOFFSET_S1     0x40
-#define EOFFSET_S2     0x44
-#define EOFFSET_S3     0x48
-#define EOFFSET_S4     0x4c
-#define EOFFSET_S5     0x50
-#define EOFFSET_S6     0x54
-#define EOFFSET_S7     0x58
-#define EOFFSET_T8     0x5c
-#define EOFFSET_T9     0x60
-#define EOFFSET_GP     0x64
-#define EOFFSET_SP     0x68
-#define EOFFSET_S8     0x6c
-#define EOFFSET_RA     0x70
-#define EOFFSET_LO     0x74
-#define EOFFSET_HI     0x78
-#define EOFFSET_STATUS 0x7c
-#define EOFFSET_EPC    0x80
-#define EOFFSET_K1     0x84
-#define REGISTER_SPACE 136
+#define EOFFSET_T8     0x3c
+#define EOFFSET_T9     0x40
+#define EOFFSET_GP     0x44
+#define EOFFSET_SP     0x48
+#define EOFFSET_RA     0x4c
+#define EOFFSET_LO     0x50
+#define EOFFSET_HI     0x54
+#define EOFFSET_STATUS 0x58
+#define EOFFSET_EPC    0x5c
+#define EOFFSET_K1     0x60
+#define REGISTER_SPACE 100
 #ifdef __ASM__
 ,10 → 105,10
     sw $s8,OFFSET_S8(\ctx)
     sw $gp,OFFSET_GP(\ctx)
-#ifndef KERNEL
+#ifndef KERNEL
     sw $k1,OFFSET_TLS(\ctx)
-# ifdef CONFIG_MIPS_FPU
+#ifdef CONFIG_FPU
     mfc1 $t0,$20
     sw $t0, OFFSET_F20(\ctx)
 ,7 → 141,7
     mfc1 $t0,$30
     sw $t0, OFFSET_F30(\ctx)
-# endif /* CONFIG_MIPS_FPU */
+#endif /* CONFIG_FPU */
 #endif /* KERNEL */
     sw $ra,OFFSET_PC(\ctx)
 ,7 → 163,7
 #ifndef KERNEL
     lw $k1,OFFSET_TLS(\ctx)
-# ifdef CONFIG_MIPS_FPU
+#ifdef CONFIG_FPU
     lw $t0, OFFSET_F20(\ctx)
     mtc1 $t0,$20
 ,9 → 196,9
     lw $t0, OFFSET_F30(\ctx)
     mtc1 $t0,$30
-# endif /* CONFIG_MIPS_FPU */
+#endif /* CONFIG_FPU */
 #endif /* KERNEL */
     lw $ra,OFFSET_PC(\ctx)
     lw $sp,OFFSET_SP(\ctx)
 .endm

 /branches/network/kernel/arch/mips32/include/asm/boot.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32
+/** @addtogroup mips32
  * @{
  */
 /** @file

 /branches/network/kernel/arch/mips32/include/interrupt.h
 ,9 → 38,11
 #include <typedefs.h>
 #include <arch/exception.h>
-#define IVT_ITEMS 32
-#define IVT_FIRST 0
+#define IVT_ITEMS  32
+#define IVT_FIRST  0
+#define VECTOR_TLB_SHOOTDOWN_IPI  EXC_Int
 extern function virtual_timer_fnc;
 extern uint32_t count_hi;

 /branches/network/kernel/arch/mips32/include/exception.h
 ,19 → 73,10
     uint32_t t5;
     uint32_t t6;
     uint32_t t7;
-    uint32_t s0;
-    uint32_t s1;
-    uint32_t s2;
-    uint32_t s3;
-    uint32_t s4;
-    uint32_t s5;
-    uint32_t s6;
-    uint32_t s7;
     uint32_t t8;
     uint32_t t9;
     uint32_t gp;
     uint32_t sp;
-    uint32_t s8;
     uint32_t ra;
     uint32_t lo;

 /branches/network/kernel/arch/mips32/include/console.h
 ,8 → 35,6
 #ifndef KERN_mips32_CONSOLE_H_
 #define KERN_mips32_CONSOLE_H_
-extern void console_init(devno_t devno);
 #endif
 /** @}

 /branches/network/kernel/arch/mips32/include/types.h
 ,6 → 57,9
 typedef uint32_t unative_t;
 typedef int32_t native_t;
+typedef struct {
+} fncptr_t;
 #define PRIp "x"    /**< Format for uintptr_t. */
 #define PRIs "u"    /**< Format for size_t. */
 #define PRIc "u"    /**< Format for count_t. */

 /branches/network/kernel/arch/mips32/include/smp/dorder.h
 ,0 → 1,34
+/*
+ * Copyright (c) 2007 Martin Decky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef KERN_mips32_DORDER_H_
+#define KERN_mips32_DORDER_H_
+extern void ipi_broadcast_arch(int ipi);
+#endif

 /branches/network/kernel/arch/mips32/include/atomic.h
 ,14 → 35,14
 #ifndef KERN_mips32_ATOMIC_H_
 #define KERN_mips32_ATOMIC_H_
-#define atomic_inc(x)   ((void) atomic_add(x, 1))
-#define atomic_dec(x)   ((void) atomic_add(x, -1))
+#define atomic_inc(x)  ((void) atomic_add(x, 1))
+#define atomic_dec(x)  ((void) atomic_add(x, -1))
-#define atomic_postinc(x) (atomic_add(x, 1) - 1)
-#define atomic_postdec(x) (atomic_add(x, -1) + 1)
+#define atomic_postinc(x)  (atomic_add(x, 1) - 1)
+#define atomic_postdec(x)  (atomic_add(x, -1) + 1)
-#define atomic_preinc(x) atomic_add(x, 1)
-#define atomic_predec(x) atomic_add(x, -1)
+#define atomic_preinc(x)  atomic_add(x, 1)
+#define atomic_predec(x)  atomic_add(x, -1)
 /* Atomic addition of immediate value.
  *
 ,19 → 54,37
 static inline long atomic_add(atomic_t *val, int i)
 {
     long tmp, v;
     asm volatile (
         "1:\n"
         "   ll %0, %1\n"
-        "   addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
-        "       move %2, %0\n"
+        "   addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
+        "   move %2, %0\n"
         "   sc %0, %1\n"
-        "   beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
+        "   beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
         "   nop\n"
         : "=&r" (tmp), "+m" (val->count), "=&r" (v)
         : "r" (i), "i" (0)
-        );
+    );
+    return v;
+}
+static inline uint32_t test_and_set(atomic_t *val) {
+    uint32_t tmp, v;
+    asm volatile (
+        "1:\n"
+        "   ll %2, %1\n"
+        "   bnez %2, 2f\n"
+        "   li %0, %3\n"
+        "   sc %0, %1\n"
+        "   beqz %0, 1b\n"
+        "2:\n"
+        : "=&r" (tmp), "+m" (val->count), "=&r" (v)
+        : "i" (1)
+    );
     return v;
 }

 /branches/network/kernel/arch/mips32/include/arch.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32
+/** @addtogroup mips32
  * @{
  */
 /** @file
 ,6 → 35,29
 #ifndef KERN_mips32_ARCH_H_
 #define KERN_mips32_ARCH_H_
+#define TASKMAP_MAX_RECORDS  32
+#define CPUMAP_MAX_RECORDS   32
+#define BOOTINFO_TASK_NAME_BUFLEN 32
+#include <typedefs.h>
+extern count_t cpu_count;
+typedef struct {
+    uintptr_t addr;
+    uint32_t size;
+    char name[BOOTINFO_TASK_NAME_BUFLEN];
+} utask_t;
+typedef struct {
+    uint32_t cpumap;
+    uint32_t cnt;
+    utask_t tasks[TASKMAP_MAX_RECORDS];
+} bootinfo_t;
+extern void arch_pre_main(void *entry, bootinfo_t *bootinfo);
 #endif
 /** @}

 /branches/network/kernel/arch/mips32/include/asm.h
 ,6 → 36,7
 #define KERN_mips32_ASM_H_
 #include <arch/types.h>
+#include <typedefs.h>
 #include <config.h>
 ,7 → 56,11
 {
     uintptr_t v;
-    asm volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
+    asm volatile (
+        "and %0, $29, %1\n"
+        : "=r" (v)
+        : "r" (~(STACK_SIZE-1))
+    );
     return v;
 }
 ,13 → 68,44
 extern void cpu_halt(void);
 extern void asm_delay_loop(uint32_t t);
 extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
-              uintptr_t entry);
+    uintptr_t entry);
 extern ipl_t interrupts_disable(void);
 extern ipl_t interrupts_enable(void);
 extern void interrupts_restore(ipl_t ipl);
 extern ipl_t interrupts_read(void);
+extern void asm_delay_loop(uint32_t t);
+static inline void pio_write_8(ioport8_t *port, uint8_t v)
+{
+    *port = v;
+}
+static inline void pio_write_16(ioport16_t *port, uint16_t v)
+{
+    *port = v;
+}
+static inline void pio_write_32(ioport32_t *port, uint32_t v)
+{
+    *port = v;
+}
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
+    return *port;
+}
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    return *port;
+}
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    return *port;
+}
 #endif
 /** @}

 /branches/network/kernel/arch/mips32/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm
  * @{
  */
 /** @file
 ,12 → 35,14
 #ifndef KERN_mips32_FRAME_H_
 #define KERN_mips32_FRAME_H_
-#define FRAME_WIDTH     14  /* 16K */
-#define FRAME_SIZE      (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  14  /* 16K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifdef KERNEL
 #ifndef __ASM__
+#include <typedefs.h>
 extern void frame_arch_init(void);
 extern void physmem_print(void);

 /branches/network/kernel/arch/mips32/include/mm/asid.h
 ,7 → 37,7
 #include <arch/types.h>
-#define ASID_MAX_ARCH       255 /* 2^8 - 1 */
+#define ASID_MAX_ARCH  255    /* 2^8 - 1 */
 typedef uint8_t asid_t;

 /branches/network/kernel/arch/mips32/include/mm/tlb.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm
  * @{
  */
 /** @file
 ,42 → 40,38
 #include <arch/mm/asid.h>
 #include <arch/exception.h>
-#ifdef TLBCNT
-#   define TLB_ENTRY_COUNT      TLBCNT
-#else
-#   define TLB_ENTRY_COUNT      48
-#endif
+#define TLB_ENTRY_COUNT  48
-#define TLB_WIRED       1
-#define TLB_KSTACK_WIRED_INDEX  0
+#define TLB_WIRED               1
+#define TLB_KSTACK_WIRED_INDEX  0
-#define TLB_PAGE_MASK_4K    (0x000 << 13)
-#define TLB_PAGE_MASK_16K   (0x003 << 13)
-#define TLB_PAGE_MASK_64K   (0x00f << 13)
-#define TLB_PAGE_MASK_256K  (0x03f << 13)
-#define TLB_PAGE_MASK_1M    (0x0ff << 13)
-#define TLB_PAGE_MASK_4M    (0x3ff << 13)
-#define TLB_PAGE_MASK_16M   (0xfff << 13)
+#define TLB_PAGE_MASK_4K    (0x000 << 13)
+#define TLB_PAGE_MASK_16K   (0x003 << 13)
+#define TLB_PAGE_MASK_64K   (0x00f << 13)
+#define TLB_PAGE_MASK_256K  (0x03f << 13)
+#define TLB_PAGE_MASK_1M    (0x0ff << 13)
+#define TLB_PAGE_MASK_4M    (0x3ff << 13)
+#define TLB_PAGE_MASK_16M   (0xfff << 13)
-#define PAGE_UNCACHED           2
-#define PAGE_CACHEABLE_EXC_WRITE    5
+#define PAGE_UNCACHED             2
+#define PAGE_CACHEABLE_EXC_WRITE  5
 typedef union {
     struct {
 #ifdef BIG_ENDIAN
-        unsigned : 2;       /* zero */
-        unsigned pfn : 24;  /* frame number */
-        unsigned c : 3;     /* cache coherency attribute */
-        unsigned d : 1;     /* dirty/write-protect bit */
-        unsigned v : 1;     /* valid bit */
-        unsigned g : 1;     /* global bit */
+        unsigned : 2;       /* zero */
+        unsigned pfn : 24;  /* frame number */
+        unsigned c : 3;     /* cache coherency attribute */
+        unsigned d : 1;     /* dirty/write-protect bit */
+        unsigned v : 1;     /* valid bit */
+        unsigned g : 1;     /* global bit */
 #else
-        unsigned g : 1;     /* global bit */
-        unsigned v : 1;     /* valid bit */
-        unsigned d : 1;     /* dirty/write-protect bit */
-        unsigned c : 3;     /* cache coherency attribute */
-        unsigned pfn : 24;  /* frame number */
-        unsigned : 2;       /* zero */
+        unsigned g : 1;     /* global bit */
+        unsigned v : 1;     /* valid bit */
+        unsigned d : 1;     /* dirty/write-protect bit */
+        unsigned c : 3;     /* cache coherency attribute */
+        unsigned pfn : 24;  /* frame number */
+        unsigned : 2;       /* zero */
 #endif
     } __attribute__ ((packed));
     uint32_t value;
 ,7 → 159,7
     asm volatile ("tlbwr\n\t");
 }
-#define tlb_invalidate(asid)    tlb_invalidate_asid(asid)
+#define tlb_invalidate(asid)  tlb_invalidate_asid(asid)
 extern void tlb_invalid(istate_t *istate);
 extern void tlb_refill(istate_t *istate);

 /branches/network/kernel/arch/mips32/include/cpu.h
 ,7 → 42,7
     uint32_t imp_num;
     uint32_t rev_num;
 } cpu_arch_t;
 #endif
 /** @}

 /branches/network/kernel/arch/mips32/include/drivers/msim.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32
+/** @addtogroup mips32
  * @{
  */
 /** @file
 ,16 → 36,10
 #define KERN_mips32_MSIM_H_
 /** Address of devices. */
-#define MSIM_VIDEORAM       0x90000000
-#define MSIM_KBD_ADDRESS    0x90000000
-#define MSIM_KBD_IRQ        2
+#define MSIM_VIDEORAM     0x90000000
+#define MSIM_KBD_ADDRESS  0x90000000
+#define MSIM_KBD_IRQ      2
-#include <console/chardev.h>
-void msim_console(devno_t devno);
-void msim_kbd_release(void);
-void msim_kbd_grab(void);
 #endif
 /** @}

 /branches/network/kernel/arch/mips32/Makefile.inc
 ,90 → 29,49
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_ARCH = mips
+BFD = binary
 TARGET = mipsel-linux-gnu
 TOOLCHAIN_DIR = $(CROSS_PREFIX)/mipsel
-KERNEL_LOAD_ADDRESS = 0x80100000
-INIT_ADDRESS = 0x81000000
-INIT_SIZE = 262144
+GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3
-GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss
+DEFS += -D__32_BITS__
-DEFS += -D__32_BITS__ -DMACHINE=$(MACHINE) -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS} -DINIT_ADDRESS=${INIT_ADDRESS} -DINIT_SIZE=${INIT_SIZE}
-## Compile with hierarchical page tables support.
-#
-CONFIG_PAGE_PT = y
-DEFS += -DCONFIG_PAGE_PT
-## Compile with support for address space identifiers.
-#
-CONFIG_ASID = y
-CONFIG_ASID_FIFO = y
 ## Accepted MACHINEs
 #
 ifeq ($(MACHINE),lgxemul)
     BFD_NAME = elf32-tradlittlemips
-    BFD = binary
-    GCC_CFLAGS += -DFB_INVERT_ENDIAN -DARCH_HAS_FPU -mips3
 endif
 ifeq ($(MACHINE),bgxemul)
-    BFD_NAME = elf32-bigmips
-    BFD = ecoff-bigmips
-    TARGET = mips-sgi-irix5
-    TOOLCHAIN_DIR = $(CROSS_PREFIX)/mips/bin
-    GCC_CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -mips3
-    INIT_ADDRESS = 0x81800000
+    BFD_NAME = elf32-tradbigmips
+    TOOLCHAIN_DIR = $(CROSS_PREFIX)/mips
+    TARGET = mips-linux-gnu
+    GCC_CFLAGS += -DBIG_ENDIAN
 endif
-ifeq ($(MACHINE),simics)
-    # SIMICS 4kc emulation is broken, although for instructions
-    # that do not bother us
-    BFD_NAME = elf32-tradlittlemips
-    BFD = elf32-tradlittlemips
-    GCC_CFLAGS += -mhard-float -mips3 -DTLBCNT=16
-    TLBCNT = 16
-endif
 ifeq ($(MACHINE),msim)
     BFD_NAME = elf32-tradlittlemips
-    BFD = binary
-    GCC_CFLAGS += -mhard-float -mips3
+    GCC_CFLAGS += -mhard-float
 endif
-## Compile with support for software integer division.
-#
-CONFIG_SOFTINT = y
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/start.S \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/panic.S \
-    arch/$(ARCH)/src/mips32.c \
-    arch/$(ARCH)/src/dummy.S \
-    arch/$(ARCH)/src/console.c \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/exception.c \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/cache.c \
-    arch/$(ARCH)/src/debugger.c \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/fpu_context.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/msim.c \
-    arch/$(ARCH)/src/drivers/serial.c \
-    arch/$(ARCH)/src/smp/order.c
+    arch/$(KARCH)/src/start.S \
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/panic.S \
+    arch/$(KARCH)/src/mips32.c \
+    arch/$(KARCH)/src/console.c \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/exception.c \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/cache.c \
+    arch/$(KARCH)/src/debugger.c \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/fpu_context.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/smp/dorder.c \
+    arch/$(KARCH)/src/smp/smp.c

 /branches/network/kernel/arch/mips32/src/fpu_context.c
 ,7 → 40,7
 void fpu_disable(void)
 {
-#ifdef ARCH_HAS_FPU
+#ifdef CONFIG_FPU
     cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit);
 #endif
 }
 ,7 → 47,7
 void fpu_enable(void)
 {
-#ifdef ARCH_HAS_FPU
+#ifdef CONFIG_FPU
     cp0_status_write(cp0_status_read() | cp0_status_fpu_bit);
 #endif
 }

 /branches/network/kernel/arch/mips32/src/exception.c
 ,13 → 41,12
 #include <arch.h>
 #include <debug.h>
 #include <proc/thread.h>
-#include <symtab.h>
 #include <print.h>
 #include <interrupt.h>
 #include <func.h>
-#include <console/kconsole.h>
 #include <ddi/irq.h>
 #include <arch/debugger.h>
+#include <symtab.h>
 static char * exctable[] = {
     "Interrupt",
 ,25 → 73,21
 static void print_regdump(istate_t *istate)
 {
-    char *pcsymbol = "";
-    char *rasymbol = "";
+    char *pcsymbol, *rasymbol;
-    char *s = get_symtab_entry(istate->epc);
-    if (s)
-        pcsymbol = s;
-    s = get_symtab_entry(istate->ra);
-    if (s)
-        rasymbol = s;
-    printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, istate->ra, rasymbol, istate->sp);
+    pcsymbol = symtab_fmt_name_lookup(istate->epc);
+    rasymbol = symtab_fmt_name_lookup(istate->ra);
+    printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol,
+        istate->ra, rasymbol, istate->sp);
 }
 static void unhandled_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "unhandled exception %s", exctable[n]);
+    fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]);
     print_regdump(istate);
-    panic("unhandled exception %s\n", exctable[n]);
+    panic("Unhandled exception %s.", exctable[n]);
 }
 static void reserved_instr_exception(int n, istate_t *istate)
 ,8 → 128,8
     if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
         scheduler_fpu_lazy_request();
     else {
-        fault_if_from_uspace(istate, "unhandled Coprocessor Unusable Exception");
-        panic("unhandled Coprocessor Unusable Exception\n");
+        fault_if_from_uspace(istate, "Unhandled Coprocessor Unusable Exception.");
+        panic("Unhandled Coprocessor Unusable Exception.");
     }
 }
 #endif
 ,7 → 140,7
     int i;
     /* decode interrupt number and process the interrupt */
-    cause = (cp0_cause_read() >> 8) &0xff;
+    cause = (cp0_cause_read() >> 8) & 0xff;
     for (i = 0; i < 8; i++) {
         if (cause & (1 << i)) {
 ,7 → 149,7
                 /*
                  * The IRQ handler was found.
                  */
-                irq->handler(irq, irq->arg);
+                irq->handler(irq);
                 spinlock_unlock(&irq->lock);
             } else {
                 /*
 ,7 → 156,8
                  * Spurious interrupt.
                  */
 #ifdef CONFIG_DEBUG
-                printf("cpu%u: spurious interrupt (inum=%d)\n", CPU->id, i);
+                printf("cpu%u: spurious interrupt (inum=%d)\n",
+                    CPU->id, i);
 #endif
             }
         }
 ,7 → 167,7
 /** Handle syscall userspace call */
 static void syscall_exception(int n, istate_t *istate)
 {
-    panic("Syscall is handled through shortcut");
+    panic("Syscall is handled through shortcut.");
 }
 void exception_init(void)

 /branches/network/kernel/arch/mips32/src/smp/dorder.c
 ,0 → 1,47
+/*
+ * Copyright (c) 2007 Martin Decky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup mips32
+ * @{
+ */
+/** @file
+ */
+#include <arch/smp/dorder.h>
+#define MSIM_DORDER_ADDRESS  0xB0000004
+void ipi_broadcast_arch(int ipi)
+{
+#ifdef CONFIG_SMP
+    *((volatile unsigned int *) MSIM_DORDER_ADDRESS) = 0x7FFFFFFF;
+#endif
+}
+/** @}
+ */

 /branches/network/kernel/arch/mips32/src/smp/smp.c
 ,0 → 1,53
+/*
+ * Copyright (c) 2009 Martin Decky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup mips32
+ * @{
+ */
+/** @file
+ */
+#include <config.h>
+#include <smp/smp.h>
+#include <arch/arch.h>
+#ifdef CONFIG_SMP
+void smp_init(void)
+{
+    config.cpu_count = cpu_count;
+}
+void kmp(void *arg __attribute__((unused)))
+{
+}
+#endif /* CONFIG_SMP */
+/** @}
+ */

 /branches/network/kernel/arch/mips32/src/asm.S
 ,17 → 27,17
 #
 #include <arch/asm/regname.h>
 .text
 .macro cp0_read reg
-    mfc0 $2,\reg
+    mfc0 $2, \reg
     j $31
     nop
 .endm
 .macro cp0_write reg
-    mtc0 $4,\reg
+    mtc0 $4, \reg
     j $31
     nop
 .endm
 ,6 → 46,11
 .set noreorder
 .set nomacro
+.global asm_delay_loop
+asm_delay_loop:
+    j $31
+    nop
 .global cpu_halt
 cpu_halt:
     j cpu_halt
 ,235 → 71,238
 memcpy:
 memcpy_from_uspace:
 memcpy_to_uspace:
-    addiu   $v0,$a1,3
-    li  $v1,-4          # 0xfffffffffffffffc
-    and $v0,$v0,$v1
-    beq $a1,$v0,3f
-    move    $t0,$a0
-    move    $t2,$a0         # save dst
+    move $t2, $a0      # save dst
+    addiu $v0, $a1, 3
+    li $v1, -4         # 0xfffffffffffffffc
+    and $v0, $v0, $v1
+    beq $a1, $v0, 3f
+    move $t0, $a0
+:
+        beq $a2, $zero, 2f
+        move $a3, $zero
+:
+        addu $v0, $a1, $a3
+        lbu $a0, 0($v0)
+        addu $v1, $t0, $a3
+        addiu $a3, $a3, 1
+        bne $a3, $a2, 1b
+        sb $a0, 0($v1)
+:
+        jr $ra
+        move $v0, $t2
+:
+        addiu $v0, $a0, 3
+        and $v0, $v0, $v1
+        bne $a0, $v0, 0b
+        srl $t1, $a2, 2
+        beq $t1, $zero, 5f
+        move $a3, $zero
+        move $a3, $zero
+        move $a0, $zero
+:
+        addu $v0, $a1, $a0
+        lw $v1, 0($v0)
+        addiu $a3, $a3, 1
+        addu $v0, $t0, $a0
+        sw $v1, 0($v0)
+        bne $a3, $t1, 4b
+        addiu $a0, $a0, 4
+:
+        andi $a2, $a2, 0x3
+        beq $a2, $zero, 2b
+        nop
+        sll $v0, $a3, 2
+        addu $t1, $v0, $t0
+        move $a3, $zero
+        addu $t0, $v0, $a1
+:
+        addu $v0, $t0, $a3
+        lbu $a0, 0($v0)
+        addu $v1, $t1, $a3
+        addiu $a3, $a3, 1
+        bne $a3, $a2, 6b
+        sb $a0, 0($v1)
+        jr $ra
+        move $v0, $t2
-:
-    beq $a2,$zero,2f
-    move    $a3,$zero
-:
-    addu    $v0,$a1,$a3
-    lbu $a0,0($v0)
-    addu    $v1,$t0,$a3
-    addiu   $a3,$a3,1
-    bne $a3,$a2,1b
-    sb  $a0,0($v1)
-:
-    jr  $ra
-    move    $v0,$t2
-:
-    addiu   $v0,$a0,3
-    and $v0,$v0,$v1
-    bne $a0,$v0,0b
-    srl $t1,$a2,2
-    beq $t1,$zero,5f
-    move    $a3,$zero
-    move    $a3,$zero
-    move    $a0,$zero
-:
-    addu    $v0,$a1,$a0
-    lw  $v1,0($v0)
-    addiu   $a3,$a3,1
-    addu    $v0,$t0,$a0
-    sw  $v1,0($v0)
-    bne $a3,$t1,4b
-    addiu   $a0,$a0,4
-:
-    andi    $a2,$a2,0x3
-    beq $a2,$zero,2b
-    nop
-    sll $v0,$a3,2
-    addu    $t1,$v0,$t0
-    move    $a3,$zero
-    addu    $t0,$v0,$a1
-:
-    addu    $v0,$t0,$a3
-    lbu $a0,0($v0)
-    addu    $v1,$t1,$a3
-    addiu   $a3,$a3,1
-    bne $a3,$a2,6b
-    sb  $a0,0($v1)
-    jr  $ra
-    move    $v0,$t2
 memcpy_from_uspace_failover_address:
 memcpy_to_uspace_failover_address:
-    jr  $ra
-    move    $v0, $zero
+    jr $ra
+    move $v0, $zero
 .macro fpu_gp_save reg ctx
-    mfc1 $t0,$\reg
-    sw $t0, \reg*4(\ctx)
+    mfc1 $t0, $\reg
+    sw $t0, \reg * 4(\ctx)
 .endm
 .macro fpu_gp_restore reg ctx
-    lw $t0, \reg*4(\ctx)
-    mtc1 $t0,$\reg
+    lw $t0, \reg * 4(\ctx)
+    mtc1 $t0, $\reg
 .endm
 .macro fpu_ct_save reg ctx
-    cfc1 $t0,$1
-    sw $t0, (\reg+32)*4(\ctx)
+    cfc1 $t0, $1
+    sw $t0, (\reg + 32) * 4(\ctx)
 .endm
 .macro fpu_ct_restore reg ctx
-    lw $t0, (\reg+32)*4(\ctx)
-    ctc1 $t0,$\reg
+    lw $t0, (\reg + 32) * 4(\ctx)
+    ctc1 $t0, $\reg
 .endm
 .global fpu_context_save
 fpu_context_save:
-#ifdef ARCH_HAS_FPU
-    fpu_gp_save 0,$a0
-    fpu_gp_save 1,$a0
-    fpu_gp_save 2,$a0
-    fpu_gp_save 3,$a0
-    fpu_gp_save 4,$a0
-    fpu_gp_save 5,$a0
-    fpu_gp_save 6,$a0
-    fpu_gp_save 7,$a0
-    fpu_gp_save 8,$a0
-    fpu_gp_save 9,$a0
-    fpu_gp_save 10,$a0
-    fpu_gp_save 11,$a0
-    fpu_gp_save 12,$a0
-    fpu_gp_save 13,$a0
-    fpu_gp_save 14,$a0
-    fpu_gp_save 15,$a0
-    fpu_gp_save 16,$a0
-    fpu_gp_save 17,$a0
-    fpu_gp_save 18,$a0
-    fpu_gp_save 19,$a0
-    fpu_gp_save 20,$a0
-    fpu_gp_save 21,$a0
-    fpu_gp_save 22,$a0
-    fpu_gp_save 23,$a0
-    fpu_gp_save 24,$a0
-    fpu_gp_save 25,$a0
-    fpu_gp_save 26,$a0
-    fpu_gp_save 27,$a0
-    fpu_gp_save 28,$a0
-    fpu_gp_save 29,$a0
-    fpu_gp_save 30,$a0
-    fpu_gp_save 31,$a0
-    fpu_ct_save 1,$a0
-    fpu_ct_save 2,$a0
-    fpu_ct_save 3,$a0
-    fpu_ct_save 4,$a0
-    fpu_ct_save 5,$a0
-    fpu_ct_save 6,$a0
-    fpu_ct_save 7,$a0
-    fpu_ct_save 8,$a0
-    fpu_ct_save 9,$a0
-    fpu_ct_save 10,$a0
-    fpu_ct_save 11,$a0
-    fpu_ct_save 12,$a0
-    fpu_ct_save 13,$a0
-    fpu_ct_save 14,$a0
-    fpu_ct_save 15,$a0
-    fpu_ct_save 16,$a0
-    fpu_ct_save 17,$a0
-    fpu_ct_save 18,$a0
-    fpu_ct_save 19,$a0
-    fpu_ct_save 20,$a0
-    fpu_ct_save 21,$a0
-    fpu_ct_save 22,$a0
-    fpu_ct_save 23,$a0
-    fpu_ct_save 24,$a0
-    fpu_ct_save 25,$a0
-    fpu_ct_save 26,$a0
-    fpu_ct_save 27,$a0
-    fpu_ct_save 28,$a0
-    fpu_ct_save 29,$a0
-    fpu_ct_save 30,$a0
-    fpu_ct_save 31,$a0
-#endif
+#ifdef CONFIG_FPU
+    fpu_gp_save 0, $a0
+    fpu_gp_save 1, $a0
+    fpu_gp_save 2, $a0
+    fpu_gp_save 3, $a0
+    fpu_gp_save 4, $a0
+    fpu_gp_save 5, $a0
+    fpu_gp_save 6, $a0
+    fpu_gp_save 7, $a0
+    fpu_gp_save 8, $a0
+    fpu_gp_save 9, $a0
+    fpu_gp_save 10, $a0
+    fpu_gp_save 11, $a0
+    fpu_gp_save 12, $a0
+    fpu_gp_save 13, $a0
+    fpu_gp_save 14, $a0
+    fpu_gp_save 15, $a0
+    fpu_gp_save 16, $a0
+    fpu_gp_save 17, $a0
+    fpu_gp_save 18, $a0
+    fpu_gp_save 19, $a0
+    fpu_gp_save 20, $a0
+    fpu_gp_save 21, $a0
+    fpu_gp_save 22, $a0
+    fpu_gp_save 23, $a0
+    fpu_gp_save 24, $a0
+    fpu_gp_save 25, $a0
+    fpu_gp_save 26, $a0
+    fpu_gp_save 27, $a0
+    fpu_gp_save 28, $a0
+    fpu_gp_save 29, $a0
+    fpu_gp_save 30, $a0
+    fpu_gp_save 31, $a0
+    fpu_ct_save 1, $a0
+    fpu_ct_save 2, $a0
+    fpu_ct_save 3, $a0
+    fpu_ct_save 4, $a0
+    fpu_ct_save 5, $a0
+    fpu_ct_save 6, $a0
+    fpu_ct_save 7, $a0
+    fpu_ct_save 8, $a0
+    fpu_ct_save 9, $a0
+    fpu_ct_save 10, $a0
+    fpu_ct_save 11, $a0
+    fpu_ct_save 12, $a0
+    fpu_ct_save 13, $a0
+    fpu_ct_save 14, $a0
+    fpu_ct_save 15, $a0
+    fpu_ct_save 16, $a0
+    fpu_ct_save 17, $a0
+    fpu_ct_save 18, $a0
+    fpu_ct_save 19, $a0
+    fpu_ct_save 20, $a0
+    fpu_ct_save 21, $a0
+    fpu_ct_save 22, $a0
+    fpu_ct_save 23, $a0
+    fpu_ct_save 24, $a0
+    fpu_ct_save 25, $a0
+    fpu_ct_save 26, $a0
+    fpu_ct_save 27, $a0
+    fpu_ct_save 28, $a0
+    fpu_ct_save 29, $a0
+    fpu_ct_save 30, $a0
+    fpu_ct_save 31, $a0
+#endif
     j $ra
     nop
 .global fpu_context_restore
 fpu_context_restore:
-#ifdef ARCH_HAS_FPU
-    fpu_gp_restore 0,$a0
-    fpu_gp_restore 1,$a0
-    fpu_gp_restore 2,$a0
-    fpu_gp_restore 3,$a0
-    fpu_gp_restore 4,$a0
-    fpu_gp_restore 5,$a0
-    fpu_gp_restore 6,$a0
-    fpu_gp_restore 7,$a0
-    fpu_gp_restore 8,$a0
-    fpu_gp_restore 9,$a0
-    fpu_gp_restore 10,$a0
-    fpu_gp_restore 11,$a0
-    fpu_gp_restore 12,$a0
-    fpu_gp_restore 13,$a0
-    fpu_gp_restore 14,$a0
-    fpu_gp_restore 15,$a0
-    fpu_gp_restore 16,$a0
-    fpu_gp_restore 17,$a0
-    fpu_gp_restore 18,$a0
-    fpu_gp_restore 19,$a0
-    fpu_gp_restore 20,$a0
-    fpu_gp_restore 21,$a0
-    fpu_gp_restore 22,$a0
-    fpu_gp_restore 23,$a0
-    fpu_gp_restore 24,$a0
-    fpu_gp_restore 25,$a0
-    fpu_gp_restore 26,$a0
-    fpu_gp_restore 27,$a0
-    fpu_gp_restore 28,$a0
-    fpu_gp_restore 29,$a0
-    fpu_gp_restore 30,$a0
-    fpu_gp_restore 31,$a0
-    fpu_ct_restore 1,$a0
-    fpu_ct_restore 2,$a0
-    fpu_ct_restore 3,$a0
-    fpu_ct_restore 4,$a0
-    fpu_ct_restore 5,$a0
-    fpu_ct_restore 6,$a0
-    fpu_ct_restore 7,$a0
-    fpu_ct_restore 8,$a0
-    fpu_ct_restore 9,$a0
-    fpu_ct_restore 10,$a0
-    fpu_ct_restore 11,$a0
-    fpu_ct_restore 12,$a0
-    fpu_ct_restore 13,$a0
-    fpu_ct_restore 14,$a0
-    fpu_ct_restore 15,$a0
-    fpu_ct_restore 16,$a0
-    fpu_ct_restore 17,$a0
-    fpu_ct_restore 18,$a0
-    fpu_ct_restore 19,$a0
-    fpu_ct_restore 20,$a0
-    fpu_ct_restore 21,$a0
-    fpu_ct_restore 22,$a0
-    fpu_ct_restore 23,$a0
-    fpu_ct_restore 24,$a0
-    fpu_ct_restore 25,$a0
-    fpu_ct_restore 26,$a0
-    fpu_ct_restore 27,$a0
-    fpu_ct_restore 28,$a0
-    fpu_ct_restore 29,$a0
-    fpu_ct_restore 30,$a0
-    fpu_ct_restore 31,$a0
-#endif
+#ifdef CONFIG_FPU
+    fpu_gp_restore 0, $a0
+    fpu_gp_restore 1, $a0
+    fpu_gp_restore 2, $a0
+    fpu_gp_restore 3, $a0
+    fpu_gp_restore 4, $a0
+    fpu_gp_restore 5, $a0
+    fpu_gp_restore 6, $a0
+    fpu_gp_restore 7, $a0
+    fpu_gp_restore 8, $a0
+    fpu_gp_restore 9, $a0
+    fpu_gp_restore 10, $a0
+    fpu_gp_restore 11, $a0
+    fpu_gp_restore 12, $a0
+    fpu_gp_restore 13, $a0
+    fpu_gp_restore 14, $a0
+    fpu_gp_restore 15, $a0
+    fpu_gp_restore 16, $a0
+    fpu_gp_restore 17, $a0
+    fpu_gp_restore 18, $a0
+    fpu_gp_restore 19, $a0
+    fpu_gp_restore 20, $a0
+    fpu_gp_restore 21, $a0
+    fpu_gp_restore 22, $a0
+    fpu_gp_restore 23, $a0
+    fpu_gp_restore 24, $a0
+    fpu_gp_restore 25, $a0
+    fpu_gp_restore 26, $a0
+    fpu_gp_restore 27, $a0
+    fpu_gp_restore 28, $a0
+    fpu_gp_restore 29, $a0
+    fpu_gp_restore 30, $a0
+    fpu_gp_restore 31, $a0
+    fpu_ct_restore 1, $a0
+    fpu_ct_restore 2, $a0
+    fpu_ct_restore 3, $a0
+    fpu_ct_restore 4, $a0
+    fpu_ct_restore 5, $a0
+    fpu_ct_restore 6, $a0
+    fpu_ct_restore 7, $a0
+    fpu_ct_restore 8, $a0
+    fpu_ct_restore 9, $a0
+    fpu_ct_restore 10, $a0
+    fpu_ct_restore 11, $a0
+    fpu_ct_restore 12, $a0
+    fpu_ct_restore 13, $a0
+    fpu_ct_restore 14, $a0
+    fpu_ct_restore 15, $a0
+    fpu_ct_restore 16, $a0
+    fpu_ct_restore 17, $a0
+    fpu_ct_restore 18, $a0
+    fpu_ct_restore 19, $a0
+    fpu_ct_restore 20, $a0
+    fpu_ct_restore 21, $a0
+    fpu_ct_restore 22, $a0
+    fpu_ct_restore 23, $a0
+    fpu_ct_restore 24, $a0
+    fpu_ct_restore 25, $a0
+    fpu_ct_restore 26, $a0
+    fpu_ct_restore 27, $a0
+    fpu_ct_restore 28, $a0
+    fpu_ct_restore 29, $a0
+    fpu_ct_restore 30, $a0
+    fpu_ct_restore 31, $a0
+#endif
     j $ra
     nop

 /branches/network/kernel/arch/mips32/src/console.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32
+/** @addtogroup mips32
  * @{
  */
 /** @file
 ,24 → 33,16
  */
 #include <console/console.h>
-#include <arch/console.h>
-#include <arch/drivers/serial.h>
-#include <arch/drivers/msim.h>
+#include <genarch/fb/fb.h>
-void console_init(devno_t devno)
-{
-    if (serial_init())
-        serial_console(devno);
-    else
-        msim_console(devno);
-}
 /** Acquire console back for kernel
  *
  */
 void arch_grab_console(void)
 {
-    msim_kbd_grab();
+#ifdef CONFIG_FB
+    fb_redraw();
+#endif
 }
 /** Return console to userspace
 ,7 → 50,6
  */
 void arch_release_console(void)
 {
-    msim_kbd_release();
 }
 /** @}

 /branches/network/kernel/arch/mips32/src/cache.c
 ,7 → 38,7
 void cache_error(istate_t *istate)
 {
-    panic("cache_error exception (epc=%p)\n", istate->epc);
+    panic("cache_error exception (epc=%p).", istate->epc);
 }
 /** @}

 /branches/network/kernel/arch/mips32/src/debugger.c
 ,16 → 37,18
 #include <memstr.h>
 #include <console/kconsole.h>
 #include <console/cmd.h>
-#include <symtab.h>
 #include <print.h>
 #include <panic.h>
 #include <arch.h>
 #include <arch/cp0.h>
 #include <func.h>
+#include <symtab.h>
 bpinfo_t breakpoints[BKPOINTS_MAX];
 SPINLOCK_INITIALIZE(bkpoint_lock);
+#ifdef CONFIG_KCONSOLE
 static int cmd_print_breakpoints(cmd_arg_t *argv);
 static cmd_info_t bkpts_info = {
     .name = "bkpts",
 ,10 → 125,12
     {0, 0} /* EndOfTable */
 };
 /** Test, if the given instruction is a jump or branch instruction
  *
  * @param instr Instruction code
  * @return true - it is jump instruction, false otherwise
+ *
  */
 static bool is_jump(unative_t instr)
 {
 ,7 → 162,7
     for (i = 0; i < BKPOINTS_MAX; i++) {
         if (breakpoints[i].address == (uintptr_t)argv->intval) {
             printf("Duplicate breakpoint %d.\n", i);
-            spinlock_unlock(&bkpoints_lock);
+            spinlock_unlock(&bkpoint_lock);
             return 0;
         } else if (breakpoints[i].address == (uintptr_t)argv->intval +
             sizeof(unative_t) || breakpoints[i].address ==
 ,10 → 169,10
             (uintptr_t)argv->intval - sizeof(unative_t)) {
             printf("Adjacent breakpoints not supported, conflict "
                 "with %d.\n", i);
-            spinlock_unlock(&bkpoints_lock);
+            spinlock_unlock(&bkpoint_lock);
             return 0;
         }
     }
     for (i = 0; i < BKPOINTS_MAX; i++)
 ,8 → 259,9
     for (i = 0; i < BKPOINTS_MAX; i++)
         if (breakpoints[i].address) {
-            symbol = get_symtab_entry(breakpoints[i].address);
+            symbol = symtab_fmt_name_lookup(
+                breakpoints[i].address);
             printf("%-2u %-5d %#10zx %-6s %-7s %-8s %s\n", i,
                 breakpoints[i].counter, breakpoints[i].address,
                 ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" :
 ,6 → 272,8
     return 1;
 }
+#endif
 /** Initialize debugger */
 void debugger_init()
 {
 ,22 → 281,24
     for (i = 0; i < BKPOINTS_MAX; i++)
         breakpoints[i].address = NULL;
+#ifdef CONFIG_KCONSOLE
     cmd_initialize(&bkpts_info);
     if (!cmd_register(&bkpts_info))
-        panic("could not register command %s\n", bkpts_info.name);
+        printf("Cannot register command %s\n", bkpts_info.name);
     cmd_initialize(&delbkpt_info);
     if (!cmd_register(&delbkpt_info))
-        panic("could not register command %s\n", delbkpt_info.name);
+        printf("Cannot register command %s\n", delbkpt_info.name);
     cmd_initialize(&addbkpt_info);
     if (!cmd_register(&addbkpt_info))
-        panic("could not register command %s\n", addbkpt_info.name);
+        printf("Cannot register command %s\n", addbkpt_info.name);
     cmd_initialize(&addbkpte_info);
     if (!cmd_register(&addbkpte_info))
-        panic("could not register command %s\n", addbkpte_info.name);
+        printf("Cannot register command %s\n", addbkpte_info.name);
+#endif
 }
 /** Handle breakpoint
 ,7 → 317,7
     /* test branch delay slot */
     if (cp0_cause_read() & 0x80000000)
-        panic("Breakpoint in branch delay slot not supported.\n");
+        panic("Breakpoint in branch delay slot not supported.");
     spinlock_lock(&bkpoint_lock);
     for (i = 0; i < BKPOINTS_MAX; i++) {
 ,9 → 349,10
         if (cur->flags & BKPOINT_INPROG)
             printf("Warning: breakpoint recursion\n");
-        if (!(cur->flags & BKPOINT_FUNCCALL))
+        if (!(cur->flags & BKPOINT_FUNCCALL)) {
             printf("***Breakpoint %d: %p in %s.\n", i, fireaddr,
-                get_symtab_entry(istate->epc));
+                symtab_fmt_name_lookup(istate->epc));
+        }
         /* Return first instruction back */
         ((uint32_t *)cur->address)[0] = cur->instruction;
 ,8 → 365,9
         }
         cur->flags |= BKPOINT_INPROG;
     } else {
-        printf("***Breakpoint %p in %s.\n", fireaddr,
-               get_symtab_entry(fireaddr));
+        printf("***Breakpoint %d: %p in %s.\n", i, fireaddr,
+            symtab_fmt_name_lookup(fireaddr));
         /* Move on to next instruction */
         istate->epc += 4;
     }
 ,19 → 378,20
         if (cur->bkfunc)
             cur->bkfunc(cur, istate);
     } else {
-        printf("***Type 'exit' to exit kconsole.\n");
+#ifdef CONFIG_KCONSOLE
         /* This disables all other processors - we are not SMP,
          * actually this gets us to cpu_halt, if scheduler() is run
          * - we generally do not want scheduler to be run from debug,
          *   so this is a good idea
          */
-        atomic_set(&haltstate,1);
+        atomic_set(&haltstate, 1);
         spinlock_unlock(&bkpoint_lock);
-        kconsole("debug");
+        kconsole("debug", "Debug console ready.\n", false);
         spinlock_lock(&bkpoint_lock);
-        atomic_set(&haltstate,0);
+        atomic_set(&haltstate, 0);
+#endif
     }
     if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) {
         /* Remove one-shot breakpoint */

 /branches/network/kernel/arch/mips32/src/cpu/cpu.c
 ,7 → 48,7
     { "MIPS", "R2000" },        /* 0x01 */
     { "MIPS", "R3000" },        /* 0x02 */
     { "MIPS", "R6000" },        /* 0x03 */
-    { "MIPS", " R4000/R4400" },     /* 0x04 */
+    { "MIPS", "R4000/R4400" },  /* 0x04 */
     { "LSI Logic", "R3000" },   /* 0x05 */
     { "MIPS", "R6000A" },       /* 0x06 */
     { "IDT", "3051/3052" },     /* 0x07 */
 ,9 → 123,9
         data = &imp_data[m->arch.imp_num];
     }
-    printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n",
+    printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
         m->id, data->vendor, data->model, m->arch.rev_num >> 4,
-        m->arch.rev_num & 0xf, m->arch.imp_num);
+        m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
 /** @}

 /branches/network/kernel/arch/mips32/src/mm/tlb.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm
  * @{
  */
 /** @file
 ,22 → 40,21
 #include <arch/cp0.h>
 #include <panic.h>
 #include <arch.h>
-#include <symtab.h>
-#include <synch/spinlock.h>
+#include <synch/mutex.h>
 #include <print.h>
 #include <debug.h>
 #include <align.h>
 #include <interrupt.h>
+#include <symtab.h>
-static void tlb_refill_fail(istate_t *istate);
-static void tlb_invalid_fail(istate_t *istate);
-static void tlb_modified_fail(istate_t *istate);
+static void tlb_refill_fail(istate_t *);
+static void tlb_invalid_fail(istate_t *);
+static void tlb_modified_fail(istate_t *);
-static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
+static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
-/** Initialize TLB
+/** Initialize TLB.
  *
- * Initialize TLB.
  * Invalidate all entries and mark wired entries.
  */
 void tlb_arch_init(void)
 ,11 → 80,9
     cp0_wired_write(TLB_WIRED);
 }
-/** Process TLB Refill Exception
+/** Process TLB Refill Exception.
  *
- * Process TLB Refill Exception.
- *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_refill(istate_t *istate)
 {
 ,15 → 92,15
     uintptr_t badvaddr;
     pte_t *pte;
     int pfrc;
     badvaddr = cp0_badvaddr_read();
-    spinlock_lock(&AS->lock);
+    mutex_lock(&AS->lock);
     asid = AS->asid;
-    spinlock_unlock(&AS->lock);
+    mutex_unlock(&AS->lock);
     page_table_lock(AS, true);
     pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
     if (!pte) {
         switch (pfrc) {
 ,7 → 115,7
             page_table_unlock(AS, true);
             return;
         default:
-            panic("unexpected pfrc (%d)\n", pfrc);
+            panic("Unexpected pfrc (%d).", pfrc);
         }
     }
 ,13 → 125,14
     pte->a = 1;
     tlb_prepare_entry_hi(&hi, asid, badvaddr);
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+        pte->pfn);
     /*
      * New entry is to be inserted into TLB
      */
     cp0_entry_hi_write(hi.value);
-    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
+    if ((badvaddr / PAGE_SIZE) % 2 == 0) {
         cp0_entry_lo0_write(lo.value);
         cp0_entry_lo1_write(0);
     }
 ,11 → 151,9
     tlb_refill_fail(istate);
 }
-/** Process TLB Invalid Exception
+/** Process TLB Invalid Exception.
  *
- * Process TLB Invalid Exception.
- *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_invalid(istate_t *istate)
 {
 ,7 → 199,7
             page_table_unlock(AS, true);
             return;
         default:
-            panic("unexpected pfrc (%d)\n", pfrc);
+            panic("Unexpected pfrc (%d).", pfrc);
         }
     }
 ,12 → 213,13
      */
     pte->a = 1;
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+        pte->pfn);
     /*
      * The entry is to be updated in TLB.
      */
-    if ((badvaddr/PAGE_SIZE) % 2 == 0)
+    if ((badvaddr / PAGE_SIZE) % 2 == 0)
         cp0_entry_lo0_write(lo.value);
     else
         cp0_entry_lo1_write(lo.value);
 ,11 → 234,9
     tlb_invalid_fail(istate);
 }
-/** Process TLB Modified Exception
+/** Process TLB Modified Exception.
  *
- * Process TLB Modified Exception.
- *
- * @param istate Interrupted register context.
+ * @param istate    Interrupted register context.
  */
 void tlb_modified(istate_t *istate)
 {
 ,17 → 282,11
             page_table_unlock(AS, true);
             return;
         default:
-            panic("unexpected pfrc (%d)\n", pfrc);
+            panic("Unexpected pfrc (%d).", pfrc);
         }
     }
     /*
-     * Fail if the page is not writable.
-     */
-    if (!pte->w)
-        goto fail;
-    /*
      * Read the faulting TLB entry.
      */
     tlbr();
 ,12 → 297,13
     pte->a = 1;
     pte->d = 1;
-    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
+    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
+        pte->pfn);
     /*
      * The entry is to be updated in TLB.
      */
-    if ((badvaddr/PAGE_SIZE) % 2 == 0)
+    if ((badvaddr / PAGE_SIZE) % 2 == 0)
         cp0_entry_lo0_write(lo.value);
     else
         cp0_entry_lo1_write(lo.value);
 ,56 → 320,57
 void tlb_refill_fail(istate_t *istate)
 {
-    char *symbol = "";
-    char *sym2 = "";
+    char *symbol, *sym2;
-    char *s = get_symtab_entry(istate->epc);
-    if (s)
-        symbol = s;
-    s = get_symtab_entry(istate->ra);
-    if (s)
-        sym2 = s;
-    fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
-    panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
+    symbol = symtab_fmt_name_lookup(istate->epc);
+    sym2 = symtab_fmt_name_lookup(istate->ra);
+    fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
+        cp0_badvaddr_read());
+    panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(),
+        istate->epc, symbol, sym2);
 }
 void tlb_invalid_fail(istate_t *istate)
 {
-    char *symbol = "";
+    char *symbol;
-    char *s = get_symtab_entry(istate->epc);
-    if (s)
-        symbol = s;
-    fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
-    panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
+    symbol = symtab_fmt_name_lookup(istate->epc);
+    fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
+        cp0_badvaddr_read());
+    panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(),
+        istate->epc, symbol);
 }
 void tlb_modified_fail(istate_t *istate)
 {
-    char *symbol = "";
+    char *symbol;
-    char *s = get_symtab_entry(istate->epc);
-    if (s)
-        symbol = s;
-    fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
-    panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
+    symbol = symtab_fmt_name_lookup(istate->epc);
+    fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
+        cp0_badvaddr_read());
+    panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(),
+        istate->epc, symbol);
 }
-/** Try to find PTE for faulting address
+/** Try to find PTE for faulting address.
  *
- * Try to find PTE for faulting address.
  * The AS->lock must be held on entry to this function.
  *
- * @param badvaddr Faulting virtual address.
- * @param access Access mode that caused the fault.
- * @param istate Pointer to interrupted state.
- * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
+ * @param badvaddr  Faulting virtual address.
+ * @param access    Access mode that caused the fault.
+ * @param istate    Pointer to interrupted state.
+ * @param pfrc      Pointer to variable where as_page_fault() return code
+ *          will be stored.
  *
- * @return PTE on success, NULL otherwise.
+ * @return      PTE on success, NULL otherwise.
  */
-pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
+pte_t *
+find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
+    int *pfrc)
 {
     entry_hi_t hi;
     pte_t *pte;
 ,7 → 389,7
      * Check if the mapping exists in page tables.
      */
     pte = page_mapping_find(AS, badvaddr);
-    if (pte && pte->p) {
+    if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
         /*
          * Mapping found in page tables.
          * Immediately succeed.
 ,6 → 412,7
             page_table_lock(AS, true);
             pte = page_mapping_find(AS, badvaddr);
             ASSERT(pte && pte->p);
+            ASSERT(pte->w || access != PF_ACCESS_WRITE);
             return pte;
             break;
         case AS_PF_DEFER:
 ,18 → 422,19
             break;
         case AS_PF_FAULT:
             page_table_lock(AS, true);
-            printf("Page fault.\n");
             *pfrc = AS_PF_FAULT;
             return NULL;
             break;
         default:
-            panic("unexpected rc (%d)\n", rc);
+            panic("Unexpected rc (%d).", rc);
         }
     }
 }
-void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
+void
+tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
+    uintptr_t pfn)
 {
     lo->value = 0;
     lo->g = g;
 ,10 → 473,10
         lo1.value = cp0_entry_lo1_read();
         printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
-            i, hi.asid, hi.vpn2, mask.mask,
-            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
+            i, hi.asid, hi.vpn2, mask.mask,
+            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
         printf("                    %1u %1u %1u %1u %#6x\n",
-            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
+            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
     }
     cp0_entry_hi_write(hi_save.value);
 ,11 → 553,12
     cp0_entry_hi_write(hi_save.value);
 }
-/** Invalidate TLB entries for specified page range belonging to specified address space.
+/** Invalidate TLB entries for specified page range belonging to specified
+ * address space.
  *
- * @param asid Address space identifier.
- * @param page First page whose TLB entry is to be invalidated.
- * @param cnt Number of entries to invalidate.
+ * @param asid      Address space identifier.
+ * @param page      First page whose TLB entry is to be invalidated.
+ * @param cnt       Number of entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
 {
 ,7 → 582,10
         index.value = cp0_index_read();
         if (!index.p) {
-            /* Entry was found, index register contains valid index. */
+            /*
+             * Entry was found, index register contains valid
+             * index.
+             */
             tlbr();
             lo0.value = cp0_entry_lo0_read();

 /branches/network/kernel/arch/mips32/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm
  * @{
  */
 /** @file
 ,22 → 40,22
 #include <mm/asid.h>
 #include <config.h>
 #include <arch/drivers/msim.h>
-#include <arch/drivers/serial.h>
 #include <print.h>
-#define ZERO_PAGE_MASK      TLB_PAGE_MASK_256K
-#define ZERO_FRAMES         2048
-#define ZERO_PAGE_WIDTH     18  /* 256K */
-#define ZERO_PAGE_SIZE      (1 << ZERO_PAGE_WIDTH)
-#define ZERO_PAGE_ASID      ASID_INVALID
-#define ZERO_PAGE_TLBI      0
-#define ZERO_PAGE_ADDR      0
-#define ZERO_PAGE_OFFSET    (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1)
-#define ZERO_PAGE_VALUE     (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET])
+#define ZERO_PAGE_MASK    TLB_PAGE_MASK_256K
+#define ZERO_FRAMES       2048
+#define ZERO_PAGE_WIDTH   18  /* 256K */
+#define ZERO_PAGE_SIZE    (1 << ZERO_PAGE_WIDTH)
+#define ZERO_PAGE_ASID    ASID_INVALID
+#define ZERO_PAGE_TLBI    0
+#define ZERO_PAGE_ADDR    0
+#define ZERO_PAGE_OFFSET  (ZERO_PAGE_SIZE / sizeof(uint32_t) - 1)
+#define ZERO_PAGE_VALUE   (((volatile uint32_t *) ZERO_PAGE_ADDR)[ZERO_PAGE_OFFSET])
-#define ZERO_PAGE_VALUE_KSEG1(frame) (((volatile uint32_t *) (0xa0000000 + (frame << ZERO_PAGE_WIDTH)))[ZERO_PAGE_OFFSET])
+#define ZERO_PAGE_VALUE_KSEG1(frame) \
+    (((volatile uint32_t *) (0xa0000000 + (frame << ZERO_PAGE_WIDTH)))[ZERO_PAGE_OFFSET])
-#define MAX_REGIONS         32
+#define MAX_REGIONS  32
 typedef struct {
     pfn_t start;
 ,7 → 65,6
 static count_t phys_regions_count = 0;
 static phys_region_t phys_regions[MAX_REGIONS];
 /** Check whether frame is available
  *
  * Returns true if given frame is generally available for use.
 ,7 → 74,7
  */
 static bool frame_available(pfn_t frame)
 {
-#if MACHINE == msim
+#ifdef MACHINE_msim
     /* MSIM device (dprinter) */
     if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH))
         return false;
 ,14 → 83,8
     if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH))
         return false;
 #endif
-#if MACHINE == simics
-    /* Simics device (serial line) */
-    if (frame == (KA2PA(SERIAL_ADDRESS) >> ZERO_PAGE_WIDTH))
-        return false;
-#endif
-#if (MACHINE == lgxemul) || (MACHINE == bgxemul)
+#if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
     /* gxemul devices */
     if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
 x10000000, MB2SIZE(256)))
 ,7 → 211,7
                     ZERO_PAGE_VALUE = 0xdeadbeef;
                     if (ZERO_PAGE_VALUE != 0xdeadbeef)
                         avail = false;
-#if (MACHINE == lgxemul) || (MACHINE == bgxemul)
+#if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
                     else {
                         ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd;
                         if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd)

 /branches/network/kernel/arch/mips32/src/mm/page.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup mips32mm
+/** @addtogroup mips32mm
  * @{
  */
 /** @file
 ,6 → 35,7
 #include <arch/mm/page.h>
 #include <genarch/mm/page_pt.h>
 #include <mm/page.h>
+#include <mm/frame.h>
 void page_arch_init(void)
 {

 /branches/network/kernel/arch/mips32/src/interrupt.c
 ,8 → 41,9
 #include <ipc/sysipc.h>
 #include <ddi/device.h>
-#define IRQ_COUNT 8
-#define TIMER_IRQ 7
+#define IRQ_COUNT   8
+#define TIMER_IRQ   7
+#define DORDER_IRQ  5
 function virtual_timer_fnc = NULL;
 static irq_t timer_irq;
 ,12 → 101,12
     cp0_compare_write(nextcount);
 }
-static irq_ownership_t timer_claim(void)
+static irq_ownership_t timer_claim(irq_t *irq)
 {
     return IRQ_ACCEPT;
 }
-static void timer_irq_handler(irq_t *irq, void *arg, ...)
+static void timer_irq_handler(irq_t *irq)
 {
     unsigned long drift;

 /branches/network/kernel/arch/mips32/src/mips32.c
 ,7 → 33,6
  */
 #include <arch.h>
-#include <arch/boot.h>
 #include <arch/cp0.h>
 #include <arch/exception.h>
 #include <mm/as.h>
 ,39 → 52,52
 #include <arch/debugger.h>
 #include <genarch/fb/fb.h>
 #include <genarch/fb/visuals.h>
+#include <genarch/drivers/dsrln/dsrlnin.h>
+#include <genarch/drivers/dsrln/dsrlnout.h>
+#include <genarch/srln/srln.h>
 #include <macros.h>
-#include <ddi/device.h>
+#include <config.h>
+#include <string.h>
+#include <arch/drivers/msim.h>
 #include <arch/asm/regname.h>
-/* Size of the code jumping to the exception handler code
- * - J+NOP
+/* Size of the code jumping to the exception handler code
+ * - J+NOP
  */
-#define EXCEPTION_JUMP_SIZE    8
+#define EXCEPTION_JUMP_SIZE  8
-#define TLB_EXC ((char *) 0x80000000)
-#define NORM_EXC ((char *) 0x80000180)
-#define CACHE_EXC ((char *) 0x80000100)
+#define TLB_EXC    ((char *) 0x80000000)
+#define NORM_EXC   ((char *) 0x80000180)
+#define CACHE_EXC  ((char *) 0x80000100)
 /* Why the linker moves the variable 64K away in assembler
- * when not in .text section ????????
+ * when not in .text section?
  */
+/* Stack pointer saved when entering user mode */
 uintptr_t supervisor_sp __attribute__ ((section (".text")));
-/* Stack pointer saved when entering user mode */
-/* TODO: How do we do it on SMP system???? */
-bootinfo_t bootinfo __attribute__ ((section (".text")));
-void arch_pre_main(void)
+count_t cpu_count = 0;
+/** Performs mips32-specific initialization before main_bsp() is called. */
+void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
 {
     /* Setup usermode */
-    init.cnt = bootinfo.cnt;
+    init.cnt = bootinfo->cnt;
-    uint32_t i;
+    count_t i;
+    for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); i++) {
+        init.tasks[i].addr = bootinfo->tasks[i].addr;
+        init.tasks[i].size = bootinfo->tasks[i].size;
+        strncpy(init.tasks[i].name, bootinfo->tasks[i].name,
+            CONFIG_TASK_NAME_BUFLEN);
+    }
-    for (i = 0; i < bootinfo.cnt; i++) {
-        init.tasks[i].addr = bootinfo.tasks[i].addr;
-        init.tasks[i].size = bootinfo.tasks[i].size;
+    for (i = 0; i < CPUMAP_MAX_RECORDS; i++) {
+        if ((bootinfo->cpumap & (1 << i)) != 0)
+            cpu_count++;
     }
 }
 ,12 → 123,12
      */
     cp0_status_write(cp0_status_read() &
         ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
-    /*
-     * Mask all interrupts
+    /*
+     * Mask all interrupts
      */
     cp0_mask_all_int();
     debugger_init();
 }
 ,12 → 135,23
 void arch_post_mm_init(void)
 {
     interrupt_init();
-    console_init(device_assign_devno());
 #ifdef CONFIG_FB
     /* GXemul framebuffer */
-    fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);
-#endif
-    sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1);
+    fb_properties_t gxemul_prop = {
+        .addr = 0x12000000,
+        .offset = 0,
+        .x = 640,
+        .y = 480,
+        .scan = 1920,
+        .visual = VISUAL_BGR_8_8_8,
+    };
+    fb_init(&gxemul_prop);
+#else
+#ifdef CONFIG_MIPS_PRN
+    dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
+#endif /* CONFIG_MIPS_PRN */
+#endif /* CONFIG_FB */
 }
 void arch_post_cpu_init(void)
 ,8 → 164,31
 void arch_post_smp_init(void)
 {
+#ifdef CONFIG_MIPS_KBD
+    /*
+     * Initialize the msim/GXemul keyboard port. Then initialize the serial line
+     * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
+     */
+    indev_t *kbrdin = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
+    if (kbrdin) {
+        srln_init(kbrdin);
+        cp0_unmask_int(MSIM_KBD_IRQ);
+    }
+    /*
+     * This is the necessary evil until the userspace driver is entirely
+     * self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);
+    sysinfo_set_item_val("kbd.address.virtual", NULL, MSIM_KBD_ADDRESS);
+#endif
 }
+void calibrate_delay_loop(void)
+{
+}
 void userspace(uspace_arg_t *kernel_uarg)
 {
     /* EXL = 1, UM = 1, IE = 1 */
 ,8 → 199,7
         (uintptr_t) kernel_uarg->uspace_uarg,
         (uintptr_t) kernel_uarg->uspace_entry);
-    while (1)
-        ;
+    while (1);
 }
 /** Perform mips32 specific tasks needed before the new task is run. */
 ,10 → 231,22
 void arch_reboot(void)
 {
     ___halt();
-    while (1)
-        ;
+    while (1);
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/mips32/src/start.S
 ,7 → 31,7
 #include <arch/asm/boot.h>
 #include <arch/context_offset.h>
 #include <arch/stack.h>
 .text
 .set noat
 ,18 → 75,6
     mfhi $at
     sw $at, EOFFSET_HI(\r)
-#ifdef CONFIG_DEBUG_ALLREGS
-    sw $s0, EOFFSET_S0(\r)
-    sw $s1, EOFFSET_S1(\r)
-    sw $s2, EOFFSET_S2(\r)
-    sw $s3, EOFFSET_S3(\r)
-    sw $s4, EOFFSET_S4(\r)
-    sw $s5, EOFFSET_S5(\r)
-    sw $s6, EOFFSET_S6(\r)
-    sw $s7, EOFFSET_S7(\r)
-    sw $s8, EOFFSET_S8(\r)
-#endif
     sw $gp, EOFFSET_GP(\r)
     sw $ra, EOFFSET_RA(\r)
     sw $k1, EOFFSET_K1(\r)
 ,17 → 120,6
     lw $t8, EOFFSET_T8(\r)
     lw $t9, EOFFSET_T9(\r)
-#ifdef CONFIG_DEBUG_ALLREGS
-    lw $s0, EOFFSET_S0(\r)
-    lw $s1, EOFFSET_S1(\r)
-    lw $s2, EOFFSET_S2(\r)
-    lw $s3, EOFFSET_S3(\r)
-    lw $s4, EOFFSET_S4(\r)
-    lw $s5, EOFFSET_S5(\r)
-    lw $s6, EOFFSET_S6(\r)
-    lw $s7, EOFFSET_S7(\r)
-    lw $s8, EOFFSET_S8(\r)
-#endif
     lw $gp, EOFFSET_GP(\r)
     lw $ra, EOFFSET_RA(\r)
     lw $k1, EOFFSET_K1(\r)
 ,9 → 152,9
     ori $k0, $k0, %lo(supervisor_sp)
     # Move $k0 (superveisor_sp)
     lw $k0, 0($k0)
-:
+:
 .endm
 .org 0x0
 kernel_image_start:
     /* Load temporary stack */
 ,31 → 161,12
     lui $sp, %hi(end_stack)
     ori $sp, $sp, %lo(end_stack)
-    /* $a1 contains physical address of bootinfo_t */
-    /* $a2 contains size of bootinfo_t */
-    beq $a2, $0, bootinfo_end
-    /* Not sure about this, but might be needed for PIC code???? */
+    /* Not sure about this, but might
+       be needed for PIC code */
     lui $gp, 0x8000
-    lui $a3, %hi(bootinfo)
-    ori $a3, $a3, %lo(bootinfo)
+    /* $a1 contains physical address of bootinfo_t */
-    bootinfo_loop:
-        lw $v0, 0($a1)
-        sw $v0, 0($a3)
-        addi $a1, $a1, 4
-        addi $a3, $a3, 4
-        addi $a2, $a2, -4
-        bgtz $a2, bootinfo_loop
-        nop
-    bootinfo_end:
     jal arch_pre_main
     nop
 ,8 → 186,8
 exception_entry:
     j exception_handler
-    nop
+    nop
 exception_handler:
     KERNEL_STACK_TO_K0
     sub $k0, REGISTER_SPACE
 ,17 → 196,17
     mfc0 $k0, $cause
-    sra $k0, $k0, 0x2       # cp0_exc_cause() part 1
-    andi $k0, $k0, 0x1f     # cp0_exc_cause() part 2
-    sub $k0, 8          # 8 = SYSCALL
+    sra $k0, $k0, 0x2    # cp0_exc_cause() part 1
+    andi $k0, $k0, 0x1f  # cp0_exc_cause() part 2
+    sub $k0, 8           # 8 = SYSCALL
     beqz $k0, syscall_shortcut
-    add $k0, 8          # Revert $k0 back to correct exc number
+    add $k0, 8           # Revert $k0 back to correct exc number
     REGISTERS_STORE_AND_EXC_RESET $sp
     move $a1, $sp
-    jal exc_dispatch        # exc_dispatch(excno, register_space)
+    jal exc_dispatch     # exc_dispatch(excno, register_space)
     move $a0, $k0
     REGISTERS_LOAD $sp

 /branches/network/kernel/arch/ia32/_link.ld.in
 ,11 → 1,11
 /** IA-32 linker script
- *
+ *
  * umapped section:
- *  kernel text
- *  kernel data
+ *  kernel text
+ *  kernel data
  * mapped section:
- *  kernel text
- *  kernel data
+ *  kernel text
+ *  kernel data
  */
 #include <arch/boot/boot.h>
 ,9 → 28,9
         ktext_end = .;
         kdata_start = .;
-        *(.data);           /* initialized data */
-        *(.rodata*);            /* string literals */
-        *(COMMON);          /* global variables */
+        *(.data);               /* initialized data */
+        *(.rodata*);            /* string literals */
+        *(COMMON);              /* global variables */
         hardcoded_load_address = .;
         LONG(PA2KA(BOOT_OFFSET));
         hardcoded_ktext_size = .;
 ,23 → 42,23
         hardcoded_unmapped_kdata_size = .;
         LONG(unmapped_kdata_end - unmapped_kdata_start);
         symbol_table = .;
-        *(symtab.*);                /* Symbol table, must be LAST symbol! */
-        *(.bss);            /* uninitialized static variables */
+        *(symtab.*);            /* Symbol table, must be LAST symbol! */
+        *(.bss);                /* uninitialized static variables */
         kdata_end = .;
     }
     /DISCARD/ : {
-        *(.note.GNU-stack);
+        *(.note.GNU-stack);
         *(.comment);
     }
-#ifdef CONFIG_SMP
+#ifdef CONFIG_SMP
     _hardcoded_unmapped_size = (unmapped_ktext_end - unmapped_ktext_start) + (unmapped_kdata_end - unmapped_kdata_start);
     ap_boot = unmapped_ap_boot - BOOT_OFFSET + AP_BOOT_OFFSET;
     ap_gdtr = unmapped_ap_gdtr - BOOT_OFFSET + AP_BOOT_OFFSET;
     protected_ap_gdtr = PA2KA(ap_gdtr);
 #endif /* CONFIG_SMP */
 }

 /branches/network/kernel/arch/ia32/include/interrupt.h
 ,10 → 72,6
     uint32_t eax;
     uint32_t ecx;
     uint32_t edx;
-    uint32_t esi;
-    uint32_t edi;
-    uint32_t ebp;
-    uint32_t ebx;
     uint32_t gs;
     uint32_t fs;

/branches/network/kernel/arch/ia32/include/fpu_context.h
37,7 → 37,6

#include <arch/types.h>

#define ARCH_HAS_FPU
#define FPU_CONTEXT_ALIGN 16

void fpu_fxsr(void);

 /branches/network/kernel/arch/ia32/include/cpuid.h
 ,21 → 74,21
     uint32_t val, ret;
     asm volatile (
-        "pushf\n"               /* read flags */
-        "popl %0\n"
-        "movl %0, %1\n"
+        "pushf\n"                    /* read flags */
+        "popl %[ret]\n"
+        "movl %[ret], %[val]\n"
-        "btcl $21, %1\n"        /* swap the ID bit */
+        "btcl $21, %[val]\n"         /* swap the ID bit */
-        "pushl %1\n"            /* propagate the change into flags */
+        "pushl %[val]\n"             /* propagate the change into flags */
         "popf\n"
         "pushf\n"
-        "popl %1\n"
+        "popl %[val]\n"
-        "andl $(1 << 21), %0\n" /* interrested only in ID bit */
-        "andl $(1 << 21), %1\n"
-        "xorl %1, %0\n"
-        : "=r" (ret), "=r" (val)
+        "andl $(1 << 21), %[ret]\n"  /* interrested only in ID bit */
+        "andl $(1 << 21), %[val]\n"
+        "xorl %[val], %[ret]\n"
+        : [ret] "=r" (ret), [val] "=r" (val)
     );
     return ret;
 ,7 → 98,8
 {
     asm volatile (
         "cpuid\n"
-        : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx), "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
+        : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx),
+          "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
         : "a" (cmd)
     );
 }

 /branches/network/kernel/arch/ia32/include/types.h
 ,6 → 57,9
 typedef uint32_t unative_t;
 typedef int32_t native_t;
+typedef struct {
+} fncptr_t;
 #define PRIp "x"    /**< Format for uintptr_t. */
 #define PRIs "u"    /**< Format for size_t. */
 #define PRIc "u"    /**< Format for count_t. */

/branches/network/kernel/arch/ia32/include/syscall.h
0,0 → 1,0
link ../../amd64/include/syscall.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

 /branches/network/kernel/arch/ia32/include/atomic.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,17 → 41,29
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-    asm volatile ("lock incl %0\n" : "+m" (val->count));
+    asm volatile (
+        "lock incl %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #else
-    asm volatile ("incl %0\n" : "+m" (val->count));
+    asm volatile (
+        "incl %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #endif /* CONFIG_SMP */
 }
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-    asm volatile ("lock decl %0\n" : "+m" (val->count));
+    asm volatile (
+        "lock decl %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #else
-    asm volatile ("decl %0\n" : "+m" (val->count));
+    asm volatile (
+        "decl %[count]\n"
+        : [count] "+m" (val->count)
+    );
 #endif /* CONFIG_SMP */
 }
 ,12 → 70,12
 static inline long atomic_postinc(atomic_t *val)
 {
     long r = 1;
     asm volatile (
-        "lock xaddl %1, %0\n"
-        : "+m" (val->count), "+r" (r)
+        "lock xaddl %[r], %[count]\n"
+        : [count] "+m" (val->count), [r] "+r" (r)
     );
     return r;
 }
 ,23 → 84,23
     long r = -1;
     asm volatile (
-        "lock xaddl %1, %0\n"
-        : "+m" (val->count), "+r"(r)
+        "lock xaddl %[r], %[count]\n"
+        : [count] "+m" (val->count), [r] "+r"(r)
     );
     return r;
 }
-#define atomic_preinc(val) (atomic_postinc(val) + 1)
-#define atomic_predec(val) (atomic_postdec(val) - 1)
+#define atomic_preinc(val)  (atomic_postinc(val) + 1)
+#define atomic_predec(val)  (atomic_postdec(val) - 1)
 static inline uint32_t test_and_set(atomic_t *val) {
     uint32_t v;
     asm volatile (
-        "movl $1, %0\n"
-        "xchgl %0, %1\n"
-        : "=r" (v),"+m" (val->count)
+        "movl $1, %[v]\n"
+        "xchgl %[v], %[count]\n"
+        : [v] "=r" (v), [count] "+m" (val->count)
     );
     return v;
 ,22 → 110,22
 static inline void atomic_lock_arch(atomic_t *val)
 {
     uint32_t tmp;
     preemption_disable();
     asm volatile (
         "0:\n"
 #ifdef CONFIG_HT
-        "pause\n" /* Pentium 4's HT love this instruction */
+        "pause\n"        /* Pentium 4's HT love this instruction */
 #endif
-        "mov %0, %1\n"
-        "testl %1, %1\n"
+        "mov %[count], %[tmp]\n"
+        "testl %[tmp], %[tmp]\n"
         "jnz 0b\n"       /* lightweight looping on locked spinlock */
-        "incl %1\n"      /* now use the atomic operation */
-        "xchgl %0, %1\n"
-        "testl %1, %1\n"
+        "incl %[tmp]\n"  /* now use the atomic operation */
+        "xchgl %[count], %[tmp]\n"
+        "testl %[tmp], %[tmp]\n"
         "jnz 0b\n"
-                : "+m" (val->count), "=&r"(tmp)
+        : [count] "+m" (val->count), [tmp] "=&r" (tmp)
     );
     /*
      * Prevent critical section code from bleeding out this way up.

 /branches/network/kernel/arch/ia32/include/pm.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,61 → 35,59
 #ifndef KERN_ia32_PM_H_
 #define KERN_ia32_PM_H_
-#define IDT_ITEMS   64
-#define GDT_ITEMS   7
+#define IDT_ITEMS  64
+#define GDT_ITEMS  7
-#define VESA_INIT_SEGMENT 0x8000
+#define NULL_DES   0
+#define KTEXT_DES  1
+#define KDATA_DES  2
+#define UTEXT_DES  3
+#define UDATA_DES  4
+#define TSS_DES    5
+#define TLS_DES    6  /* Pointer to Thread-Local-Storage data */
-#define NULL_DES    0
-#define KTEXT_DES   1
-#define KDATA_DES   2
-#define UTEXT_DES   3
-#define UDATA_DES   4
-#define TSS_DES     5
-#define TLS_DES     6 /* Pointer to Thread-Local-Storage data */
 #ifdef CONFIG_FB
-#define VESA_INIT_SEGMENT 0x8000
-#define VESA_INIT_DES 7
+#define VESA_INIT_SEGMENT  0x8000
+#define VESA_INIT_DES      7
+#define KTEXT32_DES        KTEXT_DES
 #undef GDT_ITEMS
-#define GDT_ITEMS 8
+#define GDT_ITEMS  8
 #endif /* CONFIG_FB */
+#define gdtselector(des)  ((des) << 3)
-#define selector(des)   ((des) << 3)
+#define PL_KERNEL  0
+#define PL_USER    3
-#define PL_KERNEL   0
-#define PL_USER     3
+#define AR_PRESENT    (1 << 7)
+#define AR_DATA       (2 << 3)
+#define AR_CODE       (3 << 3)
+#define AR_WRITABLE   (1 << 1)
+#define AR_INTERRUPT  (0x0e)
+#define AR_TSS        (0x09)
-#define AR_PRESENT  (1 << 7)
-#define AR_DATA     (2 << 3)
-#define AR_CODE     (3 << 3)
-#define AR_WRITABLE (1 << 1)
-#define AR_INTERRUPT    (0xe)
-#define AR_TSS      (0x9)
+#define DPL_KERNEL  (PL_KERNEL << 5)
+#define DPL_USER    (PL_USER << 5)
-#define DPL_KERNEL  (PL_KERNEL << 5)
-#define DPL_USER    (PL_USER << 5)
+#define TSS_BASIC_SIZE  104
+#define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
-#define TSS_BASIC_SIZE  104
-#define TSS_IOMAP_SIZE  (16 * 1024 + 1) /* 16K for bitmap + 1 terminating byte for convenience */
+#define IO_PORTS  (64 * 1024)
-#define IO_PORTS    (64 * 1024)
 #ifndef __ASM__
 #include <arch/types.h>
 #include <arch/context.h>
-struct ptr_16_32 {
+typedef struct {
     uint16_t limit;
     uint32_t base;
-} __attribute__ ((packed));
-typedef struct ptr_16_32 ptr_16_32_t;
+} __attribute__ ((packed)) ptr_16_32_t;
-struct descriptor {
+typedef struct {
     unsigned limit_0_15: 16;
     unsigned base_0_15: 16;
     unsigned base_16_23: 8;
 ,19 → 98,17
     unsigned special: 1;
     unsigned granularity : 1;
     unsigned base_24_31: 8;
-} __attribute__ ((packed));
-typedef struct descriptor  descriptor_t;
+} __attribute__ ((packed)) descriptor_t;
-struct idescriptor {
+typedef struct {
     unsigned offset_0_15: 16;
     unsigned selector: 16;
     unsigned unused: 8;
     unsigned access: 8;
     unsigned offset_16_31: 16;
-} __attribute__ ((packed));
-typedef struct idescriptor idescriptor_t;
+} __attribute__ ((packed)) idescriptor_t;
-struct tss {
+typedef struct {
     uint16_t link;
     unsigned : 16;
     uint32_t esp0;
 ,13 → 148,12
     unsigned : 16;
     uint16_t iomap_base;
     uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed));
-typedef struct tss tss_t;
+} __attribute__ ((packed)) tss_t;
 extern ptr_16_32_t gdtr;
 extern ptr_16_32_t bootstrap_gdtr;
 extern ptr_16_32_t protected_ap_gdtr;
-extern struct tss *tss_p;
+extern tss_t *tss_p;
 extern descriptor_t gdt[];

 /branches/network/kernel/arch/ia32/include/boot/memmap.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,24 → 35,29
 #ifndef KERN_ia32_MEMMAP_H_
 #define KERN_ia32_MEMMAP_H_
-/* E820h memory range types - other values*/
-    /* Free memory */
-#define MEMMAP_MEMORY_AVAILABLE 1
-    /* Not available for OS */
-#define MEMMAP_MEMORY_RESERVED  2
-    /* OS may use it after reading ACPI table */
-#define MEMMAP_MEMORY_ACPI  3
-    /* Unusable, required to be saved and restored across an NVS sleep */
-#define MEMMAP_MEMORY_NVS   4
-    /* Corrupted memory */
-#define MEMMAP_MEMORY_UNUSABLE  5
+/* E820h memory range types */
-     /* size of one entry */
-#define MEMMAP_E820_RECORD_SIZE 20
-    /* maximum entries */
-#define MEMMAP_E820_MAX_RECORDS 32
+/* Free memory */
+#define MEMMAP_MEMORY_AVAILABLE  1
+/* Not available for OS */
+#define MEMMAP_MEMORY_RESERVED   2
+/* OS may use it after reading ACPI table */
+#define MEMMAP_MEMORY_ACPI       3
+/* Unusable, required to be saved and restored across an NVS sleep */
+#define MEMMAP_MEMORY_NVS        4
+/* Corrupted memory */
+#define MEMMAP_MEMORY_UNUSABLE   5
+/* Size of one entry */
+#define MEMMAP_E820_RECORD_SIZE  20
+/* Maximum entries */
+#define MEMMAP_E820_MAX_RECORDS  32
 #ifndef __ASM__
 #include <arch/types.h>

 /branches/network/kernel/arch/ia32/include/boot/boot.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,15 → 35,24
 #ifndef KERN_ia32_BOOT_H_
 #define KERN_ia32_BOOT_H_
-#define BOOT_OFFSET     0x108000
-#define AP_BOOT_OFFSET      0x8000
-#define BOOT_STACK_SIZE 0x400
+#define BOOT_OFFSET      0x108000
+#define AP_BOOT_OFFSET   0x8000
+#define BOOT_STACK_SIZE  0x400
-#define MULTIBOOT_HEADER_MAGIC  0x1BADB002
-#define MULTIBOOT_HEADER_FLAGS  0x00010003
+#define MULTIBOOT_HEADER_MAGIC  0x1BADB002
+#define MULTIBOOT_HEADER_FLAGS  0x00010003
-#define MULTIBOOT_LOADER_MAGIC  0x2BADB002
+#ifndef __ASM__
+#ifdef CONFIG_SMP
+/* This is only a symbol so the type is dummy. Obtain the value using &. */
+extern int _hardcoded_unmapped_size;
+#endif /* CONFIG_SMP */
+#endif /* __ASM__ */
 #endif
 /** @}

 /branches/network/kernel/arch/ia32/include/arch.h
 ,5 → 1,5
 /*
- * Copyright (c) 2005 Martin Decky
+ * Copyright (c) 2009 Martin Decky
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,6 → 35,10
 #ifndef KERN_ia32_ARCH_H_
 #define KERN_ia32_ARCH_H_
+#include <genarch/multiboot/multiboot.h>
+extern void arch_pre_main(uint32_t, const multiboot_info_t *);
 #endif
 /** @}

 /branches/network/kernel/arch/ia32/include/asm.h
 ,7 → 27,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,6 → 38,7
 #include <arch/pm.h>
 #include <arch/types.h>
+#include <typedefs.h>
 #include <config.h>
 extern uint32_t interrupt_handler_size;
 ,11 → 56,16
 /** Halt CPU
  *
- * Halt the current CPU until interrupt event.
+ * Halt the current CPU.
+ *
  */
 static inline void cpu_halt(void)
 {
-    asm volatile ("hlt\n");
+    asm volatile (
+        "0:\n"
+        "   hlt\n"
+        "   jmp 0b\n"
+    );
 }
 static inline void cpu_sleep(void)
 ,16 → 74,22
 }
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
-    { \
-    unative_t res; \
-    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
-    return res; \
-    }
+    { \
+        unative_t res; \
+        asm volatile ( \
+            "movl %%" #reg ", %[res]" \
+            : [res] "=r" (res) \
+        ); \
+        return res; \
+    }
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
-    { \
-    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
-    }
+    { \
+        asm volatile ( \
+            "movl %[regn], %%" #reg \
+            :: [regn] "r" (regn) \
+        ); \
+    }
 GEN_READ_REG(cr0)
 GEN_READ_REG(cr2)
 ,10 → 116,14
  *
  * @param port Port to write to
  * @param val Value to write
+ *
  */
-static inline void outb(uint16_t port, uint8_t val)
+static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
-    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
+    asm volatile (
+        "outb %b[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
 }
 /** Word to port
 ,10 → 132,14
  *
  * @param port Port to write to
  * @param val Value to write
+ *
  */
-static inline void outw(uint16_t port, uint16_t val)
+static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
-    asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
+    asm volatile (
+        "outw %w[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
 }
 /** Double word to port
 ,10 → 148,14
  *
  * @param port Port to write to
  * @param val Value to write
+ *
  */
-static inline void outl(uint16_t port, uint32_t val)
+static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
-    asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
+    asm volatile (
+        "outl %[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
 }
 /** Byte from port
 ,12 → 164,18
  *
  * @param port Port to read from
  * @return Value read
+ *
  */
-static inline uint8_t inb(uint16_t port)
+static inline uint8_t pio_read_8(ioport8_t *port)
 {
     uint8_t val;
-    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) );
+    asm volatile (
+        "inb %w[port], %b[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
     return val;
 }
 ,12 → 185,18
  *
  * @param port Port to read from
  * @return Value read
+ *
  */
-static inline uint16_t inw(uint16_t port)
+static inline uint16_t pio_read_16(ioport16_t *port)
 {
     uint16_t val;
-    asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) );
+    asm volatile (
+        "inw %w[port], %w[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
     return val;
 }
 ,12 → 206,18
  *
  * @param port Port to read from
  * @return Value read
+ *
  */
-static inline uint32_t inl(uint16_t port)
+static inline uint32_t pio_read_32(ioport32_t *port)
 {
     uint32_t val;
-    asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) );
+    asm volatile (
+        "inl %w[port], %[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
     return val;
 }
 ,16 → 227,19
  * value of EFLAGS.
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void)
 {
     ipl_t v;
     asm volatile (
-        "pushf\n\t"
-        "popl %0\n\t"
+        "pushf\n"
+        "popl %[v]\n"
         "sti\n"
-        : "=r" (v)
+        : [v] "=r" (v)
     );
     return v;
 }
 ,16 → 249,19
  * value of EFLAGS.
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void)
 {
     ipl_t v;
     asm volatile (
-        "pushf\n\t"
-        "popl %0\n\t"
+        "pushf\n"
+        "popl %[v]\n"
         "cli\n"
-        : "=r" (v)
+        : [v] "=r" (v)
     );
     return v;
 }
 ,13 → 270,14
  * Restore EFLAGS.
  *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl)
 {
     asm volatile (
-        "pushl %0\n\t"
+        "pushl %[ipl]\n"
         "popf\n"
-        : : "r" (ipl)
+        :: [ipl] "r" (ipl)
     );
 }
 ,23 → 284,51
 /** Return interrupt priority level.
  *
  * @return EFLAFS.
+ *
  */
 static inline ipl_t interrupts_read(void)
 {
     ipl_t v;
     asm volatile (
-        "pushf\n\t"
-        "popl %0\n"
-        : "=r" (v)
+        "pushf\n"
+        "popl %[v]\n"
+        : [v] "=r" (v)
     );
     return v;
 }
+/** Write to MSR */
+static inline void write_msr(uint32_t msr, uint64_t value)
+{
+    asm volatile (
+        "wrmsr"
+        :: "c" (msr), "a" ((uint32_t) (value)),
+           "d" ((uint32_t) (value >> 32))
+    );
+}
+static inline uint64_t read_msr(uint32_t msr)
+{
+    uint32_t ax, dx;
+    asm volatile (
+        "rdmsr"
+        : "=a" (ax), "=d" (dx)
+        : "c" (msr)
+    );
+    return ((uint64_t) dx << 32) | ax;
+}
 /** Return base address of current stack
  *
  * Return the base address of the current stack.
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
 {
 ,8 → 335,8
     uintptr_t v;
     asm volatile (
-        "andl %%esp, %0\n"
-        : "=r" (v)
+        "andl %%esp, %[v]\n"
+        : [v] "=r" (v)
         : "0" (~(STACK_SIZE - 1))
     );
 ,11 → 347,12
 static inline uintptr_t * get_ip()
 {
     uintptr_t *ip;
     asm volatile (
-        "mov %%eip, %0"
-        : "=r" (ip)
-        );
+        "mov %%eip, %[ip]"
+        : [ip] "=r" (ip)
+    );
     return ip;
 }
 ,46 → 359,66
 /** Invalidate TLB Entry.
  *
  * @param addr Address on a page whose TLB entry is to be invalidated.
+ *
  */
 static inline void invlpg(uintptr_t addr)
 {
-    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+    asm volatile (
+        "invlpg %[addr]\n"
+        :: [addr] "m" (*(unative_t *) addr)
+    );
 }
 /** Load GDTR register from memory.
  *
  * @param gdtr_reg Address of memory from where to load GDTR.
+ *
  */
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
-    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+    asm volatile (
+        "lgdtl %[gdtr_reg]\n"
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
 }
 /** Store GDTR register to memory.
  *
  * @param gdtr_reg Address of memory to where to load GDTR.
+ *
  */
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
-    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+    asm volatile (
+        "sgdtl %[gdtr_reg]\n"
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
 }
 /** Load IDTR register from memory.
  *
  * @param idtr_reg Address of memory from where to load IDTR.
+ *
  */
 static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
-    asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+    asm volatile (
+        "lidtl %[idtr_reg]\n"
+        :: [idtr_reg] "m" (*idtr_reg)
+    );
 }
 /** Load TR from descriptor table.
  *
  * @param sel Selector specifying descriptor of TSS segment.
+ *
  */
 static inline void tr_load(uint16_t sel)
 {
-    asm volatile ("ltr %0" : : "r" (sel));
+    asm volatile (
+        "ltr %[sel]"
+        :: [sel] "r" (sel)
+    );
 }
 #endif

 /branches/network/kernel/arch/ia32/include/mm/frame.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32mm
+/** @addtogroup ia32mm
  * @{
  */
 /** @file
 ,8 → 35,8
 #ifndef KERN_ia32_FRAME_H_
 #define KERN_ia32_FRAME_H_
-#define FRAME_WIDTH 12  /* 4K */
-#define FRAME_SIZE  (1 << FRAME_WIDTH)
+#define FRAME_WIDTH  12  /* 4K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
 #ifdef KERNEL
 #ifndef __ASM__

 /branches/network/kernel/arch/ia32/include/mm/tlb.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32mm
+/** @addtogroup ia32mm
  * @{
  */
 /** @file
 ,9 → 35,6
 #ifndef KERN_ia32_TLB_H_
 #define KERN_ia32_TLB_H_
-#define tlb_arch_init()
-#define tlb_print()
 #endif
 /** @}

 /branches/network/kernel/arch/ia32/include/mm/as.h
 ,7 → 42,7
 #define USER_ADDRESS_SPACE_START_ARCH       ((unsigned long) 0x00000000)
 #define USER_ADDRESS_SPACE_END_ARCH     ((unsigned long) 0x7fffffff)
-#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH-(PAGE_SIZE-1))
+#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
 typedef struct {
 } as_arch_t;

 /branches/network/kernel/arch/ia32/include/barrier.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,8 → 46,8
  * Provisions are made to prevent compiler from reordering instructions itself.
  */
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 static inline void cpuid_serialization(void)
 {
 ,30 → 58,30
     );
 }
-#ifdef CONFIG_FENCES_P4
-#   define memory_barrier()     asm volatile ("mfence\n" ::: "memory")
-#   define read_barrier()       asm volatile ("lfence\n" ::: "memory")
-#   ifdef CONFIG_WEAK_MEMORY
-#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-#   else
-#       define write_barrier()  asm volatile( "" ::: "memory");
-#   endif
-#elif CONFIG_FENCES_P3
-#   define memory_barrier()     cpuid_serialization()
-#   define read_barrier()       cpuid_serialization()
-#   ifdef CONFIG_WEAK_MEMORY
-#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-#   else
-#       define write_barrier()  asm volatile( "" ::: "memory");
-#   endif
+#if defined(CONFIG_FENCES_P4)
+    #define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
+    #define read_barrier()    asm volatile ("lfence\n" ::: "memory")
+    #ifdef CONFIG_WEAK_MEMORY
+        #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+    #else
+        #define write_barrier()  asm volatile ("" ::: "memory");
+    #endif
+#elif defined(CONFIG_FENCES_P3)
+    #define memory_barrier()  cpuid_serialization()
+    #define read_barrier()    cpuid_serialization()
+    #ifdef CONFIG_WEAK_MEMORY
+        #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+    #else
+        #define write_barrier()  asm volatile ("" ::: "memory");
+    #endif
 #else
-#   define memory_barrier()     cpuid_serialization()
-#   define read_barrier()       cpuid_serialization()
-#   ifdef CONFIG_WEAK_MEMORY
-#       define write_barrier()  cpuid_serialization()
-#   else
-#       define write_barrier()  asm volatile( "" ::: "memory");
-#   endif
+    #define memory_barrier()  cpuid_serialization()
+    #define read_barrier()    cpuid_serialization()
+    #ifdef CONFIG_WEAK_MEMORY
+        #define write_barrier()  cpuid_serialization()
+    #else
+        #define write_barrier()  asm volatile ("" ::: "memory");
+    #endif
 #endif
 /*
 ,8 → 90,8
  * queueing in the store buffer drain to the memory (even though it would be
  * sufficient for them to drain to the D-cache).
  */
-#define smc_coherence(a)        write_barrier()
-#define smc_coherence_block(a, l)   write_barrier()
+#define smc_coherence(a)           write_barrier()
+#define smc_coherence_block(a, l)  write_barrier()
 #endif

 /branches/network/kernel/arch/ia32/include/cpu.h
 ,25 → 35,33
 #ifndef KERN_ia32_CPU_H_
 #define KERN_ia32_CPU_H_
+#define EFLAGS_IF       (1 << 9)
+#define EFLAGS_RF       (1 << 16)
+#define CR4_OSFXSR_MASK (1<<9)
+/* Support for SYSENTER and SYSEXIT */
+#define IA32_MSR_SYSENTER_CS    0x174
+#define IA32_MSR_SYSENTER_ESP   0x175
+#define IA32_MSR_SYSENTER_EIP   0x176
+#ifndef __ASM__
 #include <arch/pm.h>
 #include <arch/asm.h>
-#define EFLAGS_IF       (1 << 9)
-#define EFLAGS_RF       (1 << 16)
 typedef struct {
-    int vendor;
-    int family;
-    int model;
-    int stepping;
-    struct tss *tss;
+    unsigned int vendor;
+    unsigned int family;
+    unsigned int model;
+    unsigned int stepping;
+    tss_t *tss;
     count_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;
+#endif
-#define CR4_OSFXSR_MASK (1<<9)
 #endif
 /** @}

 /branches/network/kernel/arch/ia32/include/drivers/i8254.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file

 /branches/network/kernel/arch/ia32/include/drivers/vesa.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,6 → 36,7
 #define KERN_ia32_VESA_H_
 extern int vesa_present(void);
+extern void vesa_redraw(void);
 extern void vesa_init(void);
 #endif

 /branches/network/kernel/arch/ia32/include/drivers/i8259.h
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,13 → 38,13
 #include <arch/types.h>
 #include <arch/interrupt.h>
-#define PIC_PIC0PORT1   0x20
-#define PIC_PIC0PORT2   0x21
-#define PIC_PIC1PORT1   0xa0
-#define PIC_PIC1PORT2   0xa1
+#define PIC_PIC0PORT1  ((ioport8_t *) 0x20)
+#define PIC_PIC0PORT2  ((ioport8_t *) 0x21)
+#define PIC_PIC1PORT1  ((ioport8_t *) 0xa0)
+#define PIC_PIC1PORT2  ((ioport8_t *) 0xa1)
-#define PIC_NEEDICW4    (1<<0)
-#define PIC_ICW1    (1<<4)
+#define PIC_NEEDICW4  (1 << 0)
+#define PIC_ICW1      (1 << 4)
 extern void i8259_init(void);
 extern void pic_enable_irqs(uint16_t irqmask);

 /branches/network/kernel/arch/ia32/Makefile.inc
 ,10 → 29,6
 ## Toolchain configuration
 #
-ifndef CROSS_PREFIX
-    CROSS_PREFIX = /usr/local
-endif
 BFD_NAME = elf32-i386
 BFD_ARCH = i386
 BFD = binary
 ,7 → 35,7
 TARGET = i686-pc-linux-gnu
 TOOLCHAIN_DIR = $(CROSS_PREFIX)/i686
-DEFS += -DMACHINE=$(MACHINE) -D__32_BITS__
+DEFS += -D__32_BITS__
 CMN1 = -m32
 GCC_CFLAGS += $(CMN1)
 ,115 → 45,61
 ## Accepted CPUs
 #
-ifeq ($(MACHINE),athlon-xp)
-    FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-3dnow
+ifeq ($(PROCESSOR),athlon_xp)
     CMN2 = -march=athlon-xp
-    GCC_CFLAGS += $(CMN2)
-    ICC_CFLAGS += $(CMN2)
     SUNCC_CFLAGS += -xarch=ssea
-    DEFS += -DCONFIG_FENCES_P3
-    CONFIG_SMP = n
-    CONFIG_HT = n
 endif
-ifeq ($(MACHINE),athlon-mp)
-    FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-3dnow
+ifeq ($(PROCESSOR),athlon_mp)
     CMN2 = -march=athlon-mp
-    GCC_CFLAGS += $(CMN2)
-    ICC_CFLAGS += $(CMN2)
     SUNCC_CFLAGS += xarch=ssea
-    DEFS += -DCONFIG_FENCES_P3
-    CONFIG_HT = n
 endif
-ifeq ($(MACHINE),pentium3)
-    FPU_NO_CFLAGS = -mno-mmx -mno-sse
+ifeq ($(PROCESSOR),pentium3)
     CMN2 = -march=pentium3
-    GCC_CFLAGS += $(CMN2)
-    ICC_CFLAGS += $(CMN2)
     SUNCC_CFLAGS += -xarch=sse
-    DEFS += -DCONFIG_FENCES_P3
-    CONFIG_HT = n
 endif
-ifeq ($(MACHINE),core)
-    FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-sse2 -mno-sse3
+ifeq ($(PROCESSOR),pentium4)
+    CMN2 = -march=pentium4
+    SUNCC_CFLAGS += -xarch=sse2
+endif
+ifeq ($(PROCESSOR),core)
     CMN2 = -march=prescott
-    GCC_CFLAGS += $(CMN2)
-    ICC_CFLAGS += $(CMN2)
     SUNCC_CFLAGS += -xarch=sse3
-    DEFS += -DCONFIG_FENCES_P4
 endif
-ifeq ($(MACHINE),pentium4)
-    FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-sse2
-    GCC_CFLAGS += -march=pentium4
-    ICC_CFLAGS += -march=pentium4
-    SUNCC_CFLAGS += -xarch=sse2
-    DEFS += -DCONFIG_FENCES_P4
-endif
-## Own configuration directives
-#
+FPU_NO_CFLAGS = -mno-mmx -mno-sse -mno-sse2 -mno-sse3 -mno-3dnow
+GCC_CFLAGS += $(CMN2)
+ICC_CFLAGS += $(CMN2)
-CONFIG_ACPI = y
-## Compile with hierarchical page tables support.
-#
-CONFIG_PAGE_PT = y
-DEFS += -DCONFIG_PAGE_PT
-## Compile with i8042 controller support
-#
-CONFIG_I8042 = y
-DEFS += -DCONFIG_I8042
-## Accepted configuration directives
-#
-ifeq ($(CONFIG_SMP),y)
-    DEFS += -DCONFIG_SMP
-endif
-ifeq ($(CONFIG_HT),y)
-    DEFS += -DCONFIG_HT
-endif
-ifeq ($(CONFIG_SIMICS_FIX),y)
-    DEFS += -DCONFIG_SIMICS_FIX
-endif
-## Compile with support for software integer division.
-#
-CONFIG_SOFTINT = y
 ARCH_SOURCES = \
-    arch/$(ARCH)/src/context.S \
-    arch/$(ARCH)/src/debug/panic.s \
-    arch/$(ARCH)/src/delay.s \
-    arch/$(ARCH)/src/asm.S \
-    arch/$(ARCH)/src/proc/scheduler.c \
-    arch/$(ARCH)/src/proc/task.c \
-    arch/$(ARCH)/src/proc/thread.c \
-    arch/$(ARCH)/src/bios/bios.c \
-    arch/$(ARCH)/src/smp/ap.S \
-    arch/$(ARCH)/src/smp/apic.c \
-    arch/$(ARCH)/src/smp/mps.c \
-    arch/$(ARCH)/src/smp/smp.c \
-    arch/$(ARCH)/src/atomic.S \
-    arch/$(ARCH)/src/smp/ipi.c \
-    arch/$(ARCH)/src/ia32.c \
-    arch/$(ARCH)/src/interrupt.c \
-    arch/$(ARCH)/src/pm.c \
-    arch/$(ARCH)/src/userspace.c \
-    arch/$(ARCH)/src/cpu/cpu.c \
-    arch/$(ARCH)/src/mm/as.c \
-    arch/$(ARCH)/src/mm/frame.c \
-    arch/$(ARCH)/src/mm/page.c \
-    arch/$(ARCH)/src/mm/tlb.c \
-    arch/$(ARCH)/src/ddi/ddi.c \
-    arch/$(ARCH)/src/drivers/i8254.c \
-    arch/$(ARCH)/src/drivers/i8259.c \
-    arch/$(ARCH)/src/drivers/ega.c \
-    arch/$(ARCH)/src/drivers/vesa.c \
-    arch/$(ARCH)/src/boot/boot.S \
-    arch/$(ARCH)/src/boot/memmap.c \
-    arch/$(ARCH)/src/fpu_context.c \
-    arch/$(ARCH)/src/debugger.c
+    arch/$(KARCH)/src/context.S \
+    arch/$(KARCH)/src/debug/panic.s \
+    arch/$(KARCH)/src/delay.s \
+    arch/$(KARCH)/src/asm.S \
+    arch/$(KARCH)/src/proc/scheduler.c \
+    arch/$(KARCH)/src/proc/task.c \
+    arch/$(KARCH)/src/proc/thread.c \
+    arch/$(KARCH)/src/bios/bios.c \
+    arch/$(KARCH)/src/smp/ap.S \
+    arch/$(KARCH)/src/smp/apic.c \
+    arch/$(KARCH)/src/smp/mps.c \
+    arch/$(KARCH)/src/smp/smp.c \
+    arch/$(KARCH)/src/atomic.S \
+    arch/$(KARCH)/src/smp/ipi.c \
+    arch/$(KARCH)/src/ia32.c \
+    arch/$(KARCH)/src/interrupt.c \
+    arch/$(KARCH)/src/pm.c \
+    arch/$(KARCH)/src/userspace.c \
+    arch/$(KARCH)/src/cpu/cpu.c \
+    arch/$(KARCH)/src/mm/as.c \
+    arch/$(KARCH)/src/mm/frame.c \
+    arch/$(KARCH)/src/mm/page.c \
+    arch/$(KARCH)/src/mm/tlb.c \
+    arch/$(KARCH)/src/ddi/ddi.c \
+    arch/$(KARCH)/src/drivers/i8254.c \
+    arch/$(KARCH)/src/drivers/i8259.c \
+    arch/$(KARCH)/src/drivers/vesa.c \
+    arch/$(KARCH)/src/boot/boot.S \
+    arch/$(KARCH)/src/boot/memmap.c \
+    arch/$(KARCH)/src/fpu_context.c \
+    arch/$(KARCH)/src/debugger.c \
+    arch/$(KARCH)/src/syscall.c

 /branches/network/kernel/arch/ia32/src/ia32.c
 ,5 → 1,7
 /*
  * Copyright (c) 2001-2004 Jakub Jermar
+ * Copyright (c) 2009 Jiri Svoboda
+ * Copyright (c) 2009 Martin Decky
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,9 → 40,12
 #include <arch/pm.h>
-#include <arch/drivers/ega.h>
+#include <genarch/multiboot/multiboot.h>
+#include <genarch/drivers/legacy/ia32/io.h>
+#include <genarch/drivers/ega/ega.h>
 #include <arch/drivers/vesa.h>
-#include <genarch/kbd/i8042.h>
+#include <genarch/drivers/i8042/i8042.h>
+#include <genarch/kbrd/kbrd.h>
 #include <arch/drivers/i8254.h>
 #include <arch/drivers/i8259.h>
 ,12 → 65,30
 #include <proc/thread.h>
 #include <syscall/syscall.h>
 #include <console/console.h>
-#include <ddi/device.h>
+#include <sysinfo/sysinfo.h>
+#include <arch/boot/boot.h>
 #ifdef CONFIG_SMP
 #include <arch/smp/apic.h>
 #endif
+/** Perform ia32-specific initialization before main_bsp() is called.
+ *
+ * @param signature Should contain the multiboot signature.
+ * @param mi        Pointer to the multiboot information structure.
+ */
+void arch_pre_main(uint32_t signature, const multiboot_info_t *mi)
+{
+    /* Parse multiboot information obtained from the bootloader. */
+    multiboot_info_parse(signature, mi);
+#ifdef CONFIG_SMP
+    /* Copy AP bootstrap routines below 1 MB. */
+    memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
+        (size_t) &_hardcoded_unmapped_size);
+#endif
+}
 void arch_pre_mm_init(void)
 {
     pm_init();
 ,13 → 110,17
         /* hard clock */
         i8254_init();
 #ifdef CONFIG_FB
-        if (vesa_present())
+        if (vesa_present())
             vesa_init();
         else
 #endif
-            ega_init(); /* video */
+#ifdef CONFIG_EGA
+            ega_init(EGA_BASE, EGA_VIDEORAM);  /* video */
+#else
+            {}
+#endif
         /* Enable debugger */
         debugger_init();
 ,10 → 150,28
 void arch_post_smp_init(void)
 {
-    devno_t kbd = device_assign_devno();
-    devno_t mouse = device_assign_devno();
-    /* keyboard controller */
-    i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE);
+#ifdef CONFIG_PC_KBD
+    /*
+     * Initialize the i8042 controller. Then initialize the keyboard
+     * module and connect it to i8042. Enable keyboard interrupts.
+     */
+    indev_t *kbrdin = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
+    if (kbrdin) {
+        kbrd_init(kbrdin);
+        trap_virtual_enable_irqs(1 << IRQ_KBD);
+    }
+    /*
+     * This is the necessary evil until the userspace driver is entirely
+     * self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
+    sysinfo_set_item_val("kbd.address.physical", NULL,
+        (uintptr_t) I8042_BASE);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) I8042_BASE);
+#endif
 }
 void calibrate_delay_loop(void)
 ,15 → 204,38
  */
 void arch_grab_console(void)
 {
-    i8042_grab();
+#ifdef CONFIG_FB
+    if (vesa_present())
+        vesa_redraw();
+    else
+#endif
+#ifdef CONFIG_EGA
+        ega_redraw();
+#else
+        {}
+#endif
 }
 /** Return console to userspace
  *
  */
 void arch_release_console(void)
 {
-    i8042_release();
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/network/kernel/arch/ia32/src/fpu_context.c
 ,46 → 44,43
 static void fpu_context_f_save(fpu_context_t *fctx)
 {
     asm volatile (
-        "fnsave %0"
-        : "=m"(*fctx)
-        );
+        "fnsave %[fctx]"
+        : [fctx] "=m" (*fctx)
+    );
 }
 static void fpu_context_f_restore(fpu_context_t *fctx)
 {
     asm volatile (
-        "frstor %0"
-        : "=m"(*fctx)
-        );
+        "frstor %[fctx]"
+        : [fctx] "=m" (*fctx)
+    );
 }
 static void fpu_context_fx_save(fpu_context_t *fctx)
 {
     asm volatile (
-        "fxsave %0"
-        : "=m"(*fctx)
-        );
+        "fxsave %[fctx]"
+        : [fctx] "=m" (*fctx)
+    );
 }
 static void fpu_context_fx_restore(fpu_context_t *fctx)
 {
     asm volatile (
-        "fxrstor %0"
-        : "=m"(*fctx)
-        );
+        "fxrstor %[fctx]"
+        : [fctx] "=m" (*fctx)
+    );
 }
-/*
-    Setup using fxsr instruction
-*/
+/* Setup using fxsr instruction */
 void fpu_fxsr(void)
 {
     fpu_save=fpu_context_fx_save;
     fpu_restore=fpu_context_fx_restore;
 }
-/*
-    Setup using not fxsr instruction
-*/
+/* Setup using not fxsr instruction */
 void fpu_fsr(void)
 {
     fpu_save = fpu_context_f_save;
 ,16 → 99,18
 void fpu_init()
 {
-    uint32_t help0 = 0, help1 = 0;
+    uint32_t help0 = 0;
+    uint32_t help1 = 0;
     asm volatile (
-        "fninit;\n"
-        "stmxcsr %0\n"
-        "mov %0,%1;\n"
-        "or %2,%1;\n"
-        "mov %1,%0;\n"
-        "ldmxcsr %0;\n"
-        : "+m" (help0), "+r" (help1)
-        : "i" (0x1f80)
+        "fninit\n"
+        "stmxcsr %[help0]\n"
+        "mov %[help0], %[help1]\n"
+        "or %[magic], %[help1]\n"
+        "mov %[help1], %[help0]\n"
+        "ldmxcsr %[help0]\n"
+        : [help0] "+m" (help0), [help1] "+r" (help1)
+        : [magic] "i" (0x1f80)
     );
 }

 /branches/network/kernel/arch/ia32/src/asm.S
 ,6 → 147,46
     popfl
 .endm
+/*
+ * The SYSENTER syscall mechanism can be used for syscalls with
+ * four or fewer arguments. To pass these four arguments, we
+ * use four registers: EDX, ECX, EBX, ESI. The syscall number
+ * is passed in EAX. We use EDI to remember the return address
+ * and EBP to remember the stack. The INT-based syscall mechanism
+ * can actually handle six arguments plus the syscall number
+ * entirely in registers.
+ */
+.global sysenter_handler
+sysenter_handler:
+    sti
+    pushl %ebp  # remember user stack
+    pushl %edi  # remember return user address
+    pushl %gs   # remember TLS
+    pushl %eax  # syscall number
+    subl $8, %esp   # unused sixth and fifth argument
+    pushl %esi  # fourth argument
+    pushl %ebx  # third argument
+    pushl %ecx  # second argument
+    pushl %edx  # first argument
+    movw $16, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    cld
+    call syscall_handler
+    addl $28, %esp  # remove arguments from stack
+    pop %gs     # restore TLS
+    pop %edx    # prepare return EIP for SYSEXIT
+    pop %ecx    # prepare userspace ESP for SYSEXIT
+    sysexit     # return to userspace
 ## Declare interrupt handlers
 #
 # Declare interrupt handlers for n interrupt
 ,14 → 268,6
     pushl %fs
     pushl %gs
-#ifdef CONFIG_DEBUG_ALLREGS
-    pushl %ebx
-    pushl %ebp
-    pushl %edi
-    pushl %esi
-#else
-    subl $16, %esp
-#endif
     pushl %edx
     pushl %ecx
     pushl %eax
 ,14 → 289,6
     popl %eax
     popl %ecx
     popl %edx
-#ifdef CONFIG_DEBUG_ALLREGS
-    popl %esi
-    popl %edi
-    popl %ebp
-    popl %ebx
-#else
-    addl $16, %esp
-#endif
     popl %gs
     popl %fs

 /branches/network/kernel/arch/ia32/src/cpu/cpu.c
 ,22 → 42,23
 #include <fpu_context.h>
 #include <arch/smp/apic.h>
+#include <arch/syscall.h>
 /*
  * Identification of CPUs.
  * Contains only non-MP-Specification specific SMP code.
  */
-#define AMD_CPUID_EBX   0x68747541
-#define AMD_CPUID_ECX   0x444d4163
-#define AMD_CPUID_EDX   0x69746e65
+#define AMD_CPUID_EBX  0x68747541
+#define AMD_CPUID_ECX  0x444d4163
+#define AMD_CPUID_EDX  0x69746e65
-#define INTEL_CPUID_EBX 0x756e6547
-#define INTEL_CPUID_ECX 0x6c65746e
-#define INTEL_CPUID_EDX 0x49656e69
+#define INTEL_CPUID_EBX  0x756e6547
+#define INTEL_CPUID_ECX  0x6c65746e
+#define INTEL_CPUID_EDX  0x49656e69
 enum vendor {
-    VendorUnknown=0,
+    VendorUnknown = 0,
     VendorAMD,
     VendorIntel
 };
 ,19 → 65,17
 static char *vendor_str[] = {
     "Unknown Vendor",
-    "AuthenticAMD",
-    "GenuineIntel"
+    "AMD",
+    "Intel"
 };
 void fpu_disable(void)
 {
     asm volatile (
-        "mov %%cr0,%%eax;"
-        "or $8,%%eax;"
-        "mov %%eax,%%cr0;"
-        :
-        :
-        :"%eax"
+        "mov %%cr0, %%eax\n"
+        "or $8, %%eax\n"
+        "mov %%eax, %%cr0\n"
+        ::: "%eax"
     );
 }
 ,13 → 82,11
 void fpu_enable(void)
 {
     asm volatile (
-        "mov %%cr0,%%eax;"
-        "and $0xffFFffF7,%%eax;"
-        "mov %%eax,%%cr0;"
-        :
-        :
-        :"%eax"
-    );
+        "mov %%cr0, %%eax\n"
+        "and $0xffFFffF7, %%eax\n"
+        "mov %%eax,%%cr0\n"
+        ::: "%eax"
+    );
 }
 void cpu_arch_init(void)
 ,11 → 98,11
     CPU->arch.tss = tss_p;
     CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
     CPU->fpu_owner = NULL;
     cpuid(1, &info);
     fi.word = info.cpuid_edx;
     efi.word = info.cpuid_ecx;
 ,17 → 109,20
     if (fi.bits.fxsr)
         fpu_fxsr();
     else
-        fpu_fsr();
+        fpu_fsr();
     if (fi.bits.sse) {
         asm volatile (
-            "mov %%cr4,%0\n"
-            "or %1,%0\n"
-            "mov %0,%%cr4\n"
-            : "+r" (help)
-            : "i" (CR4_OSFXSR_MASK|(1<<10))
+            "mov %%cr4, %[help]\n"
+            "or %[mask], %[help]\n"
+            "mov %[help], %%cr4\n"
+            : [help] "+r" (help)
+            : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
         );
     }
+    /* Setup fast SYSENTER/SYSEXIT syscalls */
+    syscall_setup_cpu();
 }
 void cpu_identify(void)
 ,29 → 136,31
         /*
          * Check for AMD processor.
          */
-        if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
+        if ((info.cpuid_ebx == AMD_CPUID_EBX)
+            && (info.cpuid_ecx == AMD_CPUID_ECX)
+            && (info.cpuid_edx == AMD_CPUID_EDX))
             CPU->arch.vendor = VendorAMD;
-        }
         /*
          * Check for Intel processor.
          */
-        if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
+        if ((info.cpuid_ebx == INTEL_CPUID_EBX)
+            && (info.cpuid_ecx == INTEL_CPUID_ECX)
+            && (info.cpuid_edx == INTEL_CPUID_EDX))
             CPU->arch.vendor = VendorIntel;
-        }
         cpuid(1, &info);
-        CPU->arch.family = (info.cpuid_eax>>8)&0xf;
-        CPU->arch.model = (info.cpuid_eax>>4)&0xf;
-        CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
+        CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
+        CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
+        CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;
     }
 }
-void cpu_print_report(cpu_t* m)
+void cpu_print_report(cpu_t* cpu)
 {
-    printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
-        m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
-        m->frequency_mhz);
+    printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
+        cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
+        cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
 }
 /** @}

 /branches/network/kernel/arch/ia32/src/syscall.c
 ,0 → 1,53
+/*
+ * Copyright (c) 2008 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup ia32
+ * @{
+ */
+/** @file
+ */
+#include <arch/syscall.h>
+#include <arch/cpu.h>
+#include <arch/asm.h>
+#include <arch/types.h>
+#include <arch/pm.h>
+/** Enable & setup support for SYSENTER/SYSEXIT */
+void syscall_setup_cpu(void)
+{
+    extern void sysenter_handler(void);
+    /* set kernel mode CS selector */
+    write_msr(IA32_MSR_SYSENTER_CS, gdtselector(KTEXT_DES));
+    /* set kernel mode entry point */
+    write_msr(IA32_MSR_SYSENTER_EIP, (uint32_t) sysenter_handler);
+}
+/** @}
+ */

 /branches/network/kernel/arch/ia32/src/pm.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,7 → 112,7
 void tss_initialize(tss_t *t)
 {
-    memsetb(t, sizeof(struct tss), 0);
+    memsetb(t, sizeof(tss_t), 0);
 }
 /*
 ,7 → 127,7
         d = &idt[i];
         d->unused = 0;
-        d->selector = selector(KTEXT_DES);
+        d->selector = gdtselector(KTEXT_DES);
         d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
 ,7 → 154,7
         "and $0xffff8fff, %%eax\n"
         "push %%eax\n"
         "popfl\n"
-        : : : "eax"
+        ::: "eax"
     );
 }
 ,7 → 165,7
         "mov %%cr0, %%eax\n"
         "and $0xfffbffff, %%eax\n"
         "mov %%eax, %%cr0\n"
-        : : : "eax"
+        ::: "eax"
     );
 }
 ,7 → 198,7
     else {
         tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
         if (!tss_p)
-            panic("could not allocate TSS\n");
+            panic("Cannot allocate TSS.");
     }
     tss_initialize(tss_p);
 ,7 → 214,7
      * As of this moment, the current CPU has its own GDT pointing
      * to its own TSS. We just need to load the TR register.
      */
-    tr_load(selector(TSS_DES));
+    tr_load(gdtselector(TSS_DES));
     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
     clean_AM_flag();          /* Disable alignment check */

 /branches/network/kernel/arch/ia32/src/smp/smp.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,12 → 75,12
     l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME,
         FRAME_ATOMIC | FRAME_KA);
     if (!l_apic_address)
-        panic("cannot allocate address for l_apic\n");
+        panic("Cannot allocate address for l_apic.");
     io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME,
         FRAME_ATOMIC | FRAME_KA);
     if (!io_apic_address)
-        panic("cannot allocate address for io_apic\n");
+        panic("Cannot allocate address for io_apic.");
     if (config.cpu_count > 1) {
         page_mapping_insert(AS_KERNEL, l_apic_address,
 ,8 → 122,8
      * Save 0xa to address 0xf of the CMOS RAM.
      * BIOS will not do the POST after the INIT signal.
      */
-    outb(0x70, 0xf);
-    outb(0x71, 0xa);
+    pio_write_8((ioport8_t *)0x70, 0xf);
+    pio_write_8((ioport8_t *)0x71, 0xa);
     pic_disable_irqs(0xffff);
     apic_init();
 ,8 → 131,8
     uint8_t apic = l_apic_id();
     for (i = 0; i < ops->cpu_count(); i++) {
-        struct descriptor *gdt_new;
+        descriptor_t *gdt_new;
         /*
          * Skip processors marked unusable.
          */
 ,14 → 154,19
         /*
          * Prepare new GDT for CPU in question.
          */
-        gdt_new = (struct descriptor *) malloc(GDT_ITEMS *
-            sizeof(struct descriptor), FRAME_ATOMIC | FRAME_LOW_4_GiB);
+        /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
+         * it needs to be replaced by a generic fuctionality of
+         * the memory subsystem
+         */
+        gdt_new = (descriptor_t *) malloc(GDT_ITEMS *
+            sizeof(descriptor_t), FRAME_ATOMIC);
         if (!gdt_new)
-            panic("couldn't allocate memory for GDT\n");
+            panic("Cannot allocate memory for GDT.");
-        memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor));
-        memsetb(&gdt_new[TSS_DES], sizeof(struct descriptor), 0);
-        protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor);
+        memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t));
+        memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0);
+        protected_ap_gdtr.limit = GDT_ITEMS * sizeof(descriptor_t);
         protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
         gdtr.base = (uintptr_t) gdt_new;

 /branches/network/kernel/arch/ia32/src/smp/apic.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,12 → 132,12
 #endif
 }
-static irq_ownership_t l_apic_timer_claim(void)
+static irq_ownership_t l_apic_timer_claim(irq_t *irq)
 {
     return IRQ_ACCEPT;
 }
-static void l_apic_timer_irq_handler(irq_t *irq, void *arg __attribute__((unused)), ...)
+static void l_apic_timer_irq_handler(irq_t *irq)
 {
     /*
      * Holding a spinlock could prevent clock() from preempting

 /branches/network/kernel/arch/ia32/src/ddi/ddi.c
 ,7 → 156,7
      * type must be changed to describe inactive TSS.
      */
     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
-    tr_load(selector(TSS_DES));
+    tr_load(gdtselector(TSS_DES));
     /*
      * Update the generation count so that faults caused by

 /branches/network/kernel/arch/ia32/src/boot/vga323.pal
 ,256 → 1,256
+    .byte 0x3f, 0x3f, 0x3f, 0x00
+    .byte 0x36, 0x3f, 0x3f, 0x00
+    .byte 0x2d, 0x3f, 0x3f, 0x00
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-    .byte 0x09, 0x2a, 0x1b, 0x00
-    .byte 0x12, 0x2a, 0x1b, 0x00
-    .byte 0x1b, 0x2a, 0x1b, 0x00
-    .byte 0x24, 0x2a, 0x1b, 0x00
-    .byte 0x2d, 0x2a, 0x1b, 0x00
-    .byte 0x36, 0x2a, 0x1b, 0x00
-    .byte 0x3f, 0x2a, 0x1b, 0x00
-    .byte 0x00, 0x3f, 0x1b, 0x00
-    .byte 0x09, 0x3f, 0x1b, 0x00
-    .byte 0x12, 0x3f, 0x1b, 0x00
-    .byte 0x1b, 0x3f, 0x1b, 0x00
-    .byte 0x24, 0x3f, 0x1b, 0x00
-    .byte 0x2d, 0x3f, 0x1b, 0x00
-    .byte 0x36, 0x3f, 0x1b, 0x00
-    .byte 0x3f, 0x3f, 0x1b, 0x00
-    .byte 0x00, 0x00, 0x24, 0x00
-    .byte 0x09, 0x00, 0x24, 0x00
-    .byte 0x12, 0x00, 0x24, 0x00
-    .byte 0x1b, 0x00, 0x24, 0x00
-    .byte 0x24, 0x00, 0x24, 0x00
-    .byte 0x2d, 0x00, 0x24, 0x00
-    .byte 0x36, 0x00, 0x24, 0x00
-    .byte 0x3f, 0x00, 0x24, 0x00
-    .byte 0x00, 0x15, 0x24, 0x00
-    .byte 0x09, 0x15, 0x24, 0x00
-    .byte 0x12, 0x15, 0x24, 0x00
-    .byte 0x1b, 0x15, 0x24, 0x00
-    .byte 0x24, 0x15, 0x24, 0x00
-    .byte 0x2d, 0x15, 0x24, 0x00
-    .byte 0x36, 0x15, 0x24, 0x00
-    .byte 0x3f, 0x15, 0x24, 0x00
-    .byte 0x00, 0x2a, 0x24, 0x00
-    .byte 0x09, 0x2a, 0x24, 0x00
-    .byte 0x12, 0x2a, 0x24, 0x00
-    .byte 0x1b, 0x2a, 0x24, 0x00
-    .byte 0x24, 0x2a, 0x24, 0x00
-    .byte 0x2d, 0x2a, 0x24, 0x00
-    .byte 0x36, 0x2a, 0x24, 0x00
-    .byte 0x3f, 0x2a, 0x24, 0x00
-    .byte 0x00, 0x3f, 0x24, 0x00
-    .byte 0x09, 0x3f, 0x24, 0x00
-    .byte 0x12, 0x3f, 0x24, 0x00
-    .byte 0x1b, 0x3f, 0x24, 0x00
-    .byte 0x24, 0x3f, 0x24, 0x00
-    .byte 0x2d, 0x3f, 0x24, 0x00
-    .byte 0x36, 0x3f, 0x24, 0x00
-    .byte 0x3f, 0x3f, 0x24, 0x00
-    .byte 0x00, 0x00, 0x2d, 0x00
-    .byte 0x09, 0x00, 0x2d, 0x00
-    .byte 0x12, 0x00, 0x2d, 0x00
-    .byte 0x1b, 0x00, 0x2d, 0x00
-    .byte 0x24, 0x00, 0x2d, 0x00
-    .byte 0x2d, 0x00, 0x2d, 0x00
-    .byte 0x36, 0x00, 0x2d, 0x00
-    .byte 0x3f, 0x00, 0x2d, 0x00
-    .byte 0x00, 0x15, 0x2d, 0x00
-    .byte 0x09, 0x15, 0x2d, 0x00
-    .byte 0x12, 0x15, 0x2d, 0x00
-    .byte 0x1b, 0x15, 0x2d, 0x00
-    .byte 0x24, 0x15, 0x2d, 0x00
-    .byte 0x2d, 0x15, 0x2d, 0x00
-    .byte 0x36, 0x15, 0x2d, 0x00
-    .byte 0x3f, 0x15, 0x2d, 0x00
-    .byte 0x00, 0x2a, 0x2d, 0x00
-    .byte 0x09, 0x2a, 0x2d, 0x00
-    .byte 0x12, 0x2a, 0x2d, 0x00
-    .byte 0x1b, 0x2a, 0x2d, 0x00
-    .byte 0x24, 0x2a, 0x2d, 0x00
-    .byte 0x2d, 0x2a, 0x2d, 0x00
-    .byte 0x36, 0x2a, 0x2d, 0x00
-    .byte 0x3f, 0x2a, 0x2d, 0x00
-    .byte 0x00, 0x3f, 0x2d, 0x00
-    .byte 0x09, 0x3f, 0x2d, 0x00
-    .byte 0x12, 0x3f, 0x2d, 0x00
-    .byte 0x1b, 0x3f, 0x2d, 0x00
-    .byte 0x24, 0x3f, 0x2d, 0x00
-    .byte 0x2d, 0x3f, 0x2d, 0x00
-    .byte 0x36, 0x3f, 0x2d, 0x00
-    .byte 0x3f, 0x3f, 0x2d, 0x00
-    .byte 0x00, 0x00, 0x36, 0x00
-    .byte 0x09, 0x00, 0x36, 0x00
-    .byte 0x12, 0x00, 0x36, 0x00
-    .byte 0x1b, 0x00, 0x36, 0x00
-    .byte 0x24, 0x00, 0x36, 0x00
-    .byte 0x2d, 0x00, 0x36, 0x00
-    .byte 0x36, 0x00, 0x36, 0x00
-    .byte 0x3f, 0x00, 0x36, 0x00
-    .byte 0x00, 0x15, 0x36, 0x00
-    .byte 0x09, 0x15, 0x36, 0x00
-    .byte 0x12, 0x15, 0x36, 0x00
-    .byte 0x1b, 0x15, 0x36, 0x00
-    .byte 0x24, 0x15, 0x36, 0x00
-    .byte 0x2d, 0x15, 0x36, 0x00
-    .byte 0x36, 0x15, 0x36, 0x00
-    .byte 0x3f, 0x15, 0x36, 0x00
-    .byte 0x00, 0x2a, 0x36, 0x00
-    .byte 0x09, 0x2a, 0x36, 0x00
-    .byte 0x12, 0x2a, 0x36, 0x00
-    .byte 0x1b, 0x2a, 0x36, 0x00
-    .byte 0x24, 0x2a, 0x36, 0x00
-    .byte 0x2d, 0x2a, 0x36, 0x00
-    .byte 0x36, 0x2a, 0x36, 0x00
-    .byte 0x3f, 0x2a, 0x36, 0x00
-    .byte 0x00, 0x3f, 0x36, 0x00
-    .byte 0x09, 0x3f, 0x36, 0x00
-    .byte 0x12, 0x3f, 0x36, 0x00
-    .byte 0x1b, 0x3f, 0x36, 0x00
-    .byte 0x24, 0x3f, 0x36, 0x00
-    .byte 0x2d, 0x3f, 0x36, 0x00
-    .byte 0x36, 0x3f, 0x36, 0x00
-    .byte 0x3f, 0x3f, 0x36, 0x00
-    .byte 0x00, 0x00, 0x3f, 0x00
-    .byte 0x09, 0x00, 0x3f, 0x00
-    .byte 0x12, 0x00, 0x3f, 0x00
-    .byte 0x1b, 0x00, 0x3f, 0x00
-    .byte 0x24, 0x00, 0x3f, 0x00
-    .byte 0x2d, 0x00, 0x3f, 0x00
-    .byte 0x36, 0x00, 0x3f, 0x00
-    .byte 0x3f, 0x00, 0x3f, 0x00
-    .byte 0x00, 0x15, 0x3f, 0x00
-    .byte 0x09, 0x15, 0x3f, 0x00
-    .byte 0x12, 0x15, 0x3f, 0x00
-    .byte 0x1b, 0x15, 0x3f, 0x00
-    .byte 0x24, 0x15, 0x3f, 0x00
-    .byte 0x2d, 0x15, 0x3f, 0x00
-    .byte 0x36, 0x15, 0x3f, 0x00
-    .byte 0x3f, 0x15, 0x3f, 0x00
-    .byte 0x00, 0x2a, 0x3f, 0x00
-    .byte 0x09, 0x2a, 0x3f, 0x00
-    .byte 0x12, 0x2a, 0x3f, 0x00
-    .byte 0x1b, 0x2a, 0x3f, 0x00
-    .byte 0x24, 0x2a, 0x3f, 0x00
-    .byte 0x2d, 0x2a, 0x3f, 0x00
-    .byte 0x36, 0x2a, 0x3f, 0x00
-    .byte 0x3f, 0x2a, 0x3f, 0x00
-    .byte 0x00, 0x3f, 0x3f, 0x00
-    .byte 0x09, 0x3f, 0x3f, 0x00
-    .byte 0x12, 0x3f, 0x3f, 0x00
-    .byte 0x1b, 0x3f, 0x3f, 0x00
-    .byte 0x24, 0x3f, 0x3f, 0x00
-    .byte 0x2d, 0x3f, 0x3f, 0x00
-    .byte 0x36, 0x3f, 0x3f, 0x00
-    .byte 0x3f, 0x3f, 0x3f, 0x00

 /branches/network/kernel/arch/ia32/src/boot/vesa_ret.inc
 ,0 → 1,12
+.code32
+vesa_init_protected:
+    movw $gdtselector(KDATA_DES), %cx
+    movw %cx, %es
+    movw %cx, %fs
+    movw %cx, %gs
+    movw %cx, %ds               # kernel data + stack
+    movw %cx, %ss
+    movl $START_STACK, %esp     # initialize stack pointer
+    jmpl $gdtselector(KTEXT_DES), $vesa_meeting_point

 /branches/network/kernel/arch/ia32/src/boot/boot.S
 ,178 → 42,63
 multiboot_header:
     .long MULTIBOOT_HEADER_MAGIC
     .long MULTIBOOT_HEADER_FLAGS
-    .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)    # checksum
+    .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)  # checksum
     .long multiboot_header
     .long unmapped_ktext_start
     .long 0
     .long 0
     .long multiboot_image_start
 multiboot_image_start:
     cld
-    movl $START_STACK, %esp         # initialize stack pointer
-    lgdt KA2PA(bootstrap_gdtr)      # initialize Global Descriptor Table register
-    movw $selector(KDATA_DES), %cx
+    movl $START_STACK, %esp     # initialize stack pointer
+    lgdt KA2PA(bootstrap_gdtr)  # initialize Global Descriptor Table register
+    movw $gdtselector(KDATA_DES), %cx
     movw %cx, %es
     movw %cx, %fs
     movw %cx, %gs
-    movw %cx, %ds                   # kernel data + stack
+    movw %cx, %ds               # kernel data + stack
     movw %cx, %ss
-    jmpl $selector(KTEXT_DES), $multiboot_meeting_point
+    jmpl $gdtselector(KTEXT_DES), $multiboot_meeting_point
     multiboot_meeting_point:
-    movl %eax, grub_eax                 # save parameters from GRUB
+    movl %eax, grub_eax         # save parameters from GRUB
     movl %ebx, grub_ebx
-    xorl %eax, %eax
-    cpuid
-    cmp $0x0, %eax                      # any function > 0?
+    xorl %eax, %eax
+    cpuid
+    cmp $0x0, %eax              # any function > 0?
     jbe pse_unsupported
-    movl $0x1, %eax                     # Basic function code 1
+    movl $0x1, %eax             # basic function code 1
     cpuid
-    bt $3, %edx                         # Test if PSE is supported
+    bt $3, %edx                 # test if PSE is supported
     jc pse_supported
     pse_unsupported:
         movl $pse_msg, %esi
         jmp error_halt
     pse_supported:
-#ifdef CONFIG_FB
-    mov $vesa_init, %esi
-    mov $VESA_INIT_SEGMENT << 4, %edi
-    mov $e_vesa_init - vesa_init, %ecx
-    rep movsb
-    mov $VESA_INIT_SEGMENT << 4, %edi
-    jmpl *%edi
+#include "vesa_prot.inc"
+    # map kernel and turn paging on
+    call map_kernel
-    vesa_meeting_point:
+    # call arch_pre_main(grub_eax, grub_ebx)
+    pushl grub_ebx
+    pushl grub_eax
+    call arch_pre_main
-    mov %esi, KA2PA(vesa_ph_addr)
-    mov %di, KA2PA(vesa_height)
-    shr $16, %edi
-    mov %di, KA2PA(vesa_width)
-    mov %bx, KA2PA(vesa_scanline)
-    shr $16, %ebx
-    mov %bx, KA2PA(vesa_bpp)
-#endif
+    call main_bsp
-    call map_kernel                         # map kernel and turn paging on
-    movl grub_eax, %eax
-    movl grub_ebx, %ebx
-    cmpl $MULTIBOOT_LOADER_MAGIC, %eax              # compare GRUB signature
-    je valid_boot
-        xorl %ecx, %ecx                         # no memory map available
-        movl %ecx, e820counter
-        jmp invalid_boot
-    valid_boot:
-        movl (%ebx), %eax                       # ebx = physical address of struct multiboot_info
-        bt $3, %eax                             # mbi->flags[3] (mods_count, mods_addr valid)
-        jc mods_valid
-            xorl %ecx, %ecx
-            movl %ecx, init
-            jmp mods_end
-        mods_valid:
-        movl 20(%ebx), %ecx                     # mbi->mods_count
-        movl %ecx, init
-        cmpl $0, %ecx
-        je mods_end
-        movl 24(%ebx), %esi                     # mbi->mods_addr
-        movl $init, %edi
-        mods_loop:
-            movl 0(%esi), %edx                  # mods->mod_start
-            addl $0x80000000, %edx
-            movl %edx, 4(%edi)
-            movl 4(%esi), %edx
-            subl 0(%esi), %edx                  # mods->mod_end - mods->mod_start
-            movl %edx, 8(%edi)
-            addl $16, %esi
-            addl $8 , %edi
-            loop mods_loop
-        mods_end:
-        bt $6, %eax                             # mbi->flags[6] (mmap_length, mmap_addr valid)
-        jc mmap_valid
-            xorl %edx, %edx
-            jmp mmap_invalid
-        mmap_valid:
-        movl 44(%ebx), %ecx                     # mbi->mmap_length
-        movl 48(%ebx), %esi                     # mbi->mmap_addr
-        movl $e820table, %edi
-        xorl %edx, %edx
-        mmap_loop:
-            cmpl $0, %ecx
-            jle mmap_end
-            movl 4(%esi), %eax                  # mmap->base_addr_low
-            movl %eax, (%edi)
-            movl 8(%esi), %eax                  # mmap->base_addr_high
-            movl %eax, 4(%edi)
-            movl 12(%esi), %eax                 # mmap->length_low
-            movl %eax, 8(%edi)
-            movl 16(%esi), %eax                 # mmap->length_high
-            movl %eax, 12(%edi)
-            movl 20(%esi), %eax                 # mmap->type
-            movl %eax, 16(%edi)
-            movl (%esi), %eax                   # mmap->size
-            addl $0x4, %eax
-            addl %eax, %esi
-            subl %eax, %ecx
-            addl $MEMMAP_E820_RECORD_SIZE, %edi
-            incl %edx
-            jmp mmap_loop
-        mmap_end:
-        mmap_invalid:
-        movl %edx, e820counter
-    invalid_boot:
-#ifdef CONFIG_SMP
-    # copy AP bootstrap routines below 1 MB
-    movl $BOOT_OFFSET, %esi
-    movl $AP_BOOT_OFFSET, %edi
-    movl $_hardcoded_unmapped_size, %ecx
-    rep movsb
-#endif
-    call main_bsp                               # never returns
+    # not reached
     cli
-    hlt
+    hlt0:
+        hlt
+        jmp hlt0
 .global map_kernel
 map_kernel:
 ,8 → 107,8
     # For simplicity, we map the entire 4G space.
     #
     movl %cr4, %ecx
-    orl $(1 << 4), %ecx                         # turn PSE on
-    andl $(~(1 << 5)), %ecx                     # turn PAE off
+    orl $(1 << 4), %ecx                 # turn PSE on
+    andl $(~(1 << 5)), %ecx             # turn PAE off
     movl %ecx, %cr4
     movl $(page_directory + 0), %esi
 ,30 → 115,31
     movl $(page_directory + 2048), %edi
     xorl %ecx, %ecx
     xorl %ebx, %ebx
-:
-    movl $((1 << 7) | (1 << 1) | (1 << 0)), %eax
-    orl %ebx, %eax
-    movl %eax, (%esi, %ecx, 4)                  # mapping 0x00000000 + %ecx * 4M => 0x00000000 + %ecx * 4M
-    movl %eax, (%edi, %ecx, 4)                  # mapping 0x80000000 + %ecx * 4M => 0x00000000 + %ecx * 4M
-    addl $(4 * 1024 * 1024), %ebx
-    incl %ecx
-    cmpl $512, %ecx
-    jl 0b
+    floop:
+        movl $((1 << 7) | (1 << 1) | (1 << 0)), %eax
+        orl %ebx, %eax
+        movl %eax, (%esi, %ecx, 4)      # mapping 0x00000000 + %ecx * 4M => 0x00000000 + %ecx * 4M
+        movl %eax, (%edi, %ecx, 4)      # mapping 0x80000000 + %ecx * 4M => 0x00000000 + %ecx * 4M
+        addl $(4 * 1024 * 1024), %ebx
+        incl %ecx
+        cmpl $512, %ecx
+        jl floop
     movl %esi, %cr3
     movl %cr0, %ebx
-    orl $(1 << 31), %ebx                        # turn paging on
+    orl $(1 << 31), %ebx                # turn paging on
     movl %ebx, %cr0
     ret
 # Print string from %esi to EGA display (in red) and halt
 error_halt:
-    movl $0xb8000, %edi                     # base of EGA text mode memory
+    movl $0xb8000, %edi         # base of EGA text mode memory
     xorl %eax, %eax
-    movw $0x3d4, %dx                        # read bits 8 - 15 of the cursor address
+    movw $0x3d4, %dx            # read bits 8 - 15 of the cursor address
     movb $0xe, %al
     outb %al, %dx
 ,7 → 147,7
     inb %dx, %al
     shl $8, %ax
-    movw $0x3d4, %dx                        # read bits 0 - 7 of the cursor address
+    movw $0x3d4, %dx            # read bits 0 - 7 of the cursor address
     movb $0xf, %al
     outb %al, %dx
 ,7 → 156,9
     cmp $1920, %ax
     jbe cursor_ok
-        movw $1920, %ax                     # sanity check for the cursor on the last line
+        movw $1920, %ax         # sanity check for the cursor on the last line
     cursor_ok:
     movw %ax, %bx
 ,7 → 165,7
     shl $1, %eax
     addl %eax, %edi
-    movw $0x0c00, %ax                       # black background, light red foreground
+    movw $0x0c00, %ax           # black background, light red foreground
     ploop:
         lodsb
 ,11 → 172,11
         cmp $0, %al
         je ploop_end
         stosw
-        inc %bx
+        inc %bx
         jmp ploop
     ploop_end:
-    movw $0x3d4, %dx                        # write bits 8 - 15 of the cursor address
+    movw $0x3d4, %dx            # write bits 8 - 15 of the cursor address
     movb $0xe, %al
     outb %al, %dx
 ,7 → 184,7
     movb %bh, %al
     outb %al, %dx
-    movw $0x3d4, %dx                        # write bits 0 - 7 of the cursor address
+    movw $0x3d4, %dx            # write bits 0 - 7 of the cursor address
     movb $0xf, %al
     outb %al, %dx
 ,240 → 191,14
     movw $0x3d5, %dx
     movb %bl, %al
     outb %al, %dx
     cli
-    hlt
+    hlt1:
+        hlt
+        jmp hlt1
-#ifdef CONFIG_FB
-vesa_init:
-    jmp $selector(VESA_INIT_DES), $vesa_init_real - vesa_init
-.code16
-vesa_init_real:
-    mov %cr0, %eax
-    and $~1, %eax
-    mov %eax, %cr0
-    jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
-vesa_init_real2:
-    mov $VESA_INIT_SEGMENT, %bx
-    mov %bx, %es
-    mov %bx, %fs
-    mov %bx, %gs
-    mov %bx, %ds
-    mov %bx, %ss
-    movl %esp, %eax
-    movl $0x0000fffc, %esp
-    movl $0x0000fffc, %ebp
-    pushl %eax
-#define VESA_INFO_SIZE 1024
+#include "vesa_real.inc"
-#define VESA_MODE_ATTRIBUTES_OFFSET 0
-#define VESA_MODE_LIST_PTR_OFFSET 14
-#define VESA_MODE_SCANLINE_OFFSET 16
-#define VESA_MODE_WIDTH_OFFSET 18
-#define VESA_MODE_HEIGHT_OFFSET 20
-#define VESA_MODE_BPP_OFFSET 25
-#define VESA_MODE_PHADDR_OFFSET 40
-#define VESA_END_OF_MODES 0xffff
-#define VESA_OK 0x4f
-#define VESA_GET_INFO 0x4f00
-#define VESA_GET_MODE_INFO 0x4f01
-#define VESA_SET_MODE 0x4f02
-#define VESA_SET_PALETTE 0x4f09
-#if CONFIG_VESA_BPP == 24
-#define CONFIG_VESA_BPP_VARIANT 32
-#endif
-    mov $VESA_GET_INFO, %ax
-    mov $e_vesa_init - vesa_init, %di
-    push %di
-    int $0x10
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 0f
-    mov 2 + VESA_MODE_LIST_PTR_OFFSET(%di), %si
-    mov %si, %gs
-    mov VESA_MODE_LIST_PTR_OFFSET(%di), %si
-    add $VESA_INFO_SIZE, %di
-:# Try next mode
-    mov %gs:(%si), %cx
-    cmp $VESA_END_OF_MODES, %cx
-    jz 0f
-    inc %si
-    inc %si
-    push %cx
-    push %di
-    push %si
-    mov $VESA_GET_MODE_INFO, %ax
-    int $0x10
-    pop %si
-    pop %di
-    pop %cx
-    cmp $VESA_OK, %al
-    jnz 0f
-    mov $CONFIG_VESA_WIDTH, %ax
-    cmp VESA_MODE_WIDTH_OFFSET(%di), %ax
-    jnz 1b
-    mov $CONFIG_VESA_HEIGHT, %ax
-    cmp VESA_MODE_HEIGHT_OFFSET(%di), %ax
-    jnz 1b
-    mov $CONFIG_VESA_BPP, %al
-    cmp VESA_MODE_BPP_OFFSET(%di), %al
-#ifdef CONFIG_VESA_BPP_VARIANT
-    jz 2f
-    mov $CONFIG_VESA_BPP_VARIANT, %al
-    cmp VESA_MODE_BPP_OFFSET(%di), %al
-#endif
-    jnz 1b
-:
-    mov %cx, %bx
-    or $0xc000, %bx
-    push %di
-    mov $VESA_SET_MODE, %ax
-    int $0x10
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 0f
-#if CONFIG_VESA_BPP == 8
-    # Set 3:2:3 VGA palette
-    mov VESA_MODE_ATTRIBUTES_OFFSET(%di), %ax
-    push %di
-    mov $vga323 - vesa_init, %di
-    mov $0x100, %ecx
-    bt $5, %ax                          # Test if VGA compatible registers are present
-    jnc vga_compat
-        # Try VESA routine to set palette
-        mov $VESA_SET_PALETTE, %ax
-        xor %bl, %bl
-        xor %dx, %dx
-        int $0x10
-        jmp vga_not_compat
-    vga_compat:
-        # Try VGA registers to set palette
-        movw $0x3c6, %dx                        # Set palette mask
-        movb $0xff, %al
-        outb %al, %dx
-        movw $0x3c8, %dx                        # First index to set
-        xor %al, %al
-        outb %al, %dx
-        movw $0x3c9, %dx                        # Data port
-        vga_loop:
-            movb %es:2(%di), %al
-            outb %al, %dx
-            movb %es:1(%di), %al
-            outb %al, %dx
-            movb %es:(%di), %al
-            outb %al, %dx
-            addw $4, %di
-            loop vga_loop
-    vga_not_compat:
-    pop %di
-#endif
-    mov VESA_MODE_PHADDR_OFFSET(%di), %esi
-    mov VESA_MODE_WIDTH_OFFSET(%di), %ax
-    shl $16, %eax
-    mov VESA_MODE_HEIGHT_OFFSET(%di), %ax
-    mov VESA_MODE_BPP_OFFSET(%di), %bl
-    xor %bh, %bh
-    shl $16, %ebx
-    mov VESA_MODE_SCANLINE_OFFSET(%di), %bx
-    mov %eax, %edi
-:
-    mov %cr0, %eax
-    or $1, %eax
-    mov %eax, %cr0
-    jmp 9f
-:
-    ljmpl $selector(KTEXT_DES), $(vesa_init_protect - vesa_init + VESA_INIT_SEGMENT << 4)
-:# No prefered mode found
-    mov $0x111, %cx
-    push %di
-    push %cx
-    mov $VESA_GET_MODE_INFO, %ax
-    int $0x10
-    pop %cx
-    pop %di
-    cmp $VESA_OK, %al
-    jnz 1f
-    jz 2b                       # Force relative jump
-:
-    mov $0x0003, %ax
-    int $0x10
-    mov $0xffffffff, %edi       # EGA text mode used, because of problems with VESA
-    xor %ax, %ax
-    jz 8b                       # Force relative jump
-vga323:
-#include "vga323.pal"
-.code32
-vesa_init_protect:
-    movw $selector(KDATA_DES), %cx
-    movw %cx, %es
-    movw %cx, %fs
-    movw %cx, %gs
-    movw %cx, %ds                   # kernel data + stack
-    movw %cx, %ss
-    movl $START_STACK, %esp         # initialize stack pointer
-    jmpl $selector(KTEXT_DES), $vesa_meeting_point
-.align 4
-e_vesa_init:
-#endif
 .section K_DATA_START, "aw", @progbits
 .align 4096

 /branches/network/kernel/arch/ia32/src/boot/vesa_real.inc
 ,0 → 1,373
+#ifdef CONFIG_FB
+#include <macros.h>
+#define VESA_INFO_SIZE 1024
+#define VESA_MODE_ATTRIBUTES_OFFSET  0
+#define VESA_MODE_LIST_PTR_OFFSET    14
+#define VESA_MODE_SCANLINE_OFFSET    16
+#define VESA_MODE_WIDTH_OFFSET       18
+#define VESA_MODE_HEIGHT_OFFSET      20
+#define VESA_MODE_BPP_OFFSET         25
+#define VESA_MODE_RED_MASK_OFFSET    31
+#define VESA_MODE_RED_POS_OFFSET     32
+#define VESA_MODE_GREEN_MASK_OFFSET  33
+#define VESA_MODE_GREEN_POS_OFFSET   34
+#define VESA_MODE_BLUE_MASK_OFFSET   35
+#define VESA_MODE_BLUE_POS_OFFSET    36
+#define VESA_MODE_PHADDR_OFFSET      40
+#define VESA_END_OF_MODES  0xffff
+#define VESA_OK  0x4f
+#define VESA_GET_INFO       0x4f00
+#define VESA_GET_MODE_INFO  0x4f01
+#define VESA_SET_MODE       0x4f02
+#define VESA_SET_PALETTE    0x4f09
+.code32
+vesa_init:
+    jmp $gdtselector(VESA_INIT_DES), $vesa_init_real - vesa_init
+.code16
+vesa_init_real:
+    mov %cr0, %eax
+    and $~1, %eax
+    mov %eax, %cr0
+    jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
+vesa_init_real2:
+    mov $VESA_INIT_SEGMENT, %bx
+    mov %bx, %es
+    mov %bx, %fs
+    mov %bx, %gs
+    mov %bx, %ds
+    mov %bx, %ss
+    movl %esp, %eax
+    movl $0x0000fffc, %esp
+    movl $0x0000fffc, %ebp
+    pushl %eax
+    # parse default mode string
+    mov $default_mode - vesa_init, %di
+    xor %eax, %eax
+    xor %ebx, %ebx
+    mov $8, %ecx
+    parse_width:
+        mov (%di), %al
+        # check for digit
+        cmp $'0', %al
+        jb parse_width_done
+        cmp $'9', %al
+        ja parse_width_done
+        sub $'0', %al
+        # multiply default_width by 10 and add digit
+        mov default_width - vesa_init, %bx
+        lea (%ebx, %ebx, 4), %ebx
+        shl $1, %ebx
+        add %ax, %bx
+        mov %bx, default_width - vesa_init
+        inc %di
+        loop parse_width
+    parse_width_done:
+    mov (%di), %al
+    cmp $0, %al
+    jz parse_done
+    inc %di
+    mov $8, %ecx
+    parse_height:
+        mov (%di), %al
+        # check for digit
+        cmp $'0', %al
+        jb parse_height_done
+        cmp $'9', %al
+        ja parse_height_done
+        sub $'0', %al
+        # multiply default_height by 10 and add digit
+        mov default_height - vesa_init, %bx
+        lea (%ebx, %ebx, 4), %ebx
+        shl $1, %ebx
+        add %ax, %bx
+        mov %bx, default_height - vesa_init
+        inc %di
+        loop parse_height
+    parse_height_done:
+    mov (%di), %al
+    cmp $0, %al
+    jz parse_done
+    inc %di
+    mov $4, %ecx
+    parse_bpp:
+        mov (%di), %al
+        # check for digit
+        cmp $'0', %al
+        jb parse_bpp_done
+        cmp $'9', %al
+        ja parse_bpp_done
+        sub $'0', %al
+        # multiply default_bpp by 10 and add digit
+        mov default_bpp - vesa_init, %bx
+        lea (%ebx, %ebx, 4), %ebx
+        shl $1, %ebx
+        add %ax, %bx
+        mov %bx, default_bpp - vesa_init
+        inc %di
+        loop parse_bpp
+    parse_bpp_done:
+    parse_done:
+    mov $VESA_GET_INFO, %ax
+    mov $e_vesa_init - vesa_init, %di
+    push %di
+    int $0x10
+    pop %di
+    cmp $VESA_OK, %al
+    jnz no_mode
+    mov 2 + VESA_MODE_LIST_PTR_OFFSET(%di), %si
+    mov %si, %gs
+    mov VESA_MODE_LIST_PTR_OFFSET(%di), %si
+    add $VESA_INFO_SIZE, %di
+    next_mode:
+        # try next mode
+        mov %gs:(%si), %cx
+        cmp $VESA_END_OF_MODES, %cx
+        je no_mode
+        inc %si
+        inc %si
+        push %cx
+        push %di
+        push %si
+        mov $VESA_GET_MODE_INFO, %ax
+        int $0x10
+        pop %si
+        pop %di
+        pop %cx
+        cmp $VESA_OK, %al
+        jne no_mode
+        # check for proper attributes (supported, color, graphics, linear framebuffer)
+        mov VESA_MODE_ATTRIBUTES_OFFSET(%di), %ax
+        and $0x99, %ax
+        cmp $0x99, %ax
+        jne next_mode
+        # check for proper resolution
+        mov default_width - vesa_init, %ax
+        cmp VESA_MODE_WIDTH_OFFSET(%di), %ax
+        jne next_mode
+        mov default_height - vesa_init, %ax
+        cmp VESA_MODE_HEIGHT_OFFSET(%di), %ax
+        jne next_mode
+        # check for proper bpp
+        mov default_bpp - vesa_init, %al
+        cmp VESA_MODE_BPP_OFFSET(%di), %al
+        je set_mode
+        mov $24, %al
+        cmp default_bpp - vesa_init, %al
+        jne next_mode
+        # for 24 bpp modes accept also 32 bit bpp
+        mov $32, %al
+        cmp VESA_MODE_BPP_OFFSET(%di), %al
+        jne next_mode
+    set_mode:
+        mov %cx, %bx
+        or $0xc000, %bx
+        push %di
+        mov $VESA_SET_MODE, %ax
+        int $0x10
+        pop %di
+        cmp $VESA_OK, %al
+        jnz no_mode
+        # set 3:2:3 VGA palette
+        mov VESA_MODE_BPP_OFFSET(%di), %al
+        cmp $8, %al
+        jnz vga_not_set
+        mov VESA_MODE_ATTRIBUTES_OFFSET(%di), %ax
+        push %di
+        mov $vga323 - vesa_init, %di
+        mov $0x100, %ecx
+        bt $5, %ax              # test if VGA compatible registers are present
+        jnc vga_compat
+            # try VESA routine to set palette
+            mov $VESA_SET_PALETTE, %ax
+            xor %bl, %bl
+            xor %dx, %dx
+            int $0x10
+            cmp $0x00, %ah
+            je vga_not_compat
+        vga_compat:
+            # try VGA registers to set palette
+            movw $0x3c6, %dx    # set palette mask
+            movb $0xff, %al
+            outb %al, %dx
+            movw $0x3c8, %dx    # first index to set
+            xor %al, %al
+            outb %al, %dx
+            movw $0x3c9, %dx    # data port
+            vga_loop:
+                movb %es:2(%di), %al
+                outb %al, %dx
+                movb %es:1(%di), %al
+                outb %al, %dx
+                movb %es:(%di), %al
+                outb %al, %dx
+                addw $4, %di
+            loop vga_loop
+        vga_not_compat:
+            pop %di
+        vga_not_set:
+        # store mode parameters
+        #  eax = bpp[8] scanline[16]
+        #  ebx = width[16]  height[16]
+        #  edx = red_mask[8] red_pos[8] green_mask[8] green_pos[8]
+        #  esi = blue_mask[8] blue_pos[8]
+        #  edi = linear frame buffer
+        mov VESA_MODE_BPP_OFFSET(%di), %al
+        xor %ah, %ah
+        shl $16, %eax
+        mov VESA_MODE_SCANLINE_OFFSET(%di), %ax
+        mov VESA_MODE_WIDTH_OFFSET(%di), %bx
+        shl $16, %ebx
+        mov VESA_MODE_HEIGHT_OFFSET(%di), %bx
+        mov VESA_MODE_BLUE_MASK_OFFSET(%di), %dl
+        shl $8, %edx
+        mov VESA_MODE_BLUE_POS_OFFSET(%di), %dl
+        mov %edx, %esi
+        mov VESA_MODE_RED_MASK_OFFSET(%di), %dl
+        shl $8, %edx
+        mov VESA_MODE_RED_POS_OFFSET(%di), %dl
+        shl $8, %edx
+        mov VESA_MODE_GREEN_MASK_OFFSET(%di), %dl
+        shl $8, %edx
+        mov VESA_MODE_GREEN_POS_OFFSET(%di), %dl
+        mov VESA_MODE_PHADDR_OFFSET(%di), %edi
+        vesa_leave_real:
+            mov %cr0, %ecx
+            or $1, %ecx
+            mov %ecx, %cr0
+            jmp vesa_leave_real2
+        vesa_leave_real2:
+            ljmpl $gdtselector(KTEXT32_DES), $(vesa_init_protected - vesa_init + VESA_INIT_SEGMENT << 4)
+    no_mode:
+        # no prefered mode found
+        mov $0x111, %cx
+        push %di
+        push %cx
+        mov $VESA_GET_MODE_INFO, %ax
+        int $0x10
+        pop %cx
+        pop %di
+        cmp $VESA_OK, %al
+        jnz text_mode
+        jz set_mode             # force relative jump
+    text_mode:
+        # reset to EGA text mode (because of problems with VESA)
+        mov $0x0003, %ax
+        int $0x10
+        mov $0xffffffff, %edi
+        xor %ax, %ax
+        jz vesa_leave_real      # force relative jump
+vga323:
+#include "vga323.pal"
+default_width:
+    .word 0
+default_height:
+    .word 0
+default_bpp:
+    .byte 0
+default_mode:
+    .ascii STRING(CONFIG_VESA_MODE)
+    .ascii "-"
+    .asciz STRING(CONFIG_VESA_BPP)
+    .fill 24
+#include "vesa_ret.inc"
+.align 4
+e_vesa_init:
+#endif

 /branches/network/kernel/arch/ia32/src/boot/vesa_prot.inc
 ,0 → 1,107
+#ifdef CONFIG_FB
+#define MULTIBOOT_LOADER_MAGIC  0x2BADB002
+#define MBINFO_BIT_CMDLINE      2
+#define MBINFO_OFFSET_CMDLINE   16
+    # copy real mode VESA initialization code
+    mov $vesa_init, %esi
+    mov $VESA_INIT_SEGMENT << 4, %edi
+    mov $e_vesa_init - vesa_init, %ecx
+    rep movsb
+    # check for GRUB command line
+    mov grub_eax, %eax
+    cmp $MULTIBOOT_LOADER_MAGIC, %eax
+    jne no_cmdline
+    mov grub_ebx, %ebx
+    mov (%ebx), %eax
+    bt $MBINFO_BIT_CMDLINE, %eax
+    jnc no_cmdline
+    # skip the kernel path in command line
+    mov MBINFO_OFFSET_CMDLINE(%ebx), %esi
+    skip_loop:
+        lodsb
+        cmp $0, %al
+        je no_cmdline
+        cmp $' ', %al
+        je skip_loop_done
+        jmp skip_loop
+    skip_loop_done:
+    space_loop:
+        mov (%esi), %al
+        cmp $0, %al
+        je no_cmdline
+        cmp $' ', %al
+        jne space_loop_done
+        inc %esi
+        jmp space_loop
+    space_loop_done:
+    # copy at most 23 characters from command line
+    mov $VESA_INIT_SEGMENT << 4, %edi
+    add $default_mode - vesa_init, %edi
+    mov $23, %ecx
+    cmd_loop:
+        lodsb
+        stosb
+        cmp $0, %al
+        je cmd_loop_done
+        loop cmd_loop
+    cmd_loop_done:
+    # zero termination
+    xor %eax, %eax
+    stosb
+    no_cmdline:
+    # jump to the real mode
+    mov $VESA_INIT_SEGMENT << 4, %edi
+    jmpl *%edi
+    vesa_meeting_point:
+        # returned back to protected mode
+        mov %ax, KA2PA(vesa_scanline)
+        shr $16, %eax
+        mov %ax, KA2PA(vesa_bpp)
+        mov %bx, KA2PA(vesa_height)
+        shr $16, %ebx
+        mov %bx, KA2PA(vesa_width)
+        mov %dl, KA2PA(vesa_green_pos)
+        shr $8, %edx
+        mov %dl, KA2PA(vesa_green_mask)
+        shr $8, %edx
+        mov %dl, KA2PA(vesa_red_pos)
+        shr $8, %edx
+        mov %dl, KA2PA(vesa_red_mask)
+        mov %esi, %edx
+        mov %dl, KA2PA(vesa_blue_pos)
+        shr $8, %edx
+        mov %dl, KA2PA(vesa_blue_mask)
+        mov %edi, KA2PA(vesa_ph_addr)
+#endif

 /branches/network/kernel/arch/ia32/src/proc/scheduler.c
 ,7 → 38,6
 #include <proc/thread.h>
 #include <arch.h>
 #include <arch/context.h>   /* SP_DELTA */
-#include <arch/debugger.h>
 #include <arch/pm.h>
 #include <arch/asm.h>
 #include <arch/ddi/ddi.h>
 ,21 → 57,18
  */
 void before_thread_runs_arch(void)
 {
-    CPU->arch.tss->esp0 = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
+    uintptr_t kstk = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
         SP_DELTA];
-    CPU->arch.tss->ss0 = selector(KDATA_DES);
+    /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
+    write_msr(IA32_MSR_SYSENTER_ESP, kstk);
+    /* Set kernel stack for CPL3 -> CPL0 switch via interrupt */
+    CPU->arch.tss->esp0 = kstk;
+    CPU->arch.tss->ss0 = gdtselector(KDATA_DES);
     /* Set up TLS in GS register */
     set_tls_desc(THREAD->arch.tls);
-#ifdef CONFIG_DEBUG_AS_WATCHPOINT
-    /* Set watchpoint on AS to ensure that nobody sets it to zero */
-    if (CPU->id < BKPOINTS_MAX) {
-        the_t *the = THE;
-        breakpoint_add(&((the_t *) the->thread->kstack)->as,
-            BKPOINT_WRITE | BKPOINT_CHECK_ZERO, the->cpu->id);
-    }
-#endif
 }
 void after_thread_ran_arch(void)

 /branches/network/kernel/arch/ia32/src/mm/tlb.c
 ,5 → 67,13
         invlpg(page + i * PAGE_SIZE);
 }
+void tlb_arch_init(void)
+{
+}
+void tlb_print(void)
+{
+}
 /** @}
  */

 /branches/network/kernel/arch/ia32/src/mm/frame.c
 ,26 → 54,57
 static void init_e820_memory(pfn_t minconf)
 {
     unsigned int i;
-    pfn_t start, conf;
-    size_t size;
     for (i = 0; i < e820counter; i++) {
+        uint64_t base = e820table[i].base_address;
+        uint64_t size = e820table[i].size;
+#ifdef __32_BITS__
+        /* Ignore physical memory above 4 GB */
+        if ((base >> 32) != 0)
+            continue;
+        /* Clip regions above 4 GB */
+        if (((base + size) >> 32) != 0)
+            size = 0xffffffff - base;
+#endif
+        pfn_t pfn;
+        count_t count;
         if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) {
-            start = ADDR2PFN(ALIGN_UP(e820table[i].base_address, FRAME_SIZE));
-            size = SIZE2FRAMES(ALIGN_DOWN(e820table[i].size, FRAME_SIZE));
+            /* To be safe, make available zone possibly smaller */
+            pfn = ADDR2PFN(ALIGN_UP(base, FRAME_SIZE));
+            count = SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE));
-            if ((minconf < start) || (minconf >= start + size))
-                conf = start;
+            pfn_t conf;
+            if ((minconf < pfn) || (minconf >= pfn + count))
+                conf = pfn;
             else
                 conf = minconf;
-            zone_create(start, size, conf, 0);
+            zone_create(pfn, count, conf, ZONE_AVAILABLE);
-            if (last_frame < ALIGN_UP(e820table[i].base_address +
-                e820table[i].size, FRAME_SIZE))
-                last_frame =
-                    ALIGN_UP(e820table[i].base_address + e820table[i].size, FRAME_SIZE);
-        }
+            // XXX this has to be removed
+            if (last_frame < ALIGN_UP(base + size, FRAME_SIZE))
+                last_frame = ALIGN_UP(base + size, FRAME_SIZE);
+        }
+        if (e820table[i].type == MEMMAP_MEMORY_RESERVED) {
+            /* To be safe, make reserved zone possibly larger */
+            pfn = ADDR2PFN(ALIGN_DOWN(base, FRAME_SIZE));
+            count = SIZE2FRAMES(ALIGN_UP(size, FRAME_SIZE));
+            zone_create(pfn, count, 0, ZONE_RESERVED);
+        }
+        if (e820table[i].type == MEMMAP_MEMORY_ACPI) {
+            /* To be safe, make firmware zone possibly larger */
+            pfn = ADDR2PFN(ALIGN_DOWN(base, (uintptr_t) FRAME_SIZE));
+            count = SIZE2FRAMES(ALIGN_UP(size, (uintptr_t) FRAME_SIZE));
+            zone_create(pfn, count, 0, ZONE_FIRMWARE);
+        }
     }
 }
 ,16 → 144,14
     if (config.cpu_active == 1) {
         minconf = 1;
 #ifdef CONFIG_SMP
         minconf = max(minconf,
             ADDR2PFN(AP_BOOT_OFFSET + hardcoded_unmapped_ktext_size +
             hardcoded_unmapped_kdata_size));
 #endif
-#ifdef CONFIG_SIMICS_FIX
-        minconf = max(minconf, ADDR2PFN(0x10000));
-#endif
         init_e820_memory(minconf);
         /* Reserve frame 0 (BIOS data) */
         frame_mark_unavailable(0, 1);
 ,12 → 160,7
         frame_mark_unavailable(AP_BOOT_OFFSET >> FRAME_WIDTH,
             (hardcoded_unmapped_ktext_size +
             hardcoded_unmapped_kdata_size) >> FRAME_WIDTH);
-#ifdef CONFIG_SIMICS_FIX
-        /* Don't know why, but these addresses help */
-        frame_mark_unavailable(0xd000 >> FRAME_WIDTH, 3);
 #endif
-#endif
     }
 }

 /branches/network/kernel/arch/ia32/src/mm/page.c
 ,7 → 53,7
 {
     uintptr_t cur;
     int flags;
     if (config.cpu_active == 1) {
         page_mapping_operations = &pt_mapping_operations;
 ,12 → 66,12
                 flags |= PAGE_GLOBAL;
             page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
         }
         exc_register(14, "page_fault", (iroutine) page_fault);
         write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
     } else
         write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
     paging_on();
 }
 ,7 → 79,7
 uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
     if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
-        panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
+        panic("Unable to map physical memory %p (%d bytes).", physaddr, size)
     uintptr_t virtaddr = PA2KA(last_frame);
     pfn_t i;
 ,8 → 101,8
     page = read_cr2();
     if (istate->error_word & PFERR_CODE_RSVD)
-        panic("Reserved bit set in page directory.\n");
+        panic("Reserved bit set in page directory.");
     if (istate->error_word & PFERR_CODE_RW)
         access = PF_ACCESS_WRITE;
     else
 ,11 → 109,11
         access = PF_ACCESS_READ;
     if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
-        fault_if_from_uspace(istate, "Page fault: %#x", page);
+        fault_if_from_uspace(istate, "Page fault: %#x.", page);
         decode_istate(istate);
         printf("page fault address: %#lx\n", page);
-        panic("page fault\n");
+        panic("Page fault.");
     }
 }

 /branches/network/kernel/arch/ia32/src/userspace.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /** @file
 ,10 → 47,8
  */
 void userspace(uspace_arg_t *kernel_uarg)
 {
-    ipl_t ipl;
-    ipl = interrupts_disable();
+    ipl_t ipl = interrupts_disable();
     asm volatile (
         /*
          * Clear nested task flag.
 ,35 → 58,33
         "and $0xffffbfff, %%eax\n"
         "push %%eax\n"
         "popfl\n"
         /* Set up GS register (TLS) */
-        "movl %6, %%gs\n"
-        "pushl %0\n"
-        "pushl %1\n"
-        "pushl %2\n"
-        "pushl %3\n"
-        "pushl %4\n"
-        "movl %5, %%eax\n"
+        "movl %[tls_des], %%gs\n"
+        "pushl %[udata_des]\n"
+        "pushl %[stack_size]\n"
+        "pushl %[ipl]\n"
+        "pushl %[utext_des]\n"
+        "pushl %[entry]\n"
+        "movl %[uarg], %%eax\n"
         /* %ebx is defined to hold pcb_ptr - set it to 0 */
-        "xorl %%ebx, %%ebx\n"
+        "xorl %%ebx, %%ebx\n"
         "iret\n"
-        :
-        : "i" (selector(UDATA_DES) | PL_USER),
-          "r" ((uint8_t *) kernel_uarg->uspace_stack +
-              THREAD_STACK_SIZE),
-          "r" (ipl),
-          "i" (selector(UTEXT_DES) | PL_USER),
-          "r" (kernel_uarg->uspace_entry),
-          "r" (kernel_uarg->uspace_uarg),
-          "r" (selector(TLS_DES))
+        :
+        : [udata_des] "i" (gdtselector(UDATA_DES) | PL_USER),
+          [stack_size] "r" ((uint8_t *) kernel_uarg->uspace_stack + THREAD_STACK_SIZE),
+          [ipl] "r" (ipl),
+          [utext_des] "i" (gdtselector(UTEXT_DES) | PL_USER),
+          [entry] "r" (kernel_uarg->uspace_entry),
+          [uarg] "r" (kernel_uarg->uspace_uarg),
+          [tls_des] "r" (gdtselector(TLS_DES))
         : "eax");
     /* Unreachable */
-    for(;;)
-        ;
+    while (1);
 }
 /** @}

 /branches/network/kernel/arch/ia32/src/interrupt.c
 ,7 → 44,6
 #include <mm/tlb.h>
 #include <mm/as.h>
 #include <arch.h>
-#include <symtab.h>
 #include <proc/thread.h>
 #include <proc/task.h>
 #include <synch/spinlock.h>
 ,6 → 51,7
 #include <ipc/sysipc.h>
 #include <interrupt.h>
 #include <ddi/irq.h>
+#include <symtab.h>
 /*
  * Interrupt and exception dispatching.
 ,10 → 63,9
 void decode_istate(istate_t *istate)
 {
-    char *symbol = get_symtab_entry(istate->eip);
+    char *symbol;
-    if (!symbol)
-        symbol = "";
+    symbol = symtab_fmt_name_lookup(istate->eip);
     if (CPU)
         printf("----------------EXCEPTION OCCURED (cpu%u)----------------\n", CPU->id);
 ,9 → 76,6
     printf("ERROR_WORD=%#lx\n", istate->error_word);
     printf("%%cs=%#lx,flags=%#lx\n", istate->cs, istate->eflags);
     printf("%%eax=%#lx, %%ecx=%#lx, %%edx=%#lx, %%esp=%p\n", istate->eax, istate->ecx, istate->edx, &istate->stack[0]);
-#ifdef CONFIG_DEBUG_ALLREGS
-    printf("%%esi=%#lx, %%edi=%#lx, %%ebp=%#lx, %%ebx=%#lx\n", istate->esi, istate->edi, istate->ebp, istate->ebx);
-#endif
     printf("stack: %#lx, %#lx, %#lx, %#lx\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]);
     printf("       %#lx, %#lx, %#lx, %#lx\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]);
 }
 ,16 → 85,16
     if (eoi_function)
         eoi_function();
     else
-        panic("no eoi_function\n");
+        panic("No eoi_function.");
 }
 static void null_interrupt(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "unserviced interrupt: %d", n);
+    fault_if_from_uspace(istate, "Unserviced interrupt: %d.", n);
     decode_istate(istate);
-    panic("unserviced interrupt: %d\n", n);
+    panic("Unserviced interrupt: %d.", n);
 }
 /** General Protection Fault. */
 ,19 → 118,19
             io_perm_bitmap_install();
             return;
         }
-        fault_if_from_uspace(istate, "general protection fault");
+        fault_if_from_uspace(istate, "General protection fault.");
     }
     decode_istate(istate);
-    panic("general protection fault\n");
+    panic("General protection fault.");
 }
 static void ss_fault(int n __attribute__((unused)), istate_t *istate)
 {
-    fault_if_from_uspace(istate, "stack fault");
+    fault_if_from_uspace(istate, "Stack fault.");
     decode_istate(istate);
-    panic("stack fault\n");
+    panic("Stack fault.");
 }
 static void simd_fp_exception(int n __attribute__((unused)), istate_t *istate)
 ,15 → 137,15
 {
     uint32_t mxcsr;
     asm (
-        "stmxcsr %0;\n"
-        : "=m" (mxcsr)
+        "stmxcsr %[mxcsr]\n"
+        : [mxcsr] "=m" (mxcsr)
     );
-    fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx",
+    fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.",
         (unative_t) mxcsr);
     decode_istate(istate);
     printf("MXCSR: %#lx\n", mxcsr);
-    panic("SIMD FP exception(19)\n");
+    panic("SIMD FP exception(19).");
 }
 static void nm_fault(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))
 ,8 → 153,8
 #ifdef CONFIG_FPU_LAZY
     scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "fpu fault");
-    panic("fpu fault");
+    fault_if_from_uspace(istate, "FPU fault.");
+    panic("FPU fault.");
 #endif
 }
 ,7 → 187,7
             trap_virtual_eoi();
             ack = true;
         }
-        irq->handler(irq, irq->arg);
+        irq->handler(irq);
         spinlock_unlock(&irq->lock);
     } else {
         /*
 ,7 → 229,7
     if (enable_irqs_function)
         enable_irqs_function(irqmask);
     else
-        panic("no enable_irqs_function\n");
+        panic("No enable_irqs_function.");
 }
 void trap_virtual_disable_irqs(uint16_t irqmask)
 ,7 → 237,7
     if (disable_irqs_function)
         disable_irqs_function(irqmask);
     else
-        panic("no disable_irqs_function\n");
+        panic("No disable_irqs_function.");
 }
 /** @}

 /branches/network/kernel/arch/ia32/src/drivers/vesa.c
 ,12 → 56,20
 uint16_t vesa_bpp;
 uint16_t vesa_scanline;
+uint8_t vesa_red_mask;
+uint8_t vesa_red_pos;
+uint8_t vesa_green_mask;
+uint8_t vesa_green_pos;
+uint8_t vesa_blue_mask;
+uint8_t vesa_blue_pos;
 int vesa_present(void)
 {
-    if (vesa_width != 0xffff)
+    if ((vesa_width != 0xffff) && (vesa_height != 0xffff))
         return true;
-    if (vesa_height != 0xffff)
-        return true;
     return false;
 }
 ,7 → 82,12
         visual = VISUAL_INDIRECT_8;
         break;
     case 16:
-        visual = VISUAL_RGB_5_6_5;
+        if ((vesa_red_mask == 5) && (vesa_red_pos == 10)
+            && (vesa_green_mask == 5) && (vesa_green_pos == 5)
+            && (vesa_blue_mask == 5) && (vesa_blue_pos == 0))
+            visual = VISUAL_RGB_5_5_5;
+        else
+            visual = VISUAL_RGB_5_6_5;
         break;
     case 24:
         visual = VISUAL_RGB_8_8_8;
 ,12 → 96,25
         visual = VISUAL_RGB_0_8_8_8;
         break;
     default:
-        panic("Unsupported bits per pixel");
+        panic("Unsupported bits per pixel.");
     }
-    fb_init(vesa_ph_addr, vesa_width, vesa_height, vesa_scanline, visual);
+    fb_properties_t vesa_props = {
+        .addr = vesa_ph_addr,
+        .offset = 0,
+        .x = vesa_width,
+        .y = vesa_height,
+        .scan = vesa_scanline,
+        .visual = visual,
+    };
+    fb_init(&vesa_props);
 }
+void vesa_redraw(void)
+{
+    fb_redraw();
+}
 #endif
 /** @}

 /branches/network/kernel/arch/ia32/src/drivers/i8259.c
 ,28 → 49,28
 void i8259_init(void)
 {
     /* ICW1: this is ICW1, ICW4 to follow */
-    outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
+    pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
     /* ICW2: IRQ 0 maps to INT IRQBASE */
-    outb(PIC_PIC0PORT2, IVT_IRQBASE);
+    pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
     /* ICW3: pic1 using IRQ IRQ_PIC1 */
-    outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
+    pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
     /* ICW4: i8086 mode */
-    outb(PIC_PIC0PORT2, 1);
+    pio_write_8(PIC_PIC0PORT2, 1);
     /* ICW1: ICW1, ICW4 to follow */
-    outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
+    pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
     /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
-    outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
+    pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
     /* ICW3: pic1 is known as IRQ_PIC1 */
-    outb(PIC_PIC1PORT2, IRQ_PIC1);
+    pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
     /* ICW4: i8086 mode */
-    outb(PIC_PIC1PORT2, 1);
+    pio_write_8(PIC_PIC1PORT2, 1);
     /*
      * Register interrupt handler for the PIC spurious interrupt.
 ,12 → 94,12
     uint8_t x;
     if (irqmask & 0xff) {
-        x = inb(PIC_PIC0PORT2);
-        outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
+        x = pio_read_8(PIC_PIC0PORT2);
+        pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
     }
     if (irqmask >> 8) {
-        x = inb(PIC_PIC1PORT2);
-        outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
+        x = pio_read_8(PIC_PIC1PORT2);
+        pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
     }
 }
 ,19 → 108,19
     uint8_t x;
     if (irqmask & 0xff) {
-        x = inb(PIC_PIC0PORT2);
-        outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
+        x = pio_read_8(PIC_PIC0PORT2);
+        pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
     }
     if (irqmask >> 8) {
-        x = inb(PIC_PIC1PORT2);
-        outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
+        x = pio_read_8(PIC_PIC1PORT2);
+        pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
     }
 }
 void pic_eoi(void)
 {
-    outb(0x20, 0x20);
-    outb(0xa0, 0x20);
+    pio_write_8((ioport8_t *)0x20, 0x20);
+    pio_write_8((ioport8_t *)0xa0, 0x20);
 }
 void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))

 /branches/network/kernel/arch/ia32/src/drivers/i8254.c
 ,12 → 26,12
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup ia32
+/** @addtogroup ia32
  * @{
  */
 /**
  * @file
- * @brief   i8254 chip driver.
+ * @brief i8254 chip driver.
  *
  * Low level time functions.
  */
 ,8 → 53,8
 #include <ddi/irq.h>
 #include <ddi/device.h>
-#define CLK_PORT1   0x40
-#define CLK_PORT4   0x43
+#define CLK_PORT1   ((ioport8_t *)0x40)
+#define CLK_PORT4   ((ioport8_t *)0x43)
 #define CLK_CONST   1193180
 #define MAGIC_NUMBER    1194
 ,12 → 61,12
 static irq_t i8254_irq;
-static irq_ownership_t i8254_claim(void)
+static irq_ownership_t i8254_claim(irq_t *irq)
 {
     return IRQ_ACCEPT;
 }
-static void i8254_irq_handler(irq_t *irq, void *arg __attribute__((unused)), ...)
+static void i8254_irq_handler(irq_t *irq)
 {
     /*
      * This IRQ is responsible for kernel preemption.
 ,10 → 94,10
 void i8254_normal_operation(void)
 {
-    outb(CLK_PORT4, 0x36);
+    pio_write_8(CLK_PORT4, 0x36);
     pic_disable_irqs(1 << IRQ_CLK);
-    outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
-    outb(CLK_PORT1, (CLK_CONST / HZ) >> 8);
+    pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
+    pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8);
     pic_enable_irqs(1 << IRQ_CLK);
 }
 ,36 → 114,36
      * One-shot timer. Count-down from 0xffff at 1193180Hz
      * MAGIC_NUMBER is the magic value for 1ms.
      */
-    outb(CLK_PORT4, 0x30);
-    outb(CLK_PORT1, 0xff);
-    outb(CLK_PORT1, 0xff);
+    pio_write_8(CLK_PORT4, 0x30);
+    pio_write_8(CLK_PORT1, 0xff);
+    pio_write_8(CLK_PORT1, 0xff);
     do {
         /* will read both status and count */
-        outb(CLK_PORT4, 0xc2);
-        not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1);
-        t1 = inb(CLK_PORT1);
-        t1 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xc2);
+        not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1);
+        t1 = pio_read_8(CLK_PORT1);
+        t1 |= pio_read_8(CLK_PORT1) << 8;
     } while (not_ok);
     asm_delay_loop(LOOPS);
-    outb(CLK_PORT4, 0xd2);
-    t2 = inb(CLK_PORT1);
-    t2 |= inb(CLK_PORT1) << 8;
+    pio_write_8(CLK_PORT4, 0xd2);
+    t2 = pio_read_8(CLK_PORT1);
+    t2 |= pio_read_8(CLK_PORT1) << 8;
     /*
      * We want to determine the overhead of the calibrating mechanism.
      */
-    outb(CLK_PORT4, 0xd2);
-    o1 = inb(CLK_PORT1);
-    o1 |= inb(CLK_PORT1) << 8;
+    pio_write_8(CLK_PORT4, 0xd2);
+    o1 = pio_read_8(CLK_PORT1);
+    o1 |= pio_read_8(CLK_PORT1) << 8;
     asm_fake_loop(LOOPS);
-    outb(CLK_PORT4, 0xd2);
-    o2 = inb(CLK_PORT1);
-    o2 |= inb(CLK_PORT1) << 8;
+    pio_write_8(CLK_PORT4, 0xd2);
+    o2 = pio_read_8(CLK_PORT1);
+    o2 |= pio_read_8(CLK_PORT1) << 8;
     CPU->delay_loop_const =
         ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) +

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