/branches/dynload/uspace/lib/libc/arch/amd64/include/atomic.h |
---|
38,11 → 38,11 |
#define LIBC_amd64_ATOMIC_H_ |
static inline void atomic_inc(atomic_t *val) { |
asm volatile ("lock incq %0\n" : "=m" (val->count)); |
asm volatile ("lock incq %0\n" : "+m" (val->count)); |
} |
static inline void atomic_dec(atomic_t *val) { |
asm volatile ("lock decq %0\n" : "=m" (val->count)); |
asm volatile ("lock decq %0\n" : "+m" (val->count)); |
} |
static inline long atomic_postinc(atomic_t *val) |
52,7 → 52,7 |
asm volatile ( |
"movq $1, %0\n" |
"lock xaddq %0, %1\n" |
: "=r" (r), "=m" (val->count) |
: "=r" (r), "+m" (val->count) |
); |
return r; |
65,7 → 65,7 |
asm volatile ( |
"movq $-1, %0\n" |
"lock xaddq %0, %1\n" |
: "=r" (r), "=m" (val->count) |
: "=r" (r), "+m" (val->count) |
); |
return r; |
/branches/dynload/uspace/lib/libc/arch/mips32/include/atomic.h |
---|
64,7 → 64,7 |
" sc %0, %1\n" |
" beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ |
/* nop */ /* nop is inserted automatically by compiler */ |
: "=&r" (tmp), "=m" (val->count), "=&r" (v) |
: "=&r" (tmp), "+m" (val->count), "=&r" (v) |
: "i" (i), "i" (0) |
); |
/branches/dynload/uspace/lib/libc/arch/ia32/include/atomic.h |
---|
36,11 → 36,11 |
#define LIBC_ia32_ATOMIC_H_ |
static inline void atomic_inc(atomic_t *val) { |
asm volatile ("lock incl %0\n" : "=m" (val->count)); |
asm volatile ("lock incl %0\n" : "+m" (val->count)); |
} |
static inline void atomic_dec(atomic_t *val) { |
asm volatile ("lock decl %0\n" : "=m" (val->count)); |
asm volatile ("lock decl %0\n" : "+m" (val->count)); |
} |
static inline long atomic_postinc(atomic_t *val) |
50,7 → 50,7 |
asm volatile ( |
"movl $1, %0\n" |
"lock xaddl %0, %1\n" |
: "=r" (r), "=m" (val->count) |
: "=r" (r), "+m" (val->count) |
); |
return r; |
63,7 → 63,7 |
asm volatile ( |
"movl $-1, %0\n" |
"lock xaddl %0, %1\n" |
: "=r" (r), "=m" (val->count) |
: "=r" (r), "+m" (val->count) |
); |
return r; |