/branches/dynload/uspace/app/dltest/dltest.c |
46,6 → 46,14 |
// : "d" (i) /* input */ |
// : "%eax","%ecx" /* all scratch registers clobbered */ |
// ); |
asm volatile ( |
"mr %%r3, %0\n" |
"li %%r9, 32\n" |
"sc\n" |
: |
: "r" (i) |
: "%r3","%r9" |
); |
} |
|
void __tls_get_addr(void) |
52,10 → 60,12 |
{ |
} |
|
int i = 1; |
|
int main(int argc, char *argv[]) |
{ |
/* kputint(-1); |
kputint(0x100); |
kputint(-1); |
/* kputint(0x100); |
printf("Hello from dltest!\n"); |
kputint(0x200); |
while(1);*/ |
/branches/dynload/uspace/app/dltest/arch/ppc32/_link.ld.in |
2,11 → 2,16 |
ENTRY(__entry) |
|
PHDRS { |
interp PT_INTERP; |
text PT_LOAD FLAGS(5); |
data PT_LOAD FLAGS(6); |
} |
|
SECTIONS { |
.interp : { |
*(.interp); |
} :interp |
|
. = 0x1000; |
|
.init ALIGN(0x1000) : SUBALIGN(0x1000) { |
20,7 → 25,7 |
|
.rel.plt ALIGN(0x1000) : { |
*(.rel.plt); |
} |
} :text |
/* |
*.rel.dyn MUST FOLLOW IMMEDIATELY after .rel.plt |
* without alignment gap or DT_REL will be broken |
29,10 → 34,6 |
*(.rel.*); |
} :text |
|
.interp : { |
*(.interp); |
} |
|
.dynamic ALIGN(0x1000) : { |
*(.dynamic); |
} :text |