| 41,8 → 41,6 |
|---|
| #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 |
| #define KERNEL_TRANSLATION_FW 0x00100000F0000671 |
| |
| |
| |
| .section K_TEXT_START, "ax" |
| |
| .global kernel_image_start |
| 51,7 → 49,9 |
|---|
| kernel_image_start: |
| .auto |
| |
| #identifi self(CPU) in OS structures by ID / EID |
| #ifdef CONFIG_SMP |
| # Identify self(CPU) in OS structures by ID / EID |
| |
| mov r9=cr64 |
| mov r10=1 |
| movl r12=0xffffffff |
| 60,9 → 60,8 |
|---|
| shr r9=r9,16 |
| add r8=r8,r9 |
| st1 [r8]=r10 |
| #endif |
| |
| |
| |
| mov psr.l = r0 |
| srlz.i |
| srlz.d |
| 69,39 → 68,29 |
|---|
| |
| # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
| |
| |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) |
| mov r9 = rr[r8] |
| |
| |
| movl r10 = (RR_MASK) |
| and r9 = r10, r9 |
| movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) |
| or r9 = r10, r9 |
| |
| |
| mov rr[r8] = r9 |
| |
| |
| |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) |
| mov cr.ifa = r8 |
| |
| mov r11 = cr.itir |
| movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) |
| or r10 = r10, r11 |
| mov cr.itir = r10 |
| |
| mov r11 = cr.itir ;; |
| movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| mov cr.itir = r10;; |
| |
| |
| movl r10 = (KERNEL_TRANSLATION_I) |
| itr.i itr[r0] = r10 |
| |
| |
| movl r10 = (KERNEL_TRANSLATION_D) |
| itr.d dtr[r0] = r10 |
| |
| |
| movl r7 = 1 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET |
| mov cr.ifa = r8 |
| 108,15 → 97,13 |
|---|
| movl r10 = (KERNEL_TRANSLATION_VIO) |
| itr.d dtr[r7] = r10 |
| |
| mov r11 = cr.itir |
| movl r10 = ~0xfc |
| and r10 = r10, r11 |
| movl r11 = (IO_PAGE_WIDTH << PS_SHIFT) |
| or r10 = r10, r11 |
| mov cr.itir = r10 |
| |
| mov r11 = cr.itir ;; |
| movl r10 = ~0xfc;; |
| and r10 =r10 , r11 ;; |
| movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| mov cr.itir = r10;; |
| |
| |
| movl r7 = 2 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET |
| mov cr.ifa = r8 |
| 123,16 → 110,15 |
|---|
| movl r10 = (KERNEL_TRANSLATION_IO) |
| itr.d dtr[r7] = r10 |
| |
| # Setup mapping for fimware arrea (also SAPIC) |
| |
| #setup mapping for fimware arrea (also SAPIC) |
| mov r11 = cr.itir ;; |
| movl r10 = ~0xfc;; |
| and r10 =r10 , r11 ;; |
| movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| mov cr.itir = r10;; |
| mov r11 = cr.itir |
| movl r10 = ~0xfc |
| and r10 = r10, r11 |
| movl r11 = (FW_PAGE_WIDTH << PS_SHIFT) |
| or r10 = r10, r11 |
| mov cr.itir = r10 |
| |
| |
| movl r7 = 3 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET |
| mov cr.ifa = r8 |
| 139,13 → 125,11 |
|---|
| movl r10 = (KERNEL_TRANSLATION_FW) |
| itr.d dtr[r7] = r10 |
| |
| # Initialize PSR |
| |
| |
| |
| |
| # initialize PSR |
| movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ |
| mov r9 = psr |
| |
| or r10 = r10, r9 |
| mov cr.ipsr = r10 |
| mov cr.ifs = r0 |
| 155,11 → 139,14 |
|---|
| srlz.i |
| |
| .explicit |
| |
| /* |
| * Return From Interupt is the only the way to fill upper half word of PSR. |
| * Return From Interrupt is the only way to |
| * fill the upper half word of PSR. |
| */ |
| rfi;; |
| |
| |
| .global paging_start |
| paging_start: |
| |
| 167,27 → 154,29 |
|---|
| * Now we are paging. |
| */ |
| |
| # switch to register bank 1 |
| # Switch to register bank 1 |
| bsw.1 |
| |
| #Am'I BSP or AP |
| #ifdef CONFIG_SMP |
| # Am I BSP or AP? |
| movl r20=bsp_started;; |
| ld8 r20=[r20];; |
| cmp.eq p3,p2=r20,r0;; |
| #else |
| cmp.eq p3, p2 = r0, r0 ;; /* you are BSP */ |
| #endif /* CONFIG_SMP */ |
| |
| |
| # initialize register stack |
| # Initialize register stack |
| mov ar.rsc = r0 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) ;; |
| mov ar.bspstore = r8 |
| loadrs |
| |
| # initialize memory stack to some sane value |
| # Initialize memory stack to some sane value |
| movl r12 = stack0 ;; |
| |
| add r12 = -16, r12 /* allocate a scratch area on the stack */ |
| |
| # initialize gp (Global Pointer) register |
| # Initialize gp (Global Pointer) register |
| movl r20 = (VRN_KERNEL << VRN_SHIFT);; |
| or r20 = r20,r1;; |
| movl r1 = _hardcoded_load_address |
| 212,6 → 201,7 |
|---|
| srlz.i |
| srlz.d ;; |
| |
| #ifdef CONFIG_SMP |
| (p2) movl r18 = main_ap ;; |
| (p2) mov b1 = r18 ;; |
| (p2) br.call.sptk.many b0 = b1 |
| 220,8 → 210,8 |
|---|
| mov r20=1;; |
| movl r21=bsp_started;; |
| st8 [r21]=r20;; |
| #endif |
| |
| |
| br.call.sptk.many b0 = arch_pre_main |
| |
| movl r18 = main_bsp ;; |
| 228,14 → 218,17 |
|---|
| mov b1 = r18 ;; |
| br.call.sptk.many b0 = b1 |
| |
| |
| 0: |
| br 0b |
| |
| #ifdef CONFIG_SMP |
| |
| .align 4096 |
| |
| kernel_image_ap_start: |
| .auto |
| #identifi self(CPU) in OS structures by ID / EID |
| |
| # Identify self(CPU) in OS structures by ID / EID |
| |
| mov r9=cr64 |
| mov r10=1 |
| movl r12=0xffffffff |
| 245,7 → 238,8 |
|---|
| add r8=r8,r9 |
| st1 [r8]=r10 |
| |
| #wait for wakeup sychro signal (#3 in cpu_by_id_eid_list) |
| # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list) |
| |
| kernel_image_ap_start_loop: |
| movl r11=kernel_image_ap_start_loop |
| and r11=r11,r12 |
| 261,16 → 255,14 |
|---|
| mov b1 = r11 |
| br.call.sptk.many b0 = b1 |
| |
| |
| .align 16 |
| .global bsp_started |
| bsp_started: |
| .space 8 |
| |
| |
| .align 4096 |
| .global cpu_by_id_eid_list |
| cpu_by_id_eid_list: |
| .space 65536 |
| |
| |
| #endif /* CONFIG_SMP */ |