/branches/dynload/kernel/arch/amd64/include/interrupt.h |
---|
71,7 → 71,6 |
/** This is passed to interrupt handlers */ |
typedef struct { |
uint64_t rax; |
uint64_t rbx; |
uint64_t rcx; |
uint64_t rdx; |
uint64_t rsi; |
80,11 → 79,6 |
uint64_t r9; |
uint64_t r10; |
uint64_t r11; |
uint64_t r12; |
uint64_t r13; |
uint64_t r14; |
uint64_t r15; |
uint64_t rbp; |
uint64_t error_word; |
uint64_t rip; |
uint64_t cs; |
/branches/dynload/kernel/arch/amd64/include/asm.h |
---|
73,7 → 73,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint8_t inb(uint16_t port) |
static inline uint8_t pio_read_8(uint16_t port) |
{ |
uint8_t val; |
88,7 → 88,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(uint16_t port, uint8_t val) |
static inline void pio_write_8(uint16_t port, uint8_t val) |
{ |
asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); |
} |
/branches/dynload/kernel/arch/amd64/include/mm/frame.h |
---|
44,6 → 44,7 |
#ifndef __ASM__ |
extern uintptr_t last_frame; |
extern uintptr_t end_frame; |
extern void frame_arch_init(void); |
extern void physmem_print(void); |
#endif /* __ASM__ */ |
/branches/dynload/kernel/arch/amd64/src/asm_utils.S |
---|
26,23 → 26,17 |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
#define IREGISTER_SPACE 120 |
#define IREGISTER_SPACE 72 |
#define IOFFSET_RAX 0x0 |
#define IOFFSET_RBX 0x8 |
#define IOFFSET_RCX 0x10 |
#define IOFFSET_RDX 0x18 |
#define IOFFSET_RSI 0x20 |
#define IOFFSET_RDI 0x28 |
#define IOFFSET_R8 0x30 |
#define IOFFSET_R9 0x38 |
#define IOFFSET_R10 0x40 |
#define IOFFSET_R11 0x48 |
#define IOFFSET_R12 0x50 |
#define IOFFSET_R13 0x58 |
#define IOFFSET_R14 0x60 |
#define IOFFSET_R15 0x68 |
#define IOFFSET_RBP 0x70 |
#define IOFFSET_RAX 0x0 |
#define IOFFSET_RCX 0x8 |
#define IOFFSET_RDX 0x10 |
#define IOFFSET_RSI 0x18 |
#define IOFFSET_RDI 0x20 |
#define IOFFSET_R8 0x28 |
#define IOFFSET_R9 0x30 |
#define IOFFSET_R10 0x38 |
#define IOFFSET_R11 0x40 |
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
# and 1 means interrupt with error word |
173,7 → 167,7 |
rdmsr |
ret |
# Push all general purpose registers on stack except %rbp, %rsp |
# Push all volatile general purpose registers on stack |
.macro save_all_gpr |
movq %rax, IOFFSET_RAX(%rsp) |
movq %rcx, IOFFSET_RCX(%rsp) |
184,14 → 178,6 |
movq %r9, IOFFSET_R9(%rsp) |
movq %r10, IOFFSET_R10(%rsp) |
movq %r11, IOFFSET_R11(%rsp) |
#ifdef CONFIG_DEBUG_ALLREGS |
movq %rbx, IOFFSET_RBX(%rsp) |
movq %rbp, IOFFSET_RBP(%rsp) |
movq %r12, IOFFSET_R12(%rsp) |
movq %r13, IOFFSET_R13(%rsp) |
movq %r14, IOFFSET_R14(%rsp) |
movq %r15, IOFFSET_R15(%rsp) |
#endif |
.endm |
.macro restore_all_gpr |
204,21 → 190,9 |
movq IOFFSET_R9(%rsp), %r9 |
movq IOFFSET_R10(%rsp), %r10 |
movq IOFFSET_R11(%rsp), %r11 |
#ifdef CONFIG_DEBUG_ALLREGS |
movq IOFFSET_RBX(%rsp), %rbx |
movq IOFFSET_RBP(%rsp), %rbp |
movq IOFFSET_R12(%rsp), %r12 |
movq IOFFSET_R13(%rsp), %r13 |
movq IOFFSET_R14(%rsp), %r14 |
movq IOFFSET_R15(%rsp), %r15 |
#endif |
.endm |
#ifdef CONFIG_DEBUG_ALLREGS |
# define INTERRUPT_ALIGN 256 |
#else |
# define INTERRUPT_ALIGN 128 |
#endif |
#define INTERRUPT_ALIGN 128 |
## Declare interrupt handlers |
# |
/branches/dynload/kernel/arch/amd64/src/proc/scheduler.c |
---|
39,7 → 39,6 |
#include <arch.h> |
#include <arch/context.h> /* SP_DELTA */ |
#include <arch/asm.h> |
#include <arch/debugger.h> |
#include <print.h> |
#include <arch/pm.h> |
#include <arch/ddi/ddi.h> |
68,13 → 67,6 |
/* TLS support - set FS to thread local storage */ |
write_msr(AMD_MSR_FS, THREAD->arch.tls); |
#ifdef CONFIG_DEBUG_AS_WATCHPOINT |
/* Set watchpoint on AS to ensure that nobody sets it to zero */ |
if (CPU->id < BKPOINTS_MAX) |
breakpoint_add(&((the_t *) THREAD->kstack)->as, |
BKPOINT_WRITE | BKPOINT_CHECK_ZERO, CPU->id); |
#endif |
} |
void after_thread_ran_arch(void) |
/branches/dynload/kernel/arch/amd64/src/debugger.c |
---|
64,8 → 64,6 |
.argc = 0, |
}; |
#ifndef CONFIG_DEBUG_AS_WATCHPOINT |
static int cmd_del_breakpoint(cmd_arg_t *argv); |
static cmd_arg_t del_argv = { |
.type = ARG_TYPE_INT |
101,7 → 99,6 |
.argv = &addw_argv |
}; |
#endif /* CONFIG_DEBUG_AS_WATCHPOINT */ |
#endif /* CONFIG_KCONSOLE */ |
/* Setup DR register according to table */ |
320,7 → 317,6 |
if (!cmd_register(&bkpts_info)) |
printf("Cannot register command %s\n", bkpts_info.name); |
#ifndef CONFIG_DEBUG_AS_WATCHPOINT |
cmd_initialize(&delbkpt_info); |
if (!cmd_register(&delbkpt_info)) |
printf("Cannot register command %s\n", delbkpt_info.name); |
332,7 → 328,6 |
cmd_initialize(&addwatchp_info); |
if (!cmd_register(&addwatchp_info)) |
printf("Cannot register command %s\n", addwatchp_info.name); |
#endif /* CONFIG_DEBUG_AS_WATCHPOINT */ |
#endif /* CONFIG_KCONSOLE */ |
exc_register(VECTOR_DEBUG, "debugger", debug_exception); |
378,8 → 373,6 |
return 1; |
} |
#ifndef CONFIG_DEBUG_AS_WATCHPOINT |
/** Remove breakpoint from table */ |
int cmd_del_breakpoint(cmd_arg_t *argv) |
{ |
412,7 → 405,6 |
return 1; |
} |
#endif /* CONFIG_DEBUG_AS_WATCHPOINT */ |
#endif /* CONFIG_KCONSOLE */ |
/** @} |
/branches/dynload/kernel/arch/amd64/src/mm/page.c |
---|
214,5 → 214,11 |
return virtaddr; |
} |
void hw_area(uintptr_t *physaddr, pfn_t *frames) |
{ |
*physaddr = end_frame; |
*frames = ADDR2PFN(0xfffffffffffff - end_frame); |
} |
/** @} |
*/ |
/branches/dynload/kernel/arch/amd64/src/interrupt.c |
---|
80,12 → 80,6 |
istate->rdi, istate->r8); |
printf("%%r9=%#llx, %%r10=%#llx, %%r11=%#llx\n", istate->r9, |
istate->r10, istate->r11); |
#ifdef CONFIG_DEBUG_ALLREGS |
printf("%%r12=%#llx, %%r13=%#llx, %%r14=%#llx\n", istate->r12, |
istate->r13, istate->r14); |
printf("%%r15=%#llx, %%rbx=%#llx, %%rbp=%#llx\n", istate->r15, |
istate->rbx, &istate->rbp); |
#endif |
printf("%%rsp=%#llx\n", &istate->stack[0]); |
} |
179,7 → 173,7 |
trap_virtual_eoi(); |
ack = true; |
} |
irq->handler(irq, irq->arg); |
irq->handler(irq); |
spinlock_unlock(&irq->lock); |
} else { |
/* |