/branches/dd/kernel/genarch/src/drivers/dsrln/dsrlnout.c |
---|
40,13 → 40,18 |
#include <arch/asm.h> |
#include <console/console.h> |
#include <sysinfo/sysinfo.h> |
#include <string.h> |
static ioport8_t *dsrlnout_base; |
static void dsrlnout_putchar(outdev_t *dev __attribute__((unused)), const char ch, bool silent) |
static void dsrlnout_putchar(outdev_t *dev __attribute__((unused)), const wchar_t ch, bool silent) |
{ |
if (!silent) |
pio_write_8(dsrlnout_base, ch); |
if (!silent) { |
if (ascii_check(ch)) |
pio_write_8(dsrlnout_base, ch); |
else |
pio_write_8(dsrlnout_base, U_SPECIAL); |
} |
} |
static outdev_t dsrlnout_console; |
/branches/dd/kernel/genarch/src/drivers/i8042/i8042.c |
---|
34,6 → 34,7 |
* @brief i8042 processor driver |
* |
* It takes care of the i8042 serial communication. |
* |
*/ |
#include <genarch/drivers/i8042/i8042.h> |
49,6 → 50,7 |
#define i8042_SET_COMMAND 0x60 |
#define i8042_COMMAND 0x69 |
#define i8042_CPU_RESET 0xfe |
#define i8042_BUFFER_FULL_MASK 0x01 |
#define i8042_WAIT_MASK 0x02 |
96,9 → 98,7 |
instance->irq.instance = instance; |
irq_register(&instance->irq); |
/* |
* Clear input buffer. |
*/ |
/* Clear input buffer */ |
while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
(void) pio_read_8(&dev->data); |
105,5 → 105,18 |
return &instance->kbrdin; |
} |
/* Reset CPU by pulsing pin 0 */ |
void i8042_cpu_reset(i8042_t *dev) |
{ |
interrupts_disable(); |
/* Clear input buffer */ |
while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
(void) pio_read_8(&dev->data); |
/* Reset CPU */ |
pio_write_8(&dev->status, i8042_CPU_RESET); |
} |
/** @} |
*/ |
/branches/dd/kernel/genarch/src/drivers/ega/ega.c |
---|
44,6 → 44,7 |
#include <arch/types.h> |
#include <arch/asm.h> |
#include <memstr.h> |
#include <string.h> |
#include <console/chardev.h> |
#include <console/console.h> |
#include <sysinfo/sysinfo.h> |
485,7 → 486,7 |
uint8_t style; |
if ((index >> 8)) { |
glyph = '?'; |
glyph = U_SPECIAL; |
style = INVAL; |
} else { |
glyph = index & 0xff; |