/branches/dd/kernel/arch/sparc64/include/trap/mmu.h |
---|
103,17 → 103,20 |
* Note that branch-delay slots are used in order to save space. |
*/ |
0: |
mov VA_DMMU_TAG_ACCESS, %g1 |
ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 |
wr %g0, ASI_DMMU, %asi |
ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN |
set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
andcc %g1, %g2, %g3 ! get Context |
bnz 0f ! Context is non-zero |
bnz %xcc, 0f ! Context is non-zero |
andncc %g1, %g2, %g3 ! get page address into %g3 |
bz 0f ! page address is zero |
bz %xcc, 0f ! page address is zero |
ldx [%g7 + %lo(end_of_identity)], %g4 |
cmp %g3, %g4 |
bgeu %xcc, 0f |
sethi %hi(kernel_8k_tlb_data_template), %g2 |
ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2 |
or %g3, %g2, %g2 |
ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 |
add %g3, %g2, %g2 |
stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
retry |
138,8 → 141,7 |
* Read the Tag Access register for the higher-level handler. |
* This is necessary to survive nested DTLB misses. |
*/ |
mov VA_DMMU_TAG_ACCESS, %g2 |
ldxa [%g2] ASI_DMMU, %g2 |
ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 |
/* |
* g2 will be passed as an argument to fast_data_access_mmu_miss(). |
/branches/dd/kernel/arch/sparc64/include/mm/frame.h |
---|
73,6 → 73,8 |
typedef union frame_address frame_address_t; |
extern uintptr_t last_frame; |
extern uintptr_t end_of_identity; |
extern void frame_arch_init(void); |
#define physmem_print() |
/branches/dd/kernel/arch/sparc64/include/drivers/sgcn.h |
---|
38,16 → 38,16 |
#include <arch/types.h> |
#include <console/chardev.h> |
/* number of bytes in the TOC magic, including the terminating '\0' */ |
/* number of bytes in the TOC magic, including the NULL-terminator */ |
#define TOC_MAGIC_BYTES 8 |
/* number of bytes in the TOC key, including the terminating '\0' */ |
/* number of bytes in the TOC key, including the NULL-terminator */ |
#define TOC_KEY_SIZE 8 |
/* maximum number of entries in the SRAM table of contents */ |
#define MAX_TOC_ENTRIES 32 |
/* number of bytes in the SGCN buffer magic, including the terminating '\0' */ |
/* number of bytes in the SGCN buffer magic, including the NULL-terminator */ |
#define SGCN_MAGIC_BYTES 4 |
/** |
/branches/dd/kernel/arch/sparc64/src/console.c |
---|
95,7 → 95,7 |
indev_t *kbrdin; |
kbrdin = sgcnin_init(); |
if (kbrdin) |
srlnin_init(kbrdin); |
srln_init(kbrdin); |
#endif |
#ifdef CONFIG_SGCN_PRN |
sgcnout_init(); |
118,7 → 118,7 |
/* "def-cn" = "default console" */ |
prop = ofw_tree_getprop(aliases, "def-cn"); |
if ((!prop) || (!prop->value) || (strcmp(prop->value, "/sgcn") != 0)) { |
if ((!prop) || (!prop->value) || (str_cmp(prop->value, "/sgcn") != 0)) { |
standard_console_init(aliases); |
} else { |
serengeti_init(); |
134,8 → 134,9 |
#ifdef CONFIG_FB |
scr_redraw(); |
#endif |
switch (kbd_type) { |
#ifdef CONFIG_SGCN |
#ifdef CONFIG_SGCN_KBD |
case KBD_SGCN: |
sgcn_grab(); |
break; |
151,7 → 152,7 |
void arch_release_console(void) |
{ |
switch (kbd_type) { |
#ifdef CONFIG_SGCN |
#ifdef CONFIG_SGCN_KBD |
case KBD_SGCN: |
sgcn_release(); |
break; |
/branches/dd/kernel/arch/sparc64/src/sparc64.c |
---|
61,8 → 61,8 |
for (i = 0; i < bootinfo.taskmap.count; i++) { |
init.tasks[i].addr = (uintptr_t) bootinfo.taskmap.tasks[i].addr; |
init.tasks[i].size = bootinfo.taskmap.tasks[i].size; |
strncpy(init.tasks[i].name, bootinfo.taskmap.tasks[i].name, |
CONFIG_TASK_NAME_BUFLEN); |
str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN, |
bootinfo.taskmap.tasks[i].name); |
} |
/* Copy boot allocations info. */ |
/branches/dd/kernel/arch/sparc64/src/trap/trap_table.S |
---|
478,7 → 478,7 |
*/ |
rdpr %tl, %g3 |
cmp %g3, 1 |
be 1f |
be %xcc, 1f |
nop |
0: ba 0b ! this is for debugging, if we ever get here |
nop ! it will be easy to find |
499,7 → 499,7 |
wrpr %g4, 0, %cwp ! resynchronize CWP |
andcc %g3, TSTATE_PRIV_BIT, %g0 ! if this trap came from the privileged mode... |
bnz 0f ! ...skip setting of kernel stack and primary context |
bnz %xcc, 0f ! ...skip setting of kernel stack and primary context |
nop |
.endif |
672,7 → 672,7 |
and %l0, NWINDOWS - 1, %l0 ! %l0 mod NWINDOWS |
rdpr %cwp, %l1 |
cmp %l0, %l1 |
bz 0f ! CWP is ok |
bz %xcc, 0f ! CWP is ok |
nop |
/* |
712,7 → 712,7 |
.if NOT(\is_syscall) |
rdpr %tstate, %g1 |
andcc %g1, TSTATE_PRIV_BIT, %g0 ! if we are not returning to userspace..., |
bnz 1f ! ...skip restoring userspace windows |
bnz %xcc, 1f ! ...skip restoring userspace windows |
nop |
.endif |
749,7 → 749,7 |
*/ |
clr %g4 |
0: andcc %g7, UWB_ALIGNMENT - 1, %g0 ! alignment check |
bz 0f ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill |
bz %xcc, 0f ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill |
nop |
add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7 |
785,7 → 785,7 |
wrpr %g1, 0, %cwp |
add %g4, %g2, %g2 |
cmp %g2, NWINDOWS - 2 |
bg 2f ! fix the CANRESTORE=NWINDOWS-1 anomaly |
bg %xcc, 2f ! fix the CANRESTORE=NWINDOWS-1 anomaly |
mov NWINDOWS - 2, %g1 ! use dealy slot for both cases |
sub %g1, %g2, %g1 |
/branches/dd/kernel/arch/sparc64/src/mm/tlb.c |
---|
199,12 → 199,12 |
/** ITLB miss handler. */ |
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
{ |
uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
pte_t *t; |
page_table_lock(AS, true); |
t = page_mapping_find(AS, va); |
t = page_mapping_find(AS, page_16k); |
if (t && PTE_EXECUTABLE(t)) { |
/* |
* The mapping was found in the software page hash table. |
222,7 → 222,8 |
* handler. |
*/ |
page_table_unlock(AS, true); |
if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) == |
AS_PF_FAULT) { |
do_fast_instruction_access_mmu_miss_fault(istate, |
__func__); |
} |
242,11 → 243,13 |
*/ |
void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
{ |
uintptr_t va; |
uintptr_t page_8k; |
uintptr_t page_16k; |
index_t index; |
pte_t *t; |
va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH; |
page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE); |
index = tag.vpn % MMU_PAGES_PER_PAGE; |
if (tag.context == ASID_KERNEL) { |
254,6 → 257,15 |
/* NULL access in kernel */ |
do_fast_data_access_mmu_miss_fault(istate, tag, |
__func__); |
} else if (page_8k >= end_of_identity) { |
/* |
* The kernel is accessing the I/O space. |
* We still do identity mapping for I/O, |
* but without caching. |
*/ |
dtlb_insert_mapping(page_8k, KA2PA(page_8k), |
PAGESIZE_8K, false, false); |
return; |
} |
do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
"kernel page fault."); |
260,7 → 272,7 |
} |
page_table_lock(AS, true); |
t = page_mapping_find(AS, va); |
t = page_mapping_find(AS, page_16k); |
if (t) { |
/* |
* The mapping was found in the software page hash table. |
278,7 → 290,8 |
* handler. |
*/ |
page_table_unlock(AS, true); |
if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
if (as_page_fault(page_16k, PF_ACCESS_READ, istate) == |
AS_PF_FAULT) { |
do_fast_data_access_mmu_miss_fault(istate, tag, |
__func__); |
} |
295,15 → 308,15 |
*/ |
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
{ |
uintptr_t va; |
uintptr_t page_16k; |
index_t index; |
pte_t *t; |
va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
page_table_lock(AS, true); |
t = page_mapping_find(AS, va); |
t = page_mapping_find(AS, page_16k); |
if (t && PTE_WRITABLE(t)) { |
/* |
* The mapping was found in the software page hash table and is |
313,7 → 326,7 |
t->a = true; |
t->d = true; |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
va + index * MMU_PAGE_SIZE); |
page_16k + index * MMU_PAGE_SIZE); |
dtlb_pte_copy(t, index, false); |
#ifdef CONFIG_TSB |
dtsb_pte_copy(t, index, false); |
325,7 → 338,8 |
* handler. |
*/ |
page_table_unlock(AS, true); |
if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) == |
AS_PF_FAULT) { |
do_fast_data_access_protection_fault(istate, tag, |
__func__); |
} |
/branches/dd/kernel/arch/sparc64/src/mm/frame.c |
---|
79,6 → 79,8 |
*/ |
frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1); |
} |
end_of_identity = PA2KA(last_frame); |
} |
/** @} |
/branches/dd/kernel/arch/sparc64/src/mm/page.c |
---|
53,12 → 53,12 |
* |
* We are currently using identity mapping for mapping device registers. |
* |
* @param physaddr Physical address of the page where the device is |
* located. |
* @param size Size of the device's registers. This argument is |
* ignored. |
* @param physaddr Physical address of the page where the device is |
* located. |
* @param size Size of the device's registers. |
* |
* @return Virtual address of the page where the device is mapped. |
* @return Virtual address of the page where the device is mapped. |
* |
*/ |
uintptr_t hw_map(uintptr_t physaddr, size_t size) |
{ |
/branches/dd/kernel/arch/sparc64/src/drivers/kbd.c |
---|
86,9 → 86,9 |
/* |
* Determine keyboard serial controller type. |
*/ |
if (strcmp(name, "zs") == 0) |
if (str_cmp(name, "zs") == 0) |
kbd_type = KBD_Z8530; |
else if (strcmp(name, "su") == 0) |
else if (str_cmp(name, "su") == 0) |
kbd_type = KBD_NS16550; |
if (kbd_type == KBD_UNKNOWN) { |
162,8 → 162,8 |
switch (kbd_type) { |
#ifdef CONFIG_Z8530 |
case KBD_Z8530: |
z8530 = (z8530_t *) hw_map(aligned_addr, offset + size) + |
offset; |
z8530 = (z8530_t *) |
(hw_map(aligned_addr, offset + size) + offset); |
indev_t *kbrdin_z8530 = z8530_init(z8530, inr, cir, cir_arg); |
if (kbrdin_z8530) |
183,8 → 183,8 |
#endif |
#ifdef CONFIG_NS16550 |
case KBD_NS16550: |
ns16550 = (ns16550_t *) hw_map(aligned_addr, offset + size) + |
offset; |
ns16550 = (ns16550_t *) |
(hw_map(aligned_addr, offset + size) + offset); |
indev_t *kbrdin_ns16550 = ns16550_init(ns16550, inr, cir, cir_arg); |
if (kbrdin_ns16550) |
/branches/dd/kernel/arch/sparc64/src/drivers/scr.c |
---|
63,13 → 63,13 |
name = ofw_tree_node_name(node); |
if (strcmp(name, "SUNW,m64B") == 0) |
if (str_cmp(name, "SUNW,m64B") == 0) |
scr_type = SCR_ATYFB; |
else if (strcmp(name, "SUNW,XVR-100") == 0) |
else if (str_cmp(name, "SUNW,XVR-100") == 0) |
scr_type = SCR_XVR; |
else if (strcmp(name, "SUNW,ffb") == 0) |
else if (str_cmp(name, "SUNW,ffb") == 0) |
scr_type = SCR_FFB; |
else if (strcmp(name, "cgsix") == 0) |
else if (str_cmp(name, "cgsix") == 0) |
scr_type = SCR_CGSIX; |
if (scr_type == SCR_UNKNOWN) { |
/branches/dd/kernel/arch/sparc64/src/drivers/sgcn.c |
---|
31,7 → 31,7 |
*/ |
/** |
* @file |
* @brief SGCN driver. |
* @brief SGCN driver. |
*/ |
#include <arch.h> |
207,12 → 207,12 |
init_sram_begin(); |
ASSERT(strcmp(SRAM_TOC->magic, SRAM_TOC_MAGIC) == 0); |
ASSERT(str_cmp(SRAM_TOC->magic, SRAM_TOC_MAGIC) == 0); |
/* lookup TOC entry with the correct key */ |
uint32_t i; |
for (i = 0; i < MAX_TOC_ENTRIES; i++) { |
if (strcmp(SRAM_TOC->keys[i].key, CONSOLE_KEY) == 0) |
if (str_cmp(SRAM_TOC->keys[i].key, CONSOLE_KEY) == 0) |
break; |
} |
ASSERT(i < MAX_TOC_ENTRIES); |
277,7 → 277,7 |
sgcn_do_putchar('\r'); |
sgcn_do_putchar(ch); |
} else |
sgcn_do_putchar(invalch); |
sgcn_do_putchar(U_SPECIAL); |
spinlock_unlock(&sgcn_output_lock); |
} |
/branches/dd/kernel/arch/sparc64/src/drivers/pci.c |
---|
183,7 → 183,7 |
/* |
* First, verify this is a PCI node. |
*/ |
ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0); |
ASSERT(str_cmp(ofw_tree_node_name(node), "pci") == 0); |
/* |
* Determine PCI controller model. |
192,13 → 192,13 |
if (!prop || !prop->value) |
return NULL; |
if (strcmp(prop->value, "SUNW,sabre") == 0) { |
if (str_cmp(prop->value, "SUNW,sabre") == 0) { |
/* |
* PCI controller Sabre. |
* This model is found on UltraSPARC IIi based machines. |
*/ |
return pci_sabre_init(node); |
} else if (strcmp(prop->value, "SUNW,psycho") == 0) { |
} else if (str_cmp(prop->value, "SUNW,psycho") == 0) { |
/* |
* PCI controller Psycho. |
* Used on UltraSPARC II based processors, for instance, |
/branches/dd/kernel/arch/sparc64/src/start.S |
---|
84,7 → 84,7 |
! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
/* |
* Setup basic runtime environment. |
*/ |
333,7 → 333,7 |
2: |
ldx [%g2], %g3 |
cmp %g3, %g1 |
bne 2b |
bne %xcc, 2b |
nop |
/* |
381,10 → 381,31 |
.quad 0 |
/* |
* This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
* is further modified to reflect the starting address of physical memory. |
* The fast_data_access_mmu_miss_data_hi label and the end_of_identity and |
* kernel_8k_tlb_data_template variables are meant to stay together, |
* aligned on 16B boundary. |
*/ |
.global fast_data_access_mmu_miss_data_hi |
.global end_of_identity |
.global kernel_8k_tlb_data_template |
.align 16 |
/* |
* This label is used by the fast_data_access_MMU_miss trap handler. |
*/ |
fast_data_access_mmu_miss_data_hi: |
/* |
* This variable is used by the fast_data_access_MMU_miss trap handler. |
* In runtime, it is modified to contain the address of the end of physical |
* memory. |
*/ |
end_of_identity: |
.quad -1 |
/* |
* This variable is used by the fast_data_access_MMU_miss trap handler. |
* In runtime, it is further modified to reflect the starting address of |
* physical memory. |
*/ |
kernel_8k_tlb_data_template: |
#ifdef CONFIG_VIRT_IDX_DCACHE |
.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |