| 53,8 → 53,8 |
|---|
| #include <ddi/irq.h> |
| #include <ddi/device.h> |
| |
| #define CLK_PORT1 0x40 |
| #define CLK_PORT4 0x43 |
| #define CLK_PORT1 ((ioport8_t *)0x40) |
| #define CLK_PORT4 ((ioport8_t *)0x43) |
| |
| #define CLK_CONST 1193180 |
| #define MAGIC_NUMBER 1194 |
| 61,12 → 61,12 |
|---|
| |
| static irq_t i8254_irq; |
| |
| static irq_ownership_t i8254_claim(void) |
| static irq_ownership_t i8254_claim(irq_t *irq) |
| { |
| return IRQ_ACCEPT; |
| } |
| |
| static void i8254_irq_handler(irq_t *irq, void *arg __attribute__((unused)), ...) |
| static void i8254_irq_handler(irq_t *irq) |
| { |
| /* |
| * This IRQ is responsible for kernel preemption. |
| 94,10 → 94,10 |
|---|
| |
| void i8254_normal_operation(void) |
| { |
| outb(CLK_PORT4, 0x36); |
| pio_write_8(CLK_PORT4, 0x36); |
| pic_disable_irqs(1 << IRQ_CLK); |
| outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
| outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
| pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
| pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
| pic_enable_irqs(1 << IRQ_CLK); |
| } |
| |
| 114,36 → 114,36 |
|---|
| * One-shot timer. Count-down from 0xffff at 1193180Hz |
| * MAGIC_NUMBER is the magic value for 1ms. |
| */ |
| outb(CLK_PORT4, 0x30); |
| outb(CLK_PORT1, 0xff); |
| outb(CLK_PORT1, 0xff); |
| pio_write_8(CLK_PORT4, 0x30); |
| pio_write_8(CLK_PORT1, 0xff); |
| pio_write_8(CLK_PORT1, 0xff); |
| |
| do { |
| /* will read both status and count */ |
| outb(CLK_PORT4, 0xc2); |
| not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1); |
| t1 = inb(CLK_PORT1); |
| t1 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xc2); |
| not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1); |
| t1 = pio_read_8(CLK_PORT1); |
| t1 |= pio_read_8(CLK_PORT1) << 8; |
| } while (not_ok); |
| |
| asm_delay_loop(LOOPS); |
| |
| outb(CLK_PORT4, 0xd2); |
| t2 = inb(CLK_PORT1); |
| t2 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| t2 = pio_read_8(CLK_PORT1); |
| t2 |= pio_read_8(CLK_PORT1) << 8; |
| |
| /* |
| * We want to determine the overhead of the calibrating mechanism. |
| */ |
| outb(CLK_PORT4, 0xd2); |
| o1 = inb(CLK_PORT1); |
| o1 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| o1 = pio_read_8(CLK_PORT1); |
| o1 |= pio_read_8(CLK_PORT1) << 8; |
| |
| asm_fake_loop(LOOPS); |
| |
| outb(CLK_PORT4, 0xd2); |
| o2 = inb(CLK_PORT1); |
| o2 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| o2 = pio_read_8(CLK_PORT1); |
| o2 |= pio_read_8(CLK_PORT1) << 8; |
| |
| CPU->delay_loop_const = |
| ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |