| /branches/dd/kernel/arch/ia32/src/drivers/ega.c |
|---|
| File deleted |
| /branches/dd/kernel/arch/ia32/src/drivers/vesa.c |
|---|
| 83,12 → 83,25 |
| visual = VISUAL_RGB_0_8_8_8; |
| break; |
| default: |
| panic("Unsupported bits per pixel"); |
| panic("Unsupported bits per pixel."); |
| } |
| fb_init(vesa_ph_addr, vesa_width, vesa_height, vesa_scanline, visual); |
| fb_properties_t vesa_props = { |
| .addr = vesa_ph_addr, |
| .offset = 0, |
| .x = vesa_width, |
| .y = vesa_height, |
| .scan = vesa_scanline, |
| .visual = visual, |
| }; |
| fb_init(&vesa_props); |
| } |
| void vesa_redraw(void) |
| { |
| fb_redraw(); |
| } |
| #endif |
| /** @} |
| /branches/dd/kernel/arch/ia32/src/drivers/i8259.c |
|---|
| 49,28 → 49,28 |
| void i8259_init(void) |
| { |
| /* ICW1: this is ICW1, ICW4 to follow */ |
| outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4); |
| pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4); |
| /* ICW2: IRQ 0 maps to INT IRQBASE */ |
| outb(PIC_PIC0PORT2, IVT_IRQBASE); |
| pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE); |
| /* ICW3: pic1 using IRQ IRQ_PIC1 */ |
| outb(PIC_PIC0PORT2, 1 << IRQ_PIC1); |
| pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1); |
| /* ICW4: i8086 mode */ |
| outb(PIC_PIC0PORT2, 1); |
| pio_write_8(PIC_PIC0PORT2, 1); |
| /* ICW1: ICW1, ICW4 to follow */ |
| outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4); |
| pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4); |
| /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */ |
| outb(PIC_PIC1PORT2, IVT_IRQBASE + 8); |
| pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8); |
| /* ICW3: pic1 is known as IRQ_PIC1 */ |
| outb(PIC_PIC1PORT2, IRQ_PIC1); |
| pio_write_8(PIC_PIC1PORT2, IRQ_PIC1); |
| /* ICW4: i8086 mode */ |
| outb(PIC_PIC1PORT2, 1); |
| pio_write_8(PIC_PIC1PORT2, 1); |
| /* |
| * Register interrupt handler for the PIC spurious interrupt. |
| 94,12 → 94,12 |
| uint8_t x; |
| if (irqmask & 0xff) { |
| x = inb(PIC_PIC0PORT2); |
| outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff)))); |
| x = pio_read_8(PIC_PIC0PORT2); |
| pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff)))); |
| } |
| if (irqmask >> 8) { |
| x = inb(PIC_PIC1PORT2); |
| outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8)))); |
| x = pio_read_8(PIC_PIC1PORT2); |
| pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8)))); |
| } |
| } |
| 108,19 → 108,19 |
| uint8_t x; |
| if (irqmask & 0xff) { |
| x = inb(PIC_PIC0PORT2); |
| outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff))); |
| x = pio_read_8(PIC_PIC0PORT2); |
| pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff))); |
| } |
| if (irqmask >> 8) { |
| x = inb(PIC_PIC1PORT2); |
| outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8))); |
| x = pio_read_8(PIC_PIC1PORT2); |
| pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8))); |
| } |
| } |
| void pic_eoi(void) |
| { |
| outb(0x20, 0x20); |
| outb(0xa0, 0x20); |
| pio_write_8((ioport8_t *)0x20, 0x20); |
| pio_write_8((ioport8_t *)0xa0, 0x20); |
| } |
| void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) |
| /branches/dd/kernel/arch/ia32/src/drivers/i8254.c |
|---|
| 53,8 → 53,8 |
| #include <ddi/irq.h> |
| #include <ddi/device.h> |
| #define CLK_PORT1 0x40 |
| #define CLK_PORT4 0x43 |
| #define CLK_PORT1 ((ioport8_t *)0x40) |
| #define CLK_PORT4 ((ioport8_t *)0x43) |
| #define CLK_CONST 1193180 |
| #define MAGIC_NUMBER 1194 |
| 61,12 → 61,12 |
| static irq_t i8254_irq; |
| static irq_ownership_t i8254_claim(void) |
| static irq_ownership_t i8254_claim(irq_t *irq) |
| { |
| return IRQ_ACCEPT; |
| } |
| static void i8254_irq_handler(irq_t *irq, void *arg __attribute__((unused)), ...) |
| static void i8254_irq_handler(irq_t *irq) |
| { |
| /* |
| * This IRQ is responsible for kernel preemption. |
| 94,10 → 94,10 |
| void i8254_normal_operation(void) |
| { |
| outb(CLK_PORT4, 0x36); |
| pio_write_8(CLK_PORT4, 0x36); |
| pic_disable_irqs(1 << IRQ_CLK); |
| outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
| outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
| pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
| pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
| pic_enable_irqs(1 << IRQ_CLK); |
| } |
| 114,36 → 114,36 |
| * One-shot timer. Count-down from 0xffff at 1193180Hz |
| * MAGIC_NUMBER is the magic value for 1ms. |
| */ |
| outb(CLK_PORT4, 0x30); |
| outb(CLK_PORT1, 0xff); |
| outb(CLK_PORT1, 0xff); |
| pio_write_8(CLK_PORT4, 0x30); |
| pio_write_8(CLK_PORT1, 0xff); |
| pio_write_8(CLK_PORT1, 0xff); |
| do { |
| /* will read both status and count */ |
| outb(CLK_PORT4, 0xc2); |
| not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1); |
| t1 = inb(CLK_PORT1); |
| t1 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xc2); |
| not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1); |
| t1 = pio_read_8(CLK_PORT1); |
| t1 |= pio_read_8(CLK_PORT1) << 8; |
| } while (not_ok); |
| asm_delay_loop(LOOPS); |
| outb(CLK_PORT4, 0xd2); |
| t2 = inb(CLK_PORT1); |
| t2 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| t2 = pio_read_8(CLK_PORT1); |
| t2 |= pio_read_8(CLK_PORT1) << 8; |
| /* |
| * We want to determine the overhead of the calibrating mechanism. |
| */ |
| outb(CLK_PORT4, 0xd2); |
| o1 = inb(CLK_PORT1); |
| o1 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| o1 = pio_read_8(CLK_PORT1); |
| o1 |= pio_read_8(CLK_PORT1) << 8; |
| asm_fake_loop(LOOPS); |
| outb(CLK_PORT4, 0xd2); |
| o2 = inb(CLK_PORT1); |
| o2 |= inb(CLK_PORT1) << 8; |
| pio_write_8(CLK_PORT4, 0xd2); |
| o2 = pio_read_8(CLK_PORT1); |
| o2 |= pio_read_8(CLK_PORT1) << 8; |
| CPU->delay_loop_const = |
| ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |