| 42,22 → 42,23 |
|---|
| #include <fpu_context.h> |
| |
| #include <arch/smp/apic.h> |
| #include <arch/syscall.h> |
| |
| /* |
| * Identification of CPUs. |
| * Contains only non-MP-Specification specific SMP code. |
| */ |
| #define AMD_CPUID_EBX 0x68747541 |
| #define AMD_CPUID_ECX 0x444d4163 |
| #define AMD_CPUID_EDX 0x69746e65 |
| #define AMD_CPUID_EBX 0x68747541 |
| #define AMD_CPUID_ECX 0x444d4163 |
| #define AMD_CPUID_EDX 0x69746e65 |
| |
| #define INTEL_CPUID_EBX 0x756e6547 |
| #define INTEL_CPUID_ECX 0x6c65746e |
| #define INTEL_CPUID_EDX 0x49656e69 |
| #define INTEL_CPUID_EBX 0x756e6547 |
| #define INTEL_CPUID_ECX 0x6c65746e |
| #define INTEL_CPUID_EDX 0x49656e69 |
| |
| |
| enum vendor { |
| VendorUnknown=0, |
| VendorUnknown = 0, |
| VendorAMD, |
| VendorIntel |
| }; |
| 64,19 → 65,17 |
|---|
| |
| static char *vendor_str[] = { |
| "Unknown Vendor", |
| "AuthenticAMD", |
| "GenuineIntel" |
| "AMD", |
| "Intel" |
| }; |
| |
| void fpu_disable(void) |
| { |
| asm volatile ( |
| "mov %%cr0,%%eax;" |
| "or $8,%%eax;" |
| "mov %%eax,%%cr0;" |
| : |
| : |
| :"%eax" |
| "mov %%cr0, %%eax\n" |
| "or $8, %%eax\n" |
| "mov %%eax, %%cr0\n" |
| ::: "%eax" |
| ); |
| } |
| |
| 83,13 → 82,11 |
|---|
| void fpu_enable(void) |
| { |
| asm volatile ( |
| "mov %%cr0,%%eax;" |
| "and $0xffFFffF7,%%eax;" |
| "mov %%eax,%%cr0;" |
| : |
| : |
| :"%eax" |
| ); |
| "mov %%cr0, %%eax\n" |
| "and $0xffFFffF7, %%eax\n" |
| "mov %%eax,%%cr0\n" |
| ::: "%eax" |
| ); |
| } |
| |
| void cpu_arch_init(void) |
| 101,11 → 98,11 |
|---|
| |
| CPU->arch.tss = tss_p; |
| CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss); |
| |
| |
| CPU->fpu_owner = NULL; |
| |
| |
| cpuid(1, &info); |
| |
| |
| fi.word = info.cpuid_edx; |
| efi.word = info.cpuid_ecx; |
| |
| 112,17 → 109,20 |
|---|
| if (fi.bits.fxsr) |
| fpu_fxsr(); |
| else |
| fpu_fsr(); |
| fpu_fsr(); |
| |
| if (fi.bits.sse) { |
| asm volatile ( |
| "mov %%cr4,%0\n" |
| "or %1,%0\n" |
| "mov %0,%%cr4\n" |
| : "+r" (help) |
| : "i" (CR4_OSFXSR_MASK|(1<<10)) |
| "mov %%cr4, %[help]\n" |
| "or %[mask], %[help]\n" |
| "mov %[help], %%cr4\n" |
| : [help] "+r" (help) |
| : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10)) |
| ); |
| } |
| |
| /* Setup fast SYSENTER/SYSEXIT syscalls */ |
| syscall_setup_cpu(); |
| } |
| |
| void cpu_identify(void) |
| 136,29 → 136,31 |
|---|
| /* |
| * Check for AMD processor. |
| */ |
| if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) { |
| if ((info.cpuid_ebx == AMD_CPUID_EBX) |
| && (info.cpuid_ecx == AMD_CPUID_ECX) |
| && (info.cpuid_edx == AMD_CPUID_EDX)) |
| CPU->arch.vendor = VendorAMD; |
| } |
| |
| |
| /* |
| * Check for Intel processor. |
| */ |
| if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) { |
| if ((info.cpuid_ebx == INTEL_CPUID_EBX) |
| && (info.cpuid_ecx == INTEL_CPUID_ECX) |
| && (info.cpuid_edx == INTEL_CPUID_EDX)) |
| CPU->arch.vendor = VendorIntel; |
| } |
| |
| |
| cpuid(1, &info); |
| CPU->arch.family = (info.cpuid_eax>>8)&0xf; |
| CPU->arch.model = (info.cpuid_eax>>4)&0xf; |
| CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; |
| CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f; |
| CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f; |
| CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f; |
| } |
| } |
| |
| void cpu_print_report(cpu_t* m) |
| void cpu_print_report(cpu_t* cpu) |
| { |
| printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n", |
| m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping, |
| m->frequency_mhz); |
| printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n", |
| cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family, |
| cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz); |
| } |
| |
| /** @} |