/branches/dd/kernel/arch/amd64/src/fpu_context.c |
---|
39,8 → 39,8 |
void fpu_context_save(fpu_context_t *fctx) |
{ |
asm volatile ( |
"fxsave %0" |
: "=m"(*fctx) |
"fxsave %[fctx]\n" |
: [fctx] "=m" (*fctx) |
); |
} |
48,8 → 48,8 |
void fpu_context_restore(fpu_context_t *fctx) |
{ |
asm volatile ( |
"fxrstor %0" |
: "=m"(*fctx) |
"fxrstor %[fctx]\n" |
: [fctx] "=m" (*fctx) |
); |
} |
57,7 → 57,7 |
{ |
/* TODO: Zero all SSE, MMX etc. registers */ |
asm volatile ( |
"fninit;" |
"fninit\n" |
); |
} |