| 30,6 → 30,9 |
|---|
| #include <stack.h> |
| #include <register.h> |
| |
| .register %g2, #scratch |
| .register %g3, #scratch |
| |
| .text |
| |
| .global halt |
| 41,8 → 44,7 |
|---|
| nop |
| |
| memcpy: |
| .register %g2, #scratch |
| .register %g3, #scratch |
| mov %o0, %o3 ! save dst |
| add %o1, 7, %g1 |
| and %g1, -8, %g1 |
| cmp %o1, %g1 |
| 61,7 → 63,7 |
|---|
| mov %g2, %g3 |
| 2: |
| jmp %o7 + 8 ! exit point |
| mov %o1, %o0 |
| mov %o3, %o0 |
| 3: |
| and %g1, -8, %g1 |
| cmp %o0, %g1 |
| 95,9 → 97,38 |
|---|
| mov %g2, %g3 |
| |
| jmp %o7 + 8 ! exit point |
| mov %o1, %o0 |
| mov %o3, %o0 |
| |
| jump_to_kernel: |
| /* |
| * We have copied code and now we need to guarantee cache coherence. |
| * 1. Make sure that the code we have moved has drained to main memory. |
| * 2. Invalidate I-cache. |
| * 3. Flush instruction pipeline. |
| */ |
| |
| /* |
| * US3 processors have a write-invalidate cache, so explicitly |
| * invalidating it is not required. Whether to invalidate I-cache |
| * or not is decided according to the value of the global |
| * "subarchitecture" variable (set in the bootstrap). |
| */ |
| set subarchitecture, %g2 |
| ldub [%g2], %g2 |
| cmp %g2, 3 |
| be 1f |
| nop |
| 0: |
| call icache_flush |
| nop |
| 1: |
| membar #StoreStore |
| |
| /* |
| * Flush the instruction pipeline. |
| */ |
| flush %i7 |
| |
| mov %o0, %l1 |
| mov %o1, %o0 |
| mov %o2, %o1 |
| 105,6 → 136,23 |
|---|
| jmp %l1 ! jump to kernel |
| nop |
| |
| #define ICACHE_SIZE 8192 |
| #define ICACHE_LINE_SIZE 32 |
| #define ICACHE_SET_BIT (1 << 13) |
| #define ASI_ICACHE_TAG 0x67 |
| |
| # Flush I-cache |
| icache_flush: |
| set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 |
| stxa %g0, [%g1] ASI_ICACHE_TAG |
| 0: membar #Sync |
| subcc %g1, ICACHE_LINE_SIZE, %g1 |
| bnz,pt %xcc, 0b |
| stxa %g0, [%g1] ASI_ICACHE_TAG |
| membar #Sync |
| retl |
| ! SF Erratum #51 |
| nop |
| .global ofw |
| ofw: |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |