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Ignore whitespace Rev 2240 → Rev 2241

/branches/arm/kernel/arch/arm32/include/types.h
1,5 → 1,5
/*
* Copyright (c) 2003-2007 Jakub Jermar
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
68,27 → 68,37
typedef int32_t inr_t;
typedef int32_t devno_t;
 
/** Page Table Entry. */
/** Page table entry.
*
* We have different structs for level 0 and level 1 page table entries.
* */
typedef struct {
/**PageTables are so different that we have different types
* for level 0 and level1 page table entries
*/
unsigned dummy : 32;
} pte_t;
 
/** Level 0 page table entry. */
typedef struct {
/* 01b for coarse tables, see below for details */
unsigned descriptor_type : 2;
unsigned machine_depend : 3; // Alf: ???? v Architecture previev neni vyznam definovan
unsigned impl_specific : 3;
unsigned domain : 4;
unsigned should_be_zero : 1;
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
* or large (64KB) pages. ARM also supports fine 2nd level page tables that
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
* with 1KB per the coarse table)
*/
unsigned coarse_table_addr : 22;
} __attribute__ ((packed)) pte_level0_t;
 
//TODO Alf: Comments
/** Level 1 page table entry (small (4KB) pages used) */
typedef struct {
/* 0b10 for small pages */
unsigned descriptor_type : 2;
unsigned bufferable : 1;
unsigned cacheable : 1;
/* access permissions for each of 4 subparts of a page
* (for each 1KB when small pages used */
unsigned access_permission_0 : 2;
unsigned access_permission_1 : 2;
unsigned access_permission_2 : 2;
96,23 → 106,29
unsigned frame_base_addr : 20;
} __attribute__ ((packed)) pte_level1_t;
 
/// Page table level 1 access permission constants
/// User no acess, kernel no access
 
/* Level 1 page tables access permissions */
 
/** User mode: no access, privileged mode: no access */
#define pte_ap_user_no_kernel_no 0
/// User no acess, kernel read/write
/** User mode: no access, privileged mode: read/write */
#define pte_ap_user_no_kernel_rw 1
/// User read only, kernel read/write
/** User mode: read only, privileged mode: read/write */
#define pte_ap_user_ro_kernel_rw 2
/// User read/write, kernel read/write
#define pte_ap_user_rw_kernel_rw 2
/// User mode: read/write, privileged mode: read/write
#define pte_ap_user_rw_kernel_rw 3
 
/// Value of descriptor_type in pte_level0_t and pte_level1_t that signal not present flag
#define pte_descriptor_not_preset 0
/// Value of descriptor_type in pte_level0_t that signal a coarse page table format
 
/* pte_level0_t and pte_level1_t descriptor_type flags */
 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
#define pte_descriptor_not_preset 0
/** pte_level0_t coarse page table flag (used in descriptor_type) */
#define pte_descriptor_coarse_table 1
/// Value of descriptor_type in pte_level1_t that signal a small page table entry format
#define pte_descriptor_small_page 2
/** pte_level1_t small page table flag (used in descriptor type) */
#define pte_descriptor_small_page 2
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/mm/page.h
55,16 → 55,17
 
#ifdef KERNEL
 
// "small" pages (4KB) used
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH (2<<8) // 256
 
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
#define PTL2_INDEX_ARCH(vaddr) 0
/* TODO: ?? 0xfff or 0x0ff */
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0xfff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
88,17 → 89,22
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type )
// pte should point into ptl3
// TODO: ?? != 0
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
// pte should point into ptl3
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw )
 
#define PTE_EXECUTABLE_ARCH(pte) 1
 
#ifndef __ASM__
 
/** Sets the address of level 0 page table.
* \param pt pointer to the page table to set
/**
* Sets the address of level 0 page table.
*
* \param pt pointer to the page table to set
*/
static inline void set_ptl0_addr( pte_level0_t* pt)
{
109,7 → 115,12
}
 
//TODO Comment: Page table structure as in other architectures
/**
* Returns level 0 page table entry flags.
*
* \param pt level 0 page table
* \param i index of the entry to return
*/
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
pte_level0_t *p = &pt[i];
116,15 → 127,23
 
return (
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
( 1 << PAGE_READ_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE )
( 1 << PAGE_USER_SHIFT ) |
( 1 << PAGE_READ_SHIFT ) |
( 1 << PAGE_WRITE_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE_SHIFT )
);
}
 
/**
* Returns level 1 page table entry flags.
*
* \param pt level 1 page table
* \param i index of the entry to return
*/
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
pte_level1_t *p = &pt[i];
pte_level1_t *p = &pt[i];
 
return (
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
133,18 → 152,24
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( p->bufferable << PAGE_CACHEABLE )
( p->bufferable << PAGE_CACHEABLE )
);
 
}
 
/**
* Sets flags of level 0 page table entry.
*
* \param pt level 0 page table
* \param i index of the entry to be changed
* \param flags new flags
*
* TODO: why should_be_zero set to 1?
*/
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
pte_level0_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = pte_descriptor_not_preset;
p->should_be_zero = 1;
} else {
153,34 → 178,42
}
}
 
/* TODO: rewrite comment: We use same acess rights for whole page, so if page is set as not preset then
* in acess_rigts_3 set value 1
/**
* Sets flags of level 1 page table entry.
*
* We use same access rights for the whole page. When page is not preset then
* store 1 in acess_rigts_3.
* TODO: why access_right_3?
*
* \param pt level 1 page table
* \param i index of the entry to be changed
* \param flags new flags
*/
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
pte_level1_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = pte_descriptor_not_preset;
p->access_permission_3 = 1;
} else {
p->descriptor_type = pte_descriptor_coarse_table;
p->descriptor_type = pte_descriptor_small_page;
p->access_permission_3 = p->access_permission_0;
}
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 
// default kernel rw, user none
/* default access permission */
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
 
if ( flags & PAGE_USER ) {
if ( flags & PAGE_READ ) {
if (flags & PAGE_USER) {
if (flags & PAGE_READ) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_ro_kernel_rw;
}
if ( flags & PAGE_WRITE ) {
if (flags & PAGE_WRITE) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_rw_kernel_rw;
/branches/arm/boot/arch/arm32/loader/mm.h
76,10 → 76,10
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
* pages). Used only for booting the kernel. */
typedef struct {
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION (0b10)
unsigned bufferable : 1;
unsigned cacheable : 1;
unsigned machine_depend : 1;
unsigned impl_specific : 1;
unsigned domain : 4;
unsigned should_be_zero_1 : 1;
unsigned access_permission : 2;
/branches/arm/boot/arch/arm32/loader/mm.c
47,7 → 47,7
pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
pte->bufferable = 0; // disable
pte->cacheable = 0;
pte->machine_depend = 0;
pte->impl_specific = 0;
pte->domain = 0;
pte->should_be_zero_1 = 0;
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;