37,21 → 37,52 |
#ifndef KERN_arm32_REGUTILS_H_ |
#define KERN_arm32_REGUTILS_H_ |
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#define status_reg_ie_enabled_bit (1 << 7) |
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#define STATUS_REG_IE_ENABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1F |
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/* ARM Processor Operation Modes */ |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
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/* [CS]PRS manipulation macros */ |
#define GEN_STATUS_READ(nm,reg) \ |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm("mrs %0, " #reg : "=r"(retval)); \ |
return retval; \ |
} |
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#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
static void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
} |
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/** Returns the value of CPSR (Current Program Status Register). |
*/ |
static inline ipl_t status_reg_read (void) { |
ipl_t ipl; |
asm("mrs %0, CPSR" : "=r" (ipl)); |
return ipl; |
} |
GEN_STATUS_READ(current, cpsr) |
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/** Sets control bits of CPSR |
*/ |
static inline void status_reg_control_write(ipl_t ipl) { |
asm("msr CPSR_c, %0" : : "r" (ipl)); |
} |
GEN_STATUS_WRITE(current, cpsr, control, c); |
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/** Returns the value of SPSR (Saved Program Status Register). |
*/ |
GEN_STATUS_READ(saved, spsr) |
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#endif |
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