44,6 → 44,7 |
#include <arch/machine.h> |
#include <arch/debug/print.h> |
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/** Address of devices. */ |
#define GXEMUL_VIDEORAM 0x10000000 |
#define GXEMUL_KBD 0x10000000 |
56,6 → 57,7 |
#define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
#define GXEMUL_MP 0x11000000 |
#define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
#define GXEMUL_FB 0x12000000 |
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/** IRQs */ |
81,7 → 83,30 |
.read = gxemul_do_read, |
}; |
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/** Return the mask of active interrupts. */ |
static inline uint32_t gxemul_irqc_get_sources(void) |
{ |
return *(uint32_t*) gxemul_hw_map.irqc; |
} |
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/** Masks interrupt. |
* |
* @param irq interrupt number |
*/ |
static inline void gxemul_irqc_mask(uint32_t irq) |
{ |
*(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
} |
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/** Unmasks interrupt. |
* |
* @param irq interrupt number |
*/ |
static inline void gxemul_irqc_unmask(uint32_t irq) |
{ |
*(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
} |
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/** Initializes #gxemul_hw_map. */ |
void machine_hw_map_init(void) |
{ |
99,22 → 124,20 |
} |
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/** Putchar that works with gxemul */ |
void gxemul_write(chardev_t *dev, const char ch) |
static void gxemul_write(chardev_t *dev, const char ch) |
{ |
*((char *) gxemul_hw_map.videoram) = ch; |
} |
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/* Called from getc(). */ |
void gxemul_enable(chardev_t *dev) |
static void gxemul_enable(chardev_t *dev) |
{ |
// cp0_unmask_int(GXEMUL_KBD_IRQ); |
gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
} |
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/* Called from getc(). */ |
void gxemul_disable(chardev_t *dev) |
static void gxemul_disable(chardev_t *dev) |
{ |
// cp0_mask_int(GXEMUL_KBD_IRQ); |
gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
} |
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191,7 → 214,6 |
gxemul_irq.handler = gxemul_irq_handler; |
irq_register(&gxemul_irq); |
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// cp0_unmask_int(GXEMUL_KBD_IRQ); |
gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
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sysinfo_set_item_val("kbd", NULL, true); |
200,36 → 222,13 |
sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
} |
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/** Return the mask of active interrupts. */ |
inline uint32_t gxemul_irqc_get_sources(void) |
{ |
return *(uint32_t*) gxemul_hw_map.irqc; |
} |
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/** Masks interrupt. |
* |
* @param irq interrupt number |
*/ |
inline void gxemul_irqc_mask(uint32_t irq) |
{ |
*(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
} |
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/** Unmasks interrupt. |
* |
* @param irq interrupt number |
*/ |
inline void gxemul_irqc_unmask(uint32_t irq) |
{ |
*(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
} |
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/** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
* |
* @param frequency interrupts frequency (0 disables RTC) |
*/ |
void gxemul_timer_start(uint32_t frequency) |
static void gxemul_timer_start(uint32_t frequency) |
{ |
*(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
} |
273,7 → 272,7 |
/** |
* Initializes and registers timer interrupt handler. |
*/ |
void gxemul_timer_irq_init() |
static void gxemul_timer_irq_init() |
{ |
irq_initialize(&gxemul_timer_irq); |
gxemul_timer_irq.devno = device_assign_devno(); |
321,6 → 320,24 |
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void machine_irq_exception(int exc_no, istate_t *istate) |
{ |
/* switch to Undefined mode */ |
/* |
asm volatile( |
"stmfd sp!, {r0-r3}\n" |
"mov r1, sp\n" |
"mov r2, lr\n" |
"mrs r3, spsr\n" |
"mrs r0, cpsr\n" |
"bic r0, r0, #0x1f\n" |
"orr r0, r0, #0x1b\n" |
"msr cpsr_c, r0\n" |
"mov sp, r1\n" |
"mov lr, r2\n" |
"msr spsr, r3\n" |
"ldmfd sp!, {r0-r3}\n" |
); |
*/ |
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uint32_t sources = gxemul_irqc_get_sources(); |
int i = 0; |
for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
360,5 → 377,6 |
aux_puts("IRQ exception without source\n");*/ |
} |
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/** @} |
*/ |