55,16 → 55,17 |
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#ifdef KERNEL |
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// "small" pages (4KB) used |
#define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
/* coarse page tables used (256*4 = 1KB per page) */ |
#define PTL3_ENTRIES_ARCH (2<<8) // 256 |
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#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
#define PTL2_INDEX_ARCH(vaddr) 0 |
/* TODO: ?? 0xfff or 0x0ff */ |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0xfff) |
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
88,17 → 89,22 |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
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#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
// pte should point into ptl3 |
// TODO: ?? != 0 |
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
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/* pte should point into ptl3 */ |
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
// pte should point into ptl3 |
/* pte should point into ptl3 */ |
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) |
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#define PTE_EXECUTABLE_ARCH(pte) 1 |
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#ifndef __ASM__ |
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/** Sets the address of level 0 page table. |
* \param pt pointer to the page table to set |
/** |
* Sets the address of level 0 page table. |
* |
* \param pt pointer to the page table to set |
*/ |
static inline void set_ptl0_addr( pte_level0_t* pt) |
{ |
109,7 → 115,12 |
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} |
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//TODO Comment: Page table structure as in other architectures |
/** |
* Returns level 0 page table entry flags. |
* |
* \param pt level 0 page table |
* \param i index of the entry to return |
*/ |
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
{ |
pte_level0_t *p = &pt[i]; |
116,15 → 127,23 |
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return ( |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( 1 << PAGE_READ_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( 1 << PAGE_CACHEABLE ) |
( 1 << PAGE_USER_SHIFT ) | |
( 1 << PAGE_READ_SHIFT ) | |
( 1 << PAGE_WRITE_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( 1 << PAGE_CACHEABLE_SHIFT ) |
); |
} |
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/** |
* Returns level 1 page table entry flags. |
* |
* \param pt level 1 page table |
* \param i index of the entry to return |
*/ |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
{ |
pte_level1_t *p = &pt[i]; |
pte_level1_t *p = &pt[i]; |
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return ( |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
133,18 → 152,24 |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( p->bufferable << PAGE_CACHEABLE ) |
|
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( p->bufferable << PAGE_CACHEABLE ) |
); |
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} |
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/** |
* Sets flags of level 0 page table entry. |
* |
* \param pt level 0 page table |
* \param i index of the entry to be changed |
* \param flags new flags |
* |
* TODO: why should_be_zero set to 1? |
*/ |
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
{ |
pte_level0_t *p = &pt[i]; |
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if ( flags & PAGE_NOT_PRESENT ) { |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = pte_descriptor_not_preset; |
p->should_be_zero = 1; |
} else { |
153,34 → 178,42 |
} |
} |
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/* TODO: rewrite comment: We use same acess rights for whole page, so if page is set as not preset then |
* in acess_rigts_3 set value 1 |
/** |
* Sets flags of level 1 page table entry. |
* |
* We use same access rights for the whole page. When page is not preset then |
* store 1 in acess_rigts_3. |
* TODO: why access_right_3? |
* |
* \param pt level 1 page table |
* \param i index of the entry to be changed |
* \param flags new flags |
*/ |
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
{ |
pte_level1_t *p = &pt[i]; |
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if ( flags & PAGE_NOT_PRESENT ) { |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = pte_descriptor_not_preset; |
p->access_permission_3 = 1; |
} else { |
p->descriptor_type = pte_descriptor_coarse_table; |
p->descriptor_type = pte_descriptor_small_page; |
p->access_permission_3 = p->access_permission_0; |
} |
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p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
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// default kernel rw, user none |
/* default access permission */ |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw; |
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if ( flags & PAGE_USER ) { |
if ( flags & PAGE_READ ) { |
if (flags & PAGE_USER) { |
if (flags & PAGE_READ) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
pte_ap_user_ro_kernel_rw; |
} |
if ( flags & PAGE_WRITE ) { |
if (flags & PAGE_WRITE) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
pte_ap_user_rw_kernel_rw; |