WebSVN – HelenOS – Path Comparison – / – /branches/arm/kernel/arch/sparc64/src Rev 4641 and /branches/arm/kernel/arch/sparc64/src Rev 4647

Ignore whitespace Rev 4641 → Rev 4647

 /branches/arm/kernel/arch/sparc64/src/asm.S
 ,10 → 225,15
 .global memsetb
 memsetb:
-    b _memsetb
+    ba %xcc, _memsetb
     nop
+.global memsetw
+memsetw:
+    ba %xcc, _memsetw
+    nop
 .macro WRITE_ALTERNATE_REGISTER reg, bit
     rdpr %pstate, %g1               ! save PSTATE.PEF
     wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
 ,7 → 277,7
  */
 .global switch_to_userspace
 switch_to_userspace:
-    save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
+    save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
     flushw
     wrpr %g0, 0, %cleanwin      ! avoid information leak

 /branches/arm/kernel/arch/sparc64/src/smp/smp.c
 ,6 → 35,7
 #include <smp/smp.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <cpu.h>
+#include <arch/cpu_family.h>
 #include <arch/cpu.h>
 #include <arch.h>
 #include <config.h>
 ,6 → 44,7
 #include <synch/synch.h>
 #include <synch/waitq.h>
 #include <print.h>
+#include <arch/cpu_node.h>
 /**
  * This global variable is used to pick-up application processors
 ,17 → 61,57
 void smp_init(void)
 {
     ofw_tree_node_t *node;
-    count_t cnt = 0;
+    size_t cnt = 0;
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    while (node) {
-        cnt++;
-        node = ofw_tree_find_peer_by_device_type(node, "cpu");
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        while (node) {
+            cnt++;
+            node = ofw_tree_find_peer_by_device_type(node, "cpu");
+        }
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            cnt += 2;
+            node = ofw_tree_find_peer_by_name(node, "cmp");
+        }
     }
     config.cpu_count = max(1, cnt);
 }
+/**
+ * Wakes up the CPU which is represented by the "node" OFW tree node.
+ * If "node" represents the current CPU, calling the function has
+ * no effect.
+ */
+static void wakeup_cpu(ofw_tree_node_t *node)
+{
+    uint32_t mid;
+    ofw_tree_property_t *prop;
+    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
+    prop = ofw_tree_getprop(node, "upa-portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "cpuid");
+    if (!prop || prop->value == NULL)
+        return;
+    mid = *((uint32_t *) prop->value);
+    if (CPU->arch.mid == mid)
+        return;
+    waking_up_mid = mid;
+    if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) ==
+        ESYNCH_TIMEOUT)
+        printf("%s: waiting for processor (mid = %" PRIu32
+            ") timed out\n", __func__, mid);
+}
 /** Wake application processors up. */
 void kmp(void *arg)
 {
 ,31 → 118,18
     ofw_tree_node_t *node;
     int i;
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    for (i = 0; node; node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++) {
-        uint32_t mid;
-        ofw_tree_property_t *prop;
-        prop = ofw_tree_getprop(node, "upa-portid");
-        if (!prop || !prop->value)
-            continue;
-        mid = *((uint32_t *) prop->value);
-        if (CPU->arch.mid == mid) {
-            /*
-             * Skip the current CPU.
-             */
-            continue;
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        for (i = 0; node;
+                     node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++)
+            wakeup_cpu(node);
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            wakeup_cpu(ofw_tree_find_child(node, "cpu@0"));
+            wakeup_cpu(ofw_tree_find_child(node, "cpu@1"));
+            node = ofw_tree_find_peer_by_name(node, "cmp");
         }
-        /*
-         * Processor with ID == mid can proceed with its initialization.
-         */
-        waking_up_mid = mid;
-        if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT)
-            printf("%s: waiting for processor (mid = %" PRIu32 ") timed out\n",
-                __func__, mid);
     }
 }

 /branches/arm/kernel/arch/sparc64/src/smp/ipi.c
 ,6 → 46,33
 #include <time/delay.h>
 #include <panic.h>
+/** Set the contents of the outgoing interrupt vector data.
+ *
+ * The first data item (data 0) will be set to the value of func, the
+ * rest of the vector will contain zeros.
+ *
+ * This is a helper function used from within the cross_call function.
+ *
+ * @param func value the first data item of the vector will be set to
+ */
+static inline void set_intr_w_data(void (* func)(void))
+{
+#if defined (US)
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
+    asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
+#elif defined (US3)
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t) func);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
+    asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
+#endif
+}
 /** Invoke function on another processor.
  *
  * Currently, only functions without arguments are supported.
 ,16 → 98,15
     status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
     if (status & INTR_DISPATCH_STATUS_BUSY)
-        panic("Interrupt Dispatch Status busy bit set\n");
+        panic("Interrupt Dispatch Status busy bit set.");
+    ASSERT(!(pstate_read() & PSTATE_IE_BIT));
     do {
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0,
-            (uintptr_t) func);
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
-        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
-        asi_u64_write(ASI_UDB_INTR_W,
+        set_intr_w_data(func);
+        asi_u64_write(ASI_INTR_W,
             (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
-            ASI_UDB_INTR_W_DISPATCH, 0);
+            VA_INTR_W_DISPATCH, 0);
         membar();
 ,7 → 151,7
         func = tlb_shootdown_ipi_recv;
         break;
     default:
-        panic("Unknown IPI (%d).\n", ipi);
+        panic("Unknown IPI (%d).", ipi);
         break;
     }

 /branches/arm/kernel/arch/sparc64/src/mm/tlb.c
 ,14 → 54,13
 #include <arch/mm/tsb.h>
 #endif
-static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
-static void itlb_pte_copy(pte_t *t, index_t index);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
-    const char *str);
-static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str);
-static void do_fast_data_access_protection_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str);
+static void dtlb_pte_copy(pte_t *, size_t, bool);
+static void itlb_pte_copy(pte_t *, size_t);
+static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
+static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
+    const char *);
+static void do_fast_data_access_protection_fault(istate_t *,
+    tlb_tag_access_reg_t, const char *);
 char *context_encoding[] = {
     "Primary",
 ,11 → 85,11
 /** Insert privileged mapping into DMMU TLB.
  *
- * @param page Virtual page address.
- * @param frame Physical frame address.
- * @param pagesize Page size.
- * @param locked True for permanent mappings, false otherwise.
- * @param cacheable True if the mapping is cacheable, false otherwise.
+ * @param page      Virtual page address.
+ * @param frame     Physical frame address.
+ * @param pagesize  Page size.
+ * @param locked    True for permanent mappings, false otherwise.
+ * @param cacheable True if the mapping is cacheable, false otherwise.
  */
 void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
     bool locked, bool cacheable)
 ,7 → 102,7
     pg.address = page;
     fr.address = frame;
-    tag.value = ASID_KERNEL;
+    tag.context = ASID_KERNEL;
     tag.vpn = pg.vpn;
     dtlb_tag_access_write(tag.value);
 ,12 → 125,12
 /** Copy PTE to TLB.
  *
- * @param t     Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
- * @param ro    If true, the entry will be created read-only, regardless of its
- *      w field.
+ * @param t         Page Table Entry to be copied.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param ro        If true, the entry will be created read-only, regardless
+ *          of its w field.
  */
-void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
+void dtlb_pte_copy(pte_t *t, size_t index, bool ro)
 {
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
 ,10 → 164,10
 /** Copy PTE to ITLB.
  *
- * @param t     Page Table Entry to be copied.
- * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param t     Page Table Entry to be copied.
+ * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
  */
-void itlb_pte_copy(pte_t *t, index_t index)
+void itlb_pte_copy(pte_t *t, size_t index)
 {
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
 ,12 → 199,12
 /** ITLB miss handler. */
 void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
 {
-    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
-    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
+    uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
+    size_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
     pte_t *t;
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, va);
+    t = page_mapping_find(AS, page_16k);
     if (t && PTE_EXECUTABLE(t)) {
         /*
          * The mapping was found in the software page hash table.
 ,7 → 222,8
          * handler.
          */
         page_table_unlock(AS, true);
-        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+        if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) ==
+            AS_PF_FAULT) {
             do_fast_instruction_access_mmu_miss_fault(istate,
                 __func__);
         }
 ,18 → 235,21
  * Note that some faults (e.g. kernel faults) were already resolved by the
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param tag Content of the TLB Tag Access register as it existed when the
- *    trap happened. This is to prevent confusion created by clobbered
- *    Tag Access register during a nested DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param tag       Content of the TLB Tag Access register as it existed
+ *          when the trap happened. This is to prevent confusion
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
 {
-    uintptr_t va;
-    index_t index;
+    uintptr_t page_8k;
+    uintptr_t page_16k;
+    size_t index;
     pte_t *t;
-    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
+    page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
+    page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE);
     index = tag.vpn % MMU_PAGES_PER_PAGE;
     if (tag.context == ASID_KERNEL) {
 ,6 → 257,15
             /* NULL access in kernel */
             do_fast_data_access_mmu_miss_fault(istate, tag,
                 __func__);
+        } else if (page_8k >= end_of_identity) {
+            /*
+             * The kernel is accessing the I/O space.
+             * We still do identity mapping for I/O,
+             * but without caching.
+             */
+            dtlb_insert_mapping(page_8k, KA2PA(page_8k),
+                PAGESIZE_8K, false, false);
+            return;
         }
         do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
             "kernel page fault.");
 ,7 → 272,7
     }
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, va);
+    t = page_mapping_find(AS, page_16k);
     if (t) {
         /*
          * The mapping was found in the software page hash table.
 ,7 → 290,8
          * handler.
          */
         page_table_unlock(AS, true);
-        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+        if (as_page_fault(page_16k, PF_ACCESS_READ, istate) ==
+            AS_PF_FAULT) {
             do_fast_data_access_mmu_miss_fault(istate, tag,
                 __func__);
         }
 ,22 → 300,23
 /** DTLB protection fault handler.
  *
- * @param tag Content of the TLB Tag Access register as it existed when the
- *    trap happened. This is to prevent confusion created by clobbered
- *    Tag Access register during a nested DTLB miss.
- * @param istate Interrupted state saved on the stack.
+ * @param tag       Content of the TLB Tag Access register as it existed
+ *          when the trap happened. This is to prevent confusion
+ *          created by clobbered Tag Access register during a nested
+ *          DTLB miss.
+ * @param istate    Interrupted state saved on the stack.
  */
 void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
 {
-    uintptr_t va;
-    index_t index;
+    uintptr_t page_16k;
+    size_t index;
     pte_t *t;
-    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
+    page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
     index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
     page_table_lock(AS, true);
-    t = page_mapping_find(AS, va);
+    t = page_mapping_find(AS, page_16k);
     if (t && PTE_WRITABLE(t)) {
         /*
          * The mapping was found in the software page hash table and is
 ,7 → 326,7
         t->a = true;
         t->d = true;
         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
-            va + index * MMU_PAGE_SIZE);
+            page_16k + index * MMU_PAGE_SIZE);
         dtlb_pte_copy(t, index, false);
 #ifdef CONFIG_TSB
         dtsb_pte_copy(t, index, false);
 ,7 → 338,8
          * handler.
          */
         page_table_unlock(AS, true);
-        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+        if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) ==
+            AS_PF_FAULT) {
             do_fast_data_access_protection_fault(istate, tag,
                 __func__);
         }
 ,6 → 346,26
     }
 }
+/** Print TLB entry (for debugging purposes).
+ *
+ * The diag field has been left out in order to make this function more generic
+ * (there is no diag field in US3 architeture).
+ *
+ * @param i     TLB entry number
+ * @param t     TLB entry tag
+ * @param d     TLB entry data
+ */
+static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
+{
+    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
+        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
+        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
+        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
+        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+}
+#if defined (US)
 /** Print contents of both TLBs. */
 void tlb_print(void)
 {
 ,12 → 377,7
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         t.value = itlb_tag_read_read(i);
-        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
-            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+        print_tlb_entry(i, t, d);
     }
     printf("D-TLB contents:\n");
 ,22 → 384,63
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         t.value = dtlb_tag_read_read(i);
-        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
-            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+        print_tlb_entry(i, t, d);
     }
+}
+#elif defined (US3)
+/** Print contents of all TLBs. */
+void tlb_print(void)
+{
+    int i;
+    tlb_data_t d;
+    tlb_tag_read_reg_t t;
+    printf("TLB_ISMALL contents:\n");
+    for (i = 0; i < tlb_ismall_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_ISMALL, i);
+        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_IBIG contents:\n");
+    for (i = 0; i < tlb_ibig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_IBIG, i);
+        t.value = dtlb_tag_read_read(TLB_IBIG, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DSMALL contents:\n");
+    for (i = 0; i < tlb_dsmall_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DSMALL, i);
+        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DBIG_1 contents:\n");
+    for (i = 0; i < tlb_dbig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
+        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
+        print_tlb_entry(i, t, d);
+    }
+    printf("TLB_DBIG_2 contents:\n");
+    for (i = 0; i < tlb_dbig_size(); i++) {
+        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
+        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
+        print_tlb_entry(i, t, d);
+    }
 }
+#endif
 void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
     const char *str)
 {
-    fault_if_from_uspace(istate, "%s\n", str);
+    fault_if_from_uspace(istate, "%s.", str);
     dump_istate(istate);
-    panic("%s\n", str);
+    panic("%s.", str);
 }
 void do_fast_data_access_mmu_miss_fault(istate_t *istate,
 ,12 → 450,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
             tag.context);
     }
     dump_istate(istate);
-    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
-    panic("%s\n", str);
+    printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
+    panic("%s.", str);
 }
 void do_fast_data_access_protection_fault(istate_t *istate,
 ,12 → 466,12
     va = tag.vpn << MMU_PAGE_WIDTH;
     if (tag.context) {
-        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
             tag.context);
     }
     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
     dump_istate(istate);
-    panic("%s\n", str);
+    panic("%s.", str);
 }
 void dump_sfsr_and_sfar(void)
 ,30 → 482,39
     sfsr.value = dtlb_sfsr_read();
     sfar = dtlb_sfar_read();
+#if defined (US)
     printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
         "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
         sfsr.ow, sfsr.fv);
+#elif defined (US3)
+    printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
+        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
+        sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
+#endif
     printf("DTLB SFAR: address=%p\n", sfar);
     dtlb_sfsr_write(0);
 }
+#if defined (US)
 /** Invalidate all unlocked ITLB and DTLB entries. */
 void tlb_invalidate_all(void)
 {
     int i;
-    tlb_data_t d;
-    tlb_tag_read_reg_t t;
     /*
      * Walk all ITLB and DTLB entries and remove all unlocked mappings.
      *
      * The kernel doesn't use global mappings so any locked global mappings
-     * found  must have been created by someone else. Their only purpose now
+     * found must have been created by someone else. Their only purpose now
      * is to collide with proper mappings. Invalidate immediately. It should
      * be safe to invalidate them as late as now.
      */
+    tlb_data_t d;
+    tlb_tag_read_reg_t t;
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         if (!d.l || d.g) {
 ,7 → 524,7
             itlb_data_access_write(i, d.value);
         }
     }
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         if (!d.l || d.g) {
 ,9 → 534,20
             dtlb_data_access_write(i, d.value);
         }
     }
 }
+#elif defined (US3)
+/** Invalidate all unlocked ITLB and DTLB entries. */
+void tlb_invalidate_all(void)
+{
+    itlb_demap(TLB_DEMAP_ALL, 0, 0);
+    dtlb_demap(TLB_DEMAP_ALL, 0, 0);
+}
+#endif
 /** Invalidate all ITLB and DTLB entries that belong to specified ASID
  * (Context).
  *
 ,11 → 575,11
 /** Invalidate all ITLB and DTLB entries for specified page range in specified
  * address space.
  *
- * @param asid Address Space ID.
- * @param page First page which to sweep out from ITLB and DTLB.
- * @param cnt Number of ITLB and DTLB entries to invalidate.
+ * @param asid      Address Space ID.
+ * @param page      First page which to sweep out from ITLB and DTLB.
+ * @param cnt       Number of ITLB and DTLB entries to invalidate.
  */
-void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
+void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
 {
     unsigned int i;
     tlb_context_reg_t pc_save, ctx;

 /branches/arm/kernel/arch/sparc64/src/mm/as.c
 ,7 → 89,7
      * The count must be calculated with respect to the emualted 16K page
      * size.
      */
-    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
+    size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
         sizeof(tsb_entry_t)) >> FRAME_WIDTH;
     frame_free(KA2PA((uintptr_t) as->arch.itsb));
     return cnt;
 ,7 → 101,7
 int as_create_arch(as_t *as, int flags)
 {
 #ifdef CONFIG_TSB
-    tsb_invalidate(as, 0, (count_t) -1);
+    tsb_invalidate(as, 0, (size_t) -1);
 #endif
     return 0;
 }
 ,7 → 164,25
     itsb_base_write(tsb_base.value);
     tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
     dtsb_base_write(tsb_base.value);
+#if defined (US3)
+    /*
+     * Clear the extension registers.
+     * In HelenOS, primary and secondary context registers contain
+     * equal values and kernel misses (context 0, ie. the nucleus context)
+     * are excluded from the TSB miss handler, so it makes no sense
+     * to have separate TSBs for primary, secondary and nucleus contexts.
+     * Clearing the extension registers will ensure that the value of the
+     * TSB Base register will be used as an address of TSB, making the code
+     * compatible with the US port.
+     */
+    itsb_primary_extension_write(0);
+    itsb_nucleus_extension_write(0);
+    dtsb_primary_extension_write(0);
+    dtsb_secondary_extension_write(0);
+    dtsb_nucleus_extension_write(0);
 #endif
+#endif
 }
 /** Perform sparc64-specific tasks when an address space is removed from the

 /branches/arm/kernel/arch/sparc64/src/mm/tsb.c
 ,13 → 50,14
  *
  * @param as Address space.
  * @param page First page to invalidate in TSB.
- * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
+ * @param pages Number of pages to invalidate. Value of (size_t) -1 means the
  *  whole TSB.
  */
-void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
+void tsb_invalidate(as_t *as, uintptr_t page, size_t pages)
 {
-    index_t i0, i;
-    count_t cnt;
+    size_t i0;
+    size_t i;
+    size_t cnt;
     ASSERT(as->arch.itsb && as->arch.dtsb);
 ,7 → 64,7
     i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
     ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
-    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
+    if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
         cnt = ITSB_ENTRY_COUNT;
     else
         cnt = pages * 2;
 ,11 → 82,11
  * @param t     Software PTE.
  * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
  */
-void itsb_pte_copy(pte_t *t, index_t index)
+void itsb_pte_copy(pte_t *t, size_t index)
 {
     as_t *as;
     tsb_entry_t *tsb;
-    index_t entry;
+    size_t entry;
     ASSERT(index <= 1);
 ,9 → 113,9
     tsb->data.value = 0;
     tsb->data.size = PAGESIZE_8K;
     tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-    tsb->data.cp = t->c;
-    tsb->data.p = t->k;     /* p as privileged */
-    tsb->data.v = t->p;
+    tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
+    tsb->data.p = t->k; /* p as privileged, k as kernel */
+    tsb->data.v = t->p; /* v as valid, p as present */
     write_barrier();
 ,11 → 128,11
  * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
  * @param ro    If true, the mapping is copied read-only.
  */
-void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
+void dtsb_pte_copy(pte_t *t, size_t index, bool ro)
 {
     as_t *as;
     tsb_entry_t *tsb;
-    index_t entry;
+    size_t entry;
     ASSERT(index <= 1);
 ,3 → 174,4
 /** @}
  */

 /branches/arm/kernel/arch/sparc64/src/mm/page.c
 ,5 → 1,5
 /*
- * Copyright (c) 2005 Jakub Jermar
+ * Copyright (c) 2009 Jakub Jermar
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,126 → 42,27
 #include <align.h>
 #include <config.h>
-#ifdef CONFIG_SMP
-/** Entries locked in DTLB of BSP.
- *
- * Application processors need to have the same locked entries in their DTLBs as
- * the bootstrap processor.
- */
-static struct {
-    uintptr_t virt_page;
-    uintptr_t phys_page;
-    int pagesize_code;
-} bsp_locked_dtlb_entry[DTLB_ENTRY_COUNT];
-/** Number of entries in bsp_locked_dtlb_entry array. */
-static count_t bsp_locked_dtlb_entries = 0;
-#endif /* CONFIG_SMP */
 /** Perform sparc64 specific initialization of paging. */
 void page_arch_init(void)
 {
-    if (config.cpu_active == 1) {
+    if (config.cpu_active == 1)
         page_mapping_operations = &ht_mapping_operations;
-    } else {
-#ifdef CONFIG_SMP
-        unsigned int i;
-        /*
-         * Copy locked DTLB entries from the BSP.
-         */
-        for (i = 0; i < bsp_locked_dtlb_entries; i++) {
-            dtlb_insert_mapping(bsp_locked_dtlb_entry[i].virt_page,
-                bsp_locked_dtlb_entry[i].phys_page,
-                bsp_locked_dtlb_entry[i].pagesize_code, true,
-                false);
-        }
-#endif
-    }
 }
 /** Map memory-mapped device into virtual memory.
  *
- * So far, only DTLB is used to map devices into memory. Chances are that there
- * will be only a limited amount of devices that the kernel itself needs to
- * lock in DTLB.
+ * We are currently using identity mapping for mapping device registers.
  *
- * @param physaddr Physical address of the page where the device is located.
- *  Must be at least page-aligned.
- * @param size Size of the device's registers. Must not exceed 4M and must
- *  include extra space caused by the alignment.
+ * @param physaddr Physical address of the page where the device is
+ *                 located.
+ * @param size     Size of the device's registers.
  *
  * @return Virtual address of the page where the device is mapped.
+ *
  */
 uintptr_t hw_map(uintptr_t physaddr, size_t size)
 {
-    unsigned int order;
-    unsigned int i;
-    ASSERT(config.cpu_active == 1);
-    struct {
-        int pagesize_code;
-        size_t increment;
-        count_t count;
-    } sizemap[] = {
-        { PAGESIZE_8K, 0, 1 },              /* 8K */
-        { PAGESIZE_8K, MMU_PAGE_SIZE, 2 },      /* 16K */
-        { PAGESIZE_8K, MMU_PAGE_SIZE, 4 },      /* 32K */
-        { PAGESIZE_64K, 0, 1},              /* 64K */
-        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 2 },     /* 128K */
-        { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 4 },     /* 256K */
-        { PAGESIZE_512K, 0, 1 },            /* 512K */
-        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 2 },   /* 1M */
-        { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 4 },   /* 2M */
-        { PAGESIZE_4M, 0, 1 },              /* 4M */
-        { PAGESIZE_4M, 512 * MMU_PAGE_SIZE, 2 }     /* 8M */
-    };
-    ASSERT(ALIGN_UP(physaddr, MMU_PAGE_SIZE) == physaddr);
-    ASSERT(size <= 8 * 1024 * 1024);
-    if (size <= MMU_FRAME_SIZE)
-        order = 0;
-    else
-        order = (fnzb64(size - 1) + 1) - MMU_FRAME_WIDTH;
-    /*
-     * Use virtual addresses that are beyond the limit of physical memory.
-     * Thus, the physical address space will not be wasted by holes created
-     * by frame_alloc().
-     */
-    ASSERT(PA2KA(last_frame));
-    uintptr_t virtaddr = ALIGN_UP(PA2KA(last_frame),
-<< (order + FRAME_WIDTH));
-    last_frame = ALIGN_UP(KA2PA(virtaddr) + size,
-<< (order + FRAME_WIDTH));
-    for (i = 0; i < sizemap[order].count; i++) {
-        /*
-         * First, insert the mapping into DTLB.
-         */
-        dtlb_insert_mapping(virtaddr + i * sizemap[order].increment,
-            physaddr + i * sizemap[order].increment,
-            sizemap[order].pagesize_code, true, false);
-#ifdef CONFIG_SMP
-        /*
-         * Second, save the information about the mapping for APs.
-         */
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].virt_page =
-            virtaddr + i * sizemap[order].increment;
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].phys_page =
-            physaddr + i * sizemap[order].increment;
-        bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].pagesize_code =
-            sizemap[order].pagesize_code;
-        bsp_locked_dtlb_entries++;
-#endif
-    }
-    return virtaddr;
+    return PA2KA(physaddr);
 }
 /** @}

 /branches/arm/kernel/arch/sparc64/src/mm/frame.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
 /** @file
 ,7 → 79,8
          */
         frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1);
     }
+    end_of_identity = PA2KA(last_frame);
 }
 /** @}

 /branches/arm/kernel/arch/sparc64/src/mm/cache.S
 ,45 → 47,3
     retl
     ! beware SF Erratum #51, do not put the MEMBAR here
     nop
-/** Flush only D-cache lines of one virtual color.
- *
- * @param o0    Virtual color to be flushed.
- */
-.global dcache_flush_color
-dcache_flush_color:
-    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
-    set DCACHE_SIZE / 2, %g2
-    sllx %g2, %o0, %g2
-    sub %g2, DCACHE_LINE_SIZE, %g2
-:  stxa %g0, [%g2] ASI_DCACHE_TAG
-    membar #Sync
-    subcc %g1, 1, %g1
-    bnz,pt %xcc, 0b
-    sub %g2, DCACHE_LINE_SIZE, %g2
-    retl
-    nop
-/** Flush only D-cache lines of one virtual color and one tag.
- *
- * @param o0    Virtual color to lookup the tag.
- * @param o1    Tag of the cachelines to be flushed.
- */
-.global dcache_flush_tag
-dcache_flush_tag:
-    mov (DCACHE_SIZE / DCACHE_LINE_SIZE) / 2, %g1
-    set DCACHE_SIZE / 2, %g2
-    sllx %g2, %o0, %g2
-    sub %g2, DCACHE_LINE_SIZE, %g2
-:  ldxa [%g2] ASI_DCACHE_TAG, %g3
-    srlx %g3, DCACHE_TAG_SHIFT, %g3
-    cmp %g3, %o1
-    bnz 1f
-    nop
-    stxa %g0, [%g2] ASI_DCACHE_TAG
-    membar #Sync
-:  subcc %g1, 1, %g1
-    bnz,pt %xcc, 0b
-    sub %g2, DCACHE_LINE_SIZE, %g2
-    retl
-    nop

 /branches/arm/kernel/arch/sparc64/src/drivers/fhc.c
 ,6 → 45,7
 #include <mm/slab.h>
 #include <arch/types.h>
 #include <genarch/ofw/ofw_tree.h>
+#include <sysinfo/sysinfo.h>
 fhc_t *central_fhc = NULL;
 ,7 → 71,7
     if (!prop || !prop->value)
         return NULL;
-    count_t regs = prop->size / sizeof(ofw_central_reg_t);
+    size_t regs = prop->size / sizeof(ofw_central_reg_t);
     if (regs + 1 < UART_IMAP_REG)
         return NULL;
 ,6 → 87,13
     fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
+    /*
+     * Set sysinfo data needed by the uspace FHC driver.
+     */
+    sysinfo_set_item_val("fhc.uart.size", NULL, reg->size);
+    sysinfo_set_item_val("fhc.uart.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.fhc", NULL, 1);
     return fhc;
 }
 ,13 → 104,14
         fhc->uart_imap[FHC_UART_IMAP] |= IMAP_V_MASK;
         break;
     default:
-        panic("Unexpected INR (%d)\n", inr);
+        panic("Unexpected INR (%d).", inr);
         break;
     }
 }
-void fhc_clear_interrupt(fhc_t *fhc, int inr)
+void fhc_clear_interrupt(void *fhcp, int inr)
 {
+    fhc_t *fhc = (fhc_t *)fhcp;
     ASSERT(fhc->uart_imap);
     switch (inr) {
 ,7 → 119,7
         fhc->uart_imap[FHC_UART_ICLR] = 0;
         break;
     default:
-        panic("Unexpected INR (%d)\n", inr);
+        panic("Unexpected INR (%d).", inr);
         break;
     }
 }

 /branches/arm/kernel/arch/sparc64/src/drivers/pci.c
 ,43 → 42,41
 #include <arch/types.h>
 #include <debug.h>
 #include <print.h>
-#include <func.h>
+#include <string.h>
 #include <arch/asm.h>
+#include <sysinfo/sysinfo.h>
-#define PCI_SABRE_REGS_REG  0
+#define SABRE_INTERNAL_REG  0
+#define PSYCHO_INTERNAL_REG 2
-#define PCI_SABRE_IMAP_BASE 0x200
-#define PCI_SABRE_ICLR_BASE 0x300
+#define OBIO_IMR_BASE   0x200
+#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
-#define PCI_PSYCHO_REGS_REG 2
+#define OBIO_CIR_BASE   0x300
+#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
-#define PCI_PSYCHO_IMAP_BASE    0x200
-#define PCI_PSYCHO_ICLR_BASE    0x300
+static void obio_enable_interrupt(pci_t *, int);
+static void obio_clear_interrupt(pci_t *, int);
-static pci_t *pci_sabre_init(ofw_tree_node_t *node);
-static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
-static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
+static pci_t *pci_sabre_init(ofw_tree_node_t *);
+static pci_t *pci_psycho_init(ofw_tree_node_t *);
-static pci_t *pci_psycho_init(ofw_tree_node_t *node);
-static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
-static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
 /** PCI operations for Sabre model. */
 static pci_operations_t pci_sabre_ops = {
-    .enable_interrupt = pci_sabre_enable_interrupt,
-    .clear_interrupt = pci_sabre_clear_interrupt
+    .enable_interrupt = obio_enable_interrupt,
+    .clear_interrupt = obio_clear_interrupt
 };
 /** PCI operations for Psycho model. */
 static pci_operations_t pci_psycho_ops = {
-    .enable_interrupt = pci_psycho_enable_interrupt,
-    .clear_interrupt = pci_psycho_clear_interrupt
+    .enable_interrupt = obio_enable_interrupt,
+    .clear_interrupt = obio_clear_interrupt
 };
 /** Initialize PCI controller (model Sabre).
  *
- * @param node OpenFirmware device tree node of the Sabre.
+ * @param node      OpenFirmware device tree node of the Sabre.
  *
- * @return Address of the initialized PCI structure.
+ * @return      Address of the initialized PCI structure.
  */
 pci_t *pci_sabre_init(ofw_tree_node_t *node)
 {
 ,13 → 91,14
         return NULL;
     ofw_upa_reg_t *reg = prop->value;
-    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
+    size_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < PCI_SABRE_REGS_REG + 1)
+    if (regs < SABRE_INTERNAL_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
+        &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,8 → 107,14
     pci->model = PCI_SABRE;
     pci->op = &pci_sabre_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
+    /*
+     * Set sysinfo data needed by the uspace OBIO driver.
+     */
+    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
 ,9 → 121,9
 /** Initialize the Psycho PCI controller.
  *
- * @param node OpenFirmware device tree node of the Psycho.
+ * @param node      OpenFirmware device tree node of the Psycho.
  *
- * @return Address of the initialized PCI structure.
+ * @return      Address of the initialized PCI structure.
  */
 pci_t *pci_psycho_init(ofw_tree_node_t *node)
 {
 ,13 → 138,14
         return NULL;
     ofw_upa_reg_t *reg = prop->value;
-    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
+    size_t regs = prop->size / sizeof(ofw_upa_reg_t);
-    if (regs < PCI_PSYCHO_REGS_REG + 1)
+    if (regs < PSYCHO_INTERNAL_REG + 1)
         return NULL;
     uintptr_t paddr;
-    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
+    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
+        &paddr))
         return NULL;
     pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 ,31 → 154,27
     pci->model = PCI_PSYCHO;
     pci->op = &pci_psycho_ops;
-    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
+    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
+    /*
+     * Set sysinfo data needed by the uspace OBIO driver.
+     */
+    sysinfo_set_item_val("obio.base.physical", NULL, paddr);
+    sysinfo_set_item_val("kbd.cir.obio", NULL, 1);
     return pci;
 }
-void pci_sabre_enable_interrupt(pci_t *pci, int inr)
+void obio_enable_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
+    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
 }
-void pci_sabre_clear_interrupt(pci_t *pci, int inr)
+void obio_clear_interrupt(pci_t *pci, int inr)
 {
-    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
+    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
 }
-void pci_psycho_enable_interrupt(pci_t *pci, int inr)
-{
-    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
-}
-void pci_psycho_clear_interrupt(pci_t *pci, int inr)
-{
-    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
-}
 /** Initialize PCI controller. */
 pci_t *pci_init(ofw_tree_node_t *node)
 {
 ,7 → 183,7
     /*
      * First, verify this is a PCI node.
      */
-    ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0);
+    ASSERT(str_cmp(ofw_tree_node_name(node), "pci") == 0);
     /*
      * Determine PCI controller model.
 ,13 → 192,13
     if (!prop || !prop->value)
         return NULL;
-    if (strcmp(prop->value, "SUNW,sabre") == 0) {
+    if (str_cmp(prop->value, "SUNW,sabre") == 0) {
         /*
          * PCI controller Sabre.
          * This model is found on UltraSPARC IIi based machines.
          */
         return pci_sabre_init(node);
-    } else if (strcmp(prop->value, "SUNW,psycho") == 0) {
+    } else if (str_cmp(prop->value, "SUNW,psycho") == 0) {
         /*
          * PCI controller Psycho.
          * Used on UltraSPARC II based processors, for instance,
 ,14 → 217,14
 void pci_enable_interrupt(pci_t *pci, int inr)
 {
-    ASSERT(pci->model);
     ASSERT(pci->op && pci->op->enable_interrupt);
     pci->op->enable_interrupt(pci, inr);
 }
-void pci_clear_interrupt(pci_t *pci, int inr)
+void pci_clear_interrupt(void *pcip, int inr)
 {
-    ASSERT(pci->model);
+    pci_t *pci = (pci_t *)pcip;
     ASSERT(pci->op && pci->op->clear_interrupt);
     pci->op->clear_interrupt(pci, inr);
 }

 /branches/arm/kernel/arch/sparc64/src/drivers/sgcn.c
 ,0 → 1,387
+/*
+ * Copyright (c) 2008 Pavel Rimsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup sparc64
+ * @{
+ */
+/**
+ * @file
+ * @brief SGCN driver.
+ */
+#include <arch.h>
+#include <arch/drivers/sgcn.h>
+#include <arch/drivers/kbd.h>
+#include <genarch/ofw/ofw_tree.h>
+#include <debug.h>
+#include <string.h>
+#include <print.h>
+#include <mm/page.h>
+#include <proc/thread.h>
+#include <console/chardev.h>
+#include <console/console.h>
+#include <sysinfo/sysinfo.h>
+#include <synch/spinlock.h>
+#define POLL_INTERVAL       10000
+/*
+ * Physical address at which the SBBC starts. This value has been obtained
+ * by inspecting (using Simics) memory accesses made by OBP. It is valid
+ * for the Simics-simulated Serengeti machine. The author of this code is
+ * not sure whether this value is valid generally.
+ */
+#define SBBC_START      0x63000000000
+/* offset of SRAM within the SBBC memory */
+#define SBBC_SRAM_OFFSET    0x900000
+/* size (in bytes) of the physical memory area which will be mapped */
+#define MAPPED_AREA_SIZE    (128 * 1024)
+/* magic string contained at the beginning of SRAM */
+#define SRAM_TOC_MAGIC      "TOCSRAM"
+/*
+ * Key into the SRAM table of contents which identifies the entry
+ * describing the OBP console buffer. It is worth mentioning
+ * that the OBP console buffer is not the only console buffer
+ * which can be used. It is, however, used because when the kernel
+ * is running, the OBP buffer is not used by OBP any more but OBP
+ * has already made necessary arrangements so that the output will
+ * be read from the OBP buffer and input will go to the OBP buffer.
+ * Therefore HelenOS needs to make no such arrangements any more.
+ */
+#define CONSOLE_KEY     "OBPCONS"
+/* magic string contained at the beginning of the console buffer */
+#define SGCN_BUFFER_MAGIC   "CON"
+/*
+ * Returns a pointer to the object of a given type which is placed at the given
+ * offset from the SRAM beginning.
+ */
+#define SRAM(type, offset)  ((type *) (sram_begin + (offset)))
+/* Returns a pointer to the SRAM table of contents. */
+#define SRAM_TOC        (SRAM(iosram_toc_t, 0))
+/*
+ * Returns a pointer to the object of a given type which is placed at the given
+ * offset from the console buffer beginning.
+ */
+#define SGCN_BUFFER(type, offset) \
+    ((type *) (sgcn_buffer_begin + (offset)))
+/** Returns a pointer to the console buffer header. */
+#define SGCN_BUFFER_HEADER  (SGCN_BUFFER(sgcn_buffer_header_t, 0))
+/** starting address of SRAM, will be set by the init_sram_begin function */
+static uintptr_t sram_begin;
+/**
+ * starting address of the SGCN buffer, will be set by the
+ * init_sgcn_buffer_begin function
+ */
+static uintptr_t sgcn_buffer_begin;
+/* true iff the kernel driver should ignore pressed keys */
+static bool kbd_disabled;
+/*
+ * Ensures that writing to the buffer and consequent update of the write pointer
+ * are together one atomic operation.
+ */
+SPINLOCK_INITIALIZE(sgcn_output_lock);
+/*
+ * Prevents the input buffer read/write pointers from getting to inconsistent
+ * state.
+ */
+SPINLOCK_INITIALIZE(sgcn_input_lock);
+/* functions referenced from definitions of I/O operations structures */
+static void sgcn_putchar(outdev_t *, const wchar_t, bool);
+/** SGCN output device operations */
+static outdev_operations_t sgcnout_ops = {
+    .write = sgcn_putchar
+};
+static outdev_t sgcnout;    /**< SGCN output device. */
+/**
+ * Set some sysinfo values (SRAM address and SRAM size).
+ */
+static void register_sram(uintptr_t sram_begin_physical)
+{
+    sysinfo_set_item_val("sram.area.size", NULL, MAPPED_AREA_SIZE);
+    sysinfo_set_item_val("sram.address.physical", NULL,
+        sram_begin_physical);
+}
+/**
+ * Initializes the starting address of SRAM.
+ *
+ * The SRAM starts 0x900000 + C bytes behind the SBBC start in the
+ * physical memory, where C is the value read from the "iosram-toc"
+ * property of the "/chosen" OBP node. The sram_begin variable will
+ * be set to the virtual address which maps to the SRAM physical
+ * address.
+ */
+static void init_sram_begin(void)
+{
+    ofw_tree_node_t *chosen;
+    ofw_tree_property_t *iosram_toc;
+    uintptr_t sram_begin_physical;
+    chosen = ofw_tree_lookup("/chosen");
+    if (!chosen)
+        panic("Cannot find '/chosen'.");
+    iosram_toc = ofw_tree_getprop(chosen, "iosram-toc");
+    if (!iosram_toc)
+        panic("Cannot find property 'iosram-toc'.");
+    if (!iosram_toc->value)
+        panic("Cannot find SRAM TOC.");
+    sram_begin_physical = SBBC_START + SBBC_SRAM_OFFSET
+        + *((uint32_t *) iosram_toc->value);
+    sram_begin = hw_map(sram_begin_physical, MAPPED_AREA_SIZE);
+    register_sram(sram_begin_physical);
+}
+/**
+ * Initializes the starting address of the SGCN buffer.
+ *
+ * The offset of the SGCN buffer within SRAM is obtained from the
+ * SRAM table of contents. The table of contents contains
+ * information about several buffers, among which there is an OBP
+ * console buffer - this one will be used as the SGCN buffer.
+ *
+ * This function also writes the offset of the SGCN buffer within SRAM
+ * under the sram.buffer.offset sysinfo key.
+ */
+static void sgcn_buffer_begin_init(void)
+{
+    static bool initialized;
+    if (initialized)
+        return;
+    init_sram_begin();
+    ASSERT(str_cmp(SRAM_TOC->magic, SRAM_TOC_MAGIC) == 0);
+    /* lookup TOC entry with the correct key */
+    uint32_t i;
+    for (i = 0; i < MAX_TOC_ENTRIES; i++) {
+        if (str_cmp(SRAM_TOC->keys[i].key, CONSOLE_KEY) == 0)
+            break;
+    }
+    ASSERT(i < MAX_TOC_ENTRIES);
+    sgcn_buffer_begin = sram_begin + SRAM_TOC->keys[i].offset;
+    sysinfo_set_item_val("sram.buffer.offset", NULL,
+        SRAM_TOC->keys[i].offset);
+    initialized = true;
+}
+/**
+ * Writes a single character to the SGCN (circular) output buffer
+ * and updates the output write pointer so that SGCN gets to know
+ * that the character has been written.
+ */
+static void sgcn_do_putchar(const char c)
+{
+    uint32_t begin = SGCN_BUFFER_HEADER->out_begin;
+    uint32_t end = SGCN_BUFFER_HEADER->out_end;
+    uint32_t size = end - begin;
+    /* we need pointers to volatile variables */
+    volatile char *buf_ptr = (volatile char *)
+        SGCN_BUFFER(char, SGCN_BUFFER_HEADER->out_wrptr);
+    volatile uint32_t *out_wrptr_ptr = &(SGCN_BUFFER_HEADER->out_wrptr);
+    volatile uint32_t *out_rdptr_ptr = &(SGCN_BUFFER_HEADER->out_rdptr);
+    /*
+     * Write the character and increment the write pointer modulo the
+     * output buffer size. Note that if we are to rewrite a character
+     * which has not been read by the SGCN controller yet (i.e. the output
+     * buffer is full), we need to wait until the controller reads some more
+     * characters. We wait actively, which means that all threads waiting
+     * for the lock are blocked. However, this situation is
+     *   1) rare - the output buffer is big, so filling the whole
+     *             output buffer is improbable
+     *   2) short-lasting - it will take the controller only a fraction
+     *             of millisecond to pick the unread characters up
+     *   3) not serious - the blocked threads are those that print something
+     *             to user console, which is not a time-critical operation
+     */
+    uint32_t new_wrptr = (((*out_wrptr_ptr) - begin + 1) % size) + begin;
+    while (*out_rdptr_ptr == new_wrptr)
+        ;
+    *buf_ptr = c;
+    *out_wrptr_ptr = new_wrptr;
+}
+/**
+ * SGCN output operation. Prints a single character to the SGCN. Newline
+ * character is converted to CRLF.
+ */
+static void sgcn_putchar(outdev_t *od, const wchar_t ch, bool silent)
+{
+    if (!silent) {
+        spinlock_lock(&sgcn_output_lock);
+        if (ascii_check(ch)) {
+            if (ch == '\n')
+                sgcn_do_putchar('\r');
+            sgcn_do_putchar(ch);
+        } else
+            sgcn_do_putchar(U_SPECIAL);
+        spinlock_unlock(&sgcn_output_lock);
+    }
+}
+/**
+ * Grabs the input for kernel.
+ */
+void sgcn_grab(void)
+{
+    kbd_disabled = false;
+}
+/**
+ * Releases the input so that userspace can use it.
+ */
+void sgcn_release(void)
+{
+    kbd_disabled = true;
+}
+/**
+ * Function regularly called by the keyboard polling thread. Finds out whether
+ * there are some unread characters in the input queue. If so, it picks them up
+ * and sends them to the upper layers of HelenOS.
+ */
+static void sgcn_poll(sgcn_instance_t *instance)
+{
+    uint32_t begin = SGCN_BUFFER_HEADER->in_begin;
+    uint32_t end = SGCN_BUFFER_HEADER->in_end;
+    uint32_t size = end - begin;
+    if (kbd_disabled)
+        return;
+    spinlock_lock(&sgcn_input_lock);
+    /* we need pointers to volatile variables */
+    volatile char *buf_ptr = (volatile char *)
+        SGCN_BUFFER(char, SGCN_BUFFER_HEADER->in_rdptr);
+    volatile uint32_t *in_wrptr_ptr = &(SGCN_BUFFER_HEADER->in_wrptr);
+    volatile uint32_t *in_rdptr_ptr = &(SGCN_BUFFER_HEADER->in_rdptr);
+    while (*in_rdptr_ptr != *in_wrptr_ptr) {
+        buf_ptr = (volatile char *)
+            SGCN_BUFFER(char, SGCN_BUFFER_HEADER->in_rdptr);
+        char c = *buf_ptr;
+        *in_rdptr_ptr = (((*in_rdptr_ptr) - begin + 1) % size) + begin;
+        indev_push_character(instance->srlnin, c);
+    }
+    spinlock_unlock(&sgcn_input_lock);
+}
+/**
+ * Polling thread function.
+ */
+static void ksgcnpoll(void *instance) {
+    while (1) {
+        if (!silent)
+            sgcn_poll(instance);
+        thread_usleep(POLL_INTERVAL);
+    }
+}
+/**
+ * A public function which initializes input from the Serengeti console.
+ */
+sgcn_instance_t *sgcnin_init(void)
+{
+    sgcn_buffer_begin_init();
+    sgcn_instance_t *instance =
+        malloc(sizeof(sgcn_instance_t), FRAME_ATOMIC);
+    if (instance) {
+        instance->srlnin = NULL;
+        instance->thread = thread_create(ksgcnpoll, instance, TASK, 0,
+            "ksgcnpoll", true);
+        if (!instance->thread) {
+            free(instance);
+            return NULL;
+        }
+    }
+    return instance;
+}
+void sgcnin_wire(sgcn_instance_t *instance, indev_t *srlnin)
+{
+    ASSERT(instance);
+    ASSERT(srlnin);
+    instance->srlnin = srlnin;
+    thread_ready(instance->thread);
+    sysinfo_set_item_val("kbd", NULL, true);
+}
+/**
+ * A public function which initializes output to the Serengeti console.
+ */
+void sgcnout_init(void)
+{
+    sgcn_buffer_begin_init();
+    sysinfo_set_item_val("fb.kind", NULL, 4);
+    outdev_initialize("sgcnout", &sgcnout, &sgcnout_ops);
+    stdout = &sgcnout;
+}
+/** @}
+ */

 /branches/arm/kernel/arch/sparc64/src/drivers/kbd.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64
+/** @addtogroup sparc64
  * @{
  */
 /** @file
 ,99 → 34,160
 #include <arch/drivers/kbd.h>
 #include <genarch/ofw/ofw_tree.h>
+#ifdef CONFIG_SUN_KBD
+#include <genarch/kbrd/kbrd.h>
+#endif
 #ifdef CONFIG_Z8530
-#include <genarch/kbd/z8530.h>
+#include <genarch/drivers/z8530/z8530.h>
 #endif
 #ifdef CONFIG_NS16550
-#include <genarch/kbd/ns16550.h>
+#include <genarch/drivers/ns16550/ns16550.h>
 #endif
-#include <ddi/device.h>
+#include <console/console.h>
 #include <ddi/irq.h>
 #include <arch/mm/page.h>
 #include <arch/types.h>
 #include <align.h>
-#include <func.h>
+#include <string.h>
 #include <print.h>
+#include <sysinfo/sysinfo.h>
-kbd_type_t kbd_type = KBD_UNKNOWN;
+#ifdef CONFIG_SUN_KBD
-/** Initialize keyboard.
- *
- * Traverse OpenFirmware device tree in order to find necessary
- * info about the keyboard device.
- *
- * @param node Keyboard device node.
- */
-void kbd_init(ofw_tree_node_t *node)
+#ifdef CONFIG_Z8530
+static bool kbd_z8530_init(ofw_tree_node_t *node)
 {
-    size_t offset;
-    uintptr_t aligned_addr;
-    ofw_tree_property_t *prop;
-    const char *name;
+    const char *name = ofw_tree_node_name(node);
-    name = ofw_tree_node_name(node);
+    if (str_cmp(name, "zs") != 0)
+        return false;
     /*
-     * Determine keyboard serial controller type.
+     * Read 'interrupts' property.
      */
-    if (strcmp(name, "zs") == 0)
-        kbd_type = KBD_Z8530;
-    else if (strcmp(name, "su") == 0)
-        kbd_type = KBD_NS16550;
+    ofw_tree_property_t *prop = ofw_tree_getprop(node, "interrupts");
+    if ((!prop) || (!prop->value)) {
+        printf("z8530: Unable to find interrupts property\n");
+        return false;
+    }
-    if (kbd_type == KBD_UNKNOWN) {
-        printf("Unknown keyboard device.\n");
-        return;
+    uint32_t interrupts = *((uint32_t *) prop->value);
+    /*
+     * Read 'reg' property.
+     */
+    prop = ofw_tree_getprop(node, "reg");
+    if ((!prop) || (!prop->value)) {
+        printf("z8530: Unable to find reg property\n");
+        return false;
     }
+    size_t size = ((ofw_fhc_reg_t *) prop->value)->size;
+    uintptr_t pa;
+    if (!ofw_fhc_apply_ranges(node->parent,
+        ((ofw_fhc_reg_t *) prop->value), &pa)) {
+        printf("z8530: Failed to determine address\n");
+        return false;
+    }
+    inr_t inr;
+    cir_t cir;
+    void *cir_arg;
+    if (!ofw_fhc_map_interrupt(node->parent,
+        ((ofw_fhc_reg_t *) prop->value), interrupts, &inr, &cir,
+        &cir_arg)) {
+        printf("z8530: Failed to determine interrupt\n");
+        return false;
+    }
     /*
-     * Read 'interrupts' property.
+     * We need to pass aligned address to hw_map().
+     * However, the physical keyboard address can
+     * be pretty much unaligned, depending on the
+     * underlying controller.
      */
-    uint32_t interrupts;
-    prop = ofw_tree_getprop(node, "interrupts");
-    if (!prop || !prop->value)
-        panic("Can't find \"interrupts\" property.\n");
-    interrupts = *((uint32_t *) prop->value);
+    uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
+    size_t offset = pa - aligned_addr;
+    z8530_t *z8530 = (z8530_t *)
+        (hw_map(aligned_addr, offset + size) + offset);
+    z8530_instance_t *z8530_instance = z8530_init(z8530, inr, cir, cir_arg);
+    if (z8530_instance) {
+        kbrd_instance_t *kbrd_instance = kbrd_init();
+        if (kbrd_instance) {
+            indev_t *sink = stdin_wire();
+            indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
+            z8530_wire(z8530_instance, kbrd);
+        }
+    }
+    /*
+     * This is the necessary evil until the userspace drivers are
+     * entirely self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, inr);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) z8530);
+    sysinfo_set_item_val("kbd.address.physical", NULL, pa);
+    sysinfo_set_item_val("kbd.type.z8530", NULL, true);
+    return true;
+}
+#endif /* CONFIG_Z8530 */
+#ifdef CONFIG_NS16550
+static bool kbd_ns16550_init(ofw_tree_node_t *node)
+{
+    const char *name = ofw_tree_node_name(node);
+    if (str_cmp(name, "su") != 0)
+        return false;
     /*
+     * Read 'interrupts' property.
+     */
+    ofw_tree_property_t *prop = ofw_tree_getprop(node, "interrupts");
+    if ((!prop) || (!prop->value)) {
+        printf("ns16550: Unable to find interrupts property\n");
+        return false;
+    }
+    uint32_t interrupts = *((uint32_t *) prop->value);
+    /*
      * Read 'reg' property.
      */
     prop = ofw_tree_getprop(node, "reg");
-    if (!prop || !prop->value)
-        panic("Can't find \"reg\" property.\n");
+    if ((!prop) || (!prop->value)) {
+        printf("ns16550: Unable to find reg property\n");
+        return false;
+    }
+    size_t size = ((ofw_ebus_reg_t *) prop->value)->size;
     uintptr_t pa;
-    size_t size;
+    if (!ofw_ebus_apply_ranges(node->parent,
+        ((ofw_ebus_reg_t *) prop->value), &pa)) {
+        printf("ns16550: Failed to determine address\n");
+        return false;
+    }
     inr_t inr;
-    devno_t devno = device_assign_devno();
-    switch (kbd_type) {
-    case KBD_Z8530:
-        size = ((ofw_fhc_reg_t *) prop->value)->size;
-        if (!ofw_fhc_apply_ranges(node->parent, ((ofw_fhc_reg_t *) prop->value) , &pa)) {
-            printf("Failed to determine keyboard address.\n");
-            return;
-        }
-        if (!ofw_fhc_map_interrupt(node->parent, ((ofw_fhc_reg_t *) prop->value), interrupts, &inr)) {
-            printf("Failed to determine keyboard interrupt.\n");
-            return;
-        }
-        break;
-    case KBD_NS16550:
-        size = ((ofw_ebus_reg_t *) prop->value)->size;
-        if (!ofw_ebus_apply_ranges(node->parent, ((ofw_ebus_reg_t *) prop->value) , &pa)) {
-            printf("Failed to determine keyboard address.\n");
-            return;
-        }
-        if (!ofw_ebus_map_interrupt(node->parent, ((ofw_ebus_reg_t *) prop->value), interrupts, &inr)) {
-            printf("Failed to determine keyboard interrupt.\n");
-            return;
-        };
-        break;
-    default:
-        panic("Unexpected type.\n");
+    cir_t cir;
+    void *cir_arg;
+    if (!ofw_ebus_map_interrupt(node->parent,
+        ((ofw_ebus_reg_t *) prop->value), interrupts, &inr, &cir,
+        &cir_arg)) {
+        printf("ns16550: Failed to determine interrupt\n");
+        return false;
     }
     /*
 ,25 → 196,58
      * be pretty much unaligned, depending on the
      * underlying controller.
      */
-    aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
-    offset = pa - aligned_addr;
-    uintptr_t vaddr = hw_map(aligned_addr, offset + size) + offset;
+    uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE);
+    size_t offset = pa - aligned_addr;
+    ns16550_t *ns16550 = (ns16550_t *)
+       (hw_map(aligned_addr, offset + size) + offset);
+    ns16550_instance_t *ns16550_instance = ns16550_init(ns16550, inr, cir, cir_arg);
+    if (ns16550_instance) {
+        kbrd_instance_t *kbrd_instance = kbrd_init();
+        if (kbrd_instance) {
+            indev_t *sink = stdin_wire();
+            indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
+            ns16550_wire(ns16550_instance, kbrd);
+        }
+    }
+    /*
+     * This is the necessary evil until the userspace drivers are
+     * entirely self-sufficient.
+     */
+    sysinfo_set_item_val("kbd", NULL, true);
+    sysinfo_set_item_val("kbd.inr", NULL, inr);
+    sysinfo_set_item_val("kbd.address.kernel", NULL,
+        (uintptr_t) ns16550);
+    sysinfo_set_item_val("kbd.address.physical", NULL, pa);
+    sysinfo_set_item_val("kbd.type.ns16550", NULL, true);
+    return true;
+}
-    switch (kbd_type) {
+#endif /* CONFIG_NS16550 */
+/** Initialize keyboard.
+ *
+ * Traverse OpenFirmware device tree in order to find necessary
+ * info about the keyboard device.
+ *
+ * @param node Keyboard device node.
+ *
+ */
+void kbd_init(ofw_tree_node_t *node)
+{
 #ifdef CONFIG_Z8530
-    case KBD_Z8530:
-        z8530_init(devno, inr, vaddr);
-        break;
+    kbd_z8530_init(node);
 #endif
 #ifdef CONFIG_NS16550
-    case KBD_NS16550:
-        ns16550_init(devno, inr, vaddr);
-        break;
+    kbd_ns16550_init(node);
 #endif
-    default:
-        printf("Kernel is not compiled with the necessary keyboard driver this machine requires.\n");
-    }
 }
+#endif /* CONFIG_SUN_KBD */
 /** @}
  */

 /branches/arm/kernel/arch/sparc64/src/drivers/scr.c
 ,7 → 37,7
 #include <genarch/fb/fb.h>
 #include <genarch/fb/visuals.h>
 #include <arch/types.h>
-#include <func.h>
+#include <string.h>
 #include <align.h>
 #include <print.h>
 ,23 → 55,30
 void scr_init(ofw_tree_node_t *node)
 {
     ofw_tree_property_t *prop;
+    ofw_pci_reg_t *pci_reg;
+    ofw_pci_reg_t pci_abs_reg;
+    ofw_upa_reg_t *upa_reg;
+    ofw_sbus_reg_t *sbus_reg;
     const char *name;
     name = ofw_tree_node_name(node);
-    if (strcmp(name, "SUNW,m64B") == 0)
+    if (str_cmp(name, "SUNW,m64B") == 0)
         scr_type = SCR_ATYFB;
-    else if (strcmp(name, "SUNW,ffb") == 0)
+    else if (str_cmp(name, "SUNW,XVR-100") == 0)
+        scr_type = SCR_XVR;
+    else if (str_cmp(name, "SUNW,ffb") == 0)
         scr_type = SCR_FFB;
-    else if (strcmp(name, "cgsix") == 0)
+    else if (str_cmp(name, "cgsix") == 0)
         scr_type = SCR_CGSIX;
     if (scr_type == SCR_UNKNOWN) {
-        printf("Unknown keyboard device.\n");
+        printf("Unknown screen device.\n");
         return;
     }
     uintptr_t fb_addr;
+    unsigned int fb_offset = 0;
     uint32_t fb_width = 0;
     uint32_t fb_height = 0;
     uint32_t fb_depth = 0;
 ,7 → 104,7
     prop = ofw_tree_getprop(node, "reg");
     if (!prop)
-        panic("Can't find \"reg\" property.\n");
+        panic("Cannot find 'reg' property.");
     switch (scr_type) {
     case SCR_ATYFB:
 ,15 → 113,15
             return;
         }
-        ofw_pci_reg_t *fb_reg = &((ofw_pci_reg_t *) prop->value)[1];
-        ofw_pci_reg_t abs_reg;
+        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
-        if (!ofw_pci_reg_absolutize(node, fb_reg, &abs_reg)) {
+        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
             printf("Failed to absolutize fb register.\n");
             return;
         }
-        if (!ofw_pci_apply_ranges(node->parent, &abs_reg , &fb_addr)) {
+        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
+            &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,12 → 149,56
         }
         break;
+    case SCR_XVR:
+        if (prop->size / sizeof(ofw_pci_reg_t) < 2) {
+            printf("Too few screen registers.\n");
+            return;
+        }
+        pci_reg = &((ofw_pci_reg_t *) prop->value)[1];
+        if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) {
+            printf("Failed to absolutize fb register.\n");
+            return;
+        }
+        if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg,
+            &fb_addr)) {
+            printf("Failed to determine screen address.\n");
+            return;
+        }
+        fb_offset = 4 * 0x2000;
+        switch (fb_depth) {
+        case 8:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_INDIRECT_8;
+            break;
+        case 16:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_RGB_5_6_5;
+            break;
+        case 24:
+            fb_scanline = fb_linebytes * 4;
+            visual = VISUAL_RGB_8_8_8_0;
+            break;
+        case 32:
+            fb_scanline = fb_linebytes * (fb_depth >> 3);
+            visual = VISUAL_RGB_0_8_8_8;
+            break;
+        default:
+            printf("Unsupported bits per pixel.\n");
+            return;
+        }
+        break;
     case SCR_FFB:
         fb_scanline = 8192;
         visual = VISUAL_BGR_0_8_8_8;
-        ofw_upa_reg_t *reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
-        if (!ofw_upa_apply_ranges(node->parent, reg, &fb_addr)) {
+        upa_reg = &((ofw_upa_reg_t *) prop->value)[FFB_REG_24BPP];
+        if (!ofw_upa_apply_ranges(node->parent, upa_reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,8 → 215,8
             return;
         }
-        ofw_sbus_reg_t *cg6_reg = &((ofw_sbus_reg_t *) prop->value)[0];
-        if (!ofw_sbus_apply_ranges(node->parent, cg6_reg, &fb_addr)) {
+        sbus_reg = &((ofw_sbus_reg_t *) prop->value)[0];
+        if (!ofw_sbus_apply_ranges(node->parent, sbus_reg, &fb_addr)) {
             printf("Failed to determine screen address.\n");
             return;
         }
 ,11 → 223,24
         break;
     default:
-        panic("Unexpected type.\n");
+        panic("Unexpected type.");
     }
-    fb_init(fb_addr, fb_width, fb_height, fb_scanline, visual);
+    fb_properties_t props = {
+        .addr = fb_addr,
+        .offset = fb_offset,
+        .x = fb_width,
+        .y = fb_height,
+        .scan = fb_scanline,
+        .visual = visual,
+    };
+    fb_init(&props);
 }
+void scr_redraw(void)
+{
+    fb_redraw();
+}
 /** @}
  */

 /branches/arm/kernel/arch/sparc64/src/drivers/tick.c
 ,11 → 45,12
 #define TICK_RESTART_TIME   50  /* Worst case estimate. */
-/** Initialize tick interrupt. */
+/** Initialize tick and stick interrupt. */
 void tick_init(void)
 {
+    /* initialize TICK interrupt */
     tick_compare_reg_t compare;
     interrupt_register(14, "tick_int", tick_interrupt);
     compare.int_dis = false;
     compare.tick_cmpr = CPU->arch.clock_frequency / HZ;
 ,6 → 57,21
     CPU->arch.next_tick_cmpr = compare.tick_cmpr;
     tick_compare_write(compare.value);
     tick_write(0);
+#if defined (US3)
+    /* disable STICK interrupts and clear any pending ones */
+    tick_compare_reg_t stick_compare;
+    softint_reg_t clear;
+    stick_compare.value = stick_compare_read();
+    stick_compare.int_dis = true;
+    stick_compare.tick_cmpr = 0;
+    stick_compare_write(stick_compare.value);
+    clear.value = 0;
+    clear.stick_int = 1;
+    clear_softint_write(clear.value);
+#endif
 }
 /** Process tick interrupt.
 ,7 → 83,7
 {
     softint_reg_t softint, clear;
     uint64_t drift;
     softint.value = softint_read();
     /*

/branches/arm/kernel/arch/sparc64/src/dummy.s
42,5 → 42,5

.global cpu_halt
cpu_halt:
b cpu_halt
ba %xcc, cpu_halt
nop

 /branches/arm/kernel/arch/sparc64/src/trap/trap_table.S
 ,7 → 341,7
 .org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE
 .global trap_instruction_\cur\()_tl0
 trap_instruction_\cur\()_tl0:
-    ba trap_instruction_handler
+    ba %xcc, trap_instruction_handler
     mov \cur, %g2
 .endr
 ,9 → 478,9
      */
     rdpr %tl, %g3
     cmp %g3, 1
-    be 1f
+    be %xcc, 1f
     nop
-:  ba 0b                   ! this is for debugging, if we ever get here
+:  ba %xcc, 0b             ! this is for debugging, if we ever get here
     nop                 ! it will be easy to find
 :
 ,7 → 499,7
     wrpr %g4, 0, %cwp           ! resynchronize CWP
     andcc %g3, TSTATE_PRIV_BIT, %g0     ! if this trap came from the privileged mode...
-    bnz 0f                  ! ...skip setting of kernel stack and primary context
+    bnz %xcc, 0f                ! ...skip setting of kernel stack and primary context
     nop
 .endif
 ,7 → 545,7
     flush %l0
 .if NOT(\is_syscall)
-    ba 1f
+    ba %xcc, 1f
     nop
 :
     save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
 ,10 → 606,10
     add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
 .else
     /*
-     * Call the higher-level syscall handler.
+     * Call the higher-level syscall handler and enable interrupts.
      */
     call syscall_handler
-    nop
+    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT | PSTATE_IE_BIT, %pstate
     mov %o0, %i0                ! copy the value returned by the syscall
 .endif
 ,7 → 672,7
     and %l0, NWINDOWS - 1, %l0  ! %l0 mod NWINDOWS
     rdpr %cwp, %l1
     cmp %l0, %l1
-    bz 0f               ! CWP is ok
+    bz %xcc, 0f         ! CWP is ok
     nop
     /*
 ,7 → 712,7
 .if NOT(\is_syscall)
     rdpr %tstate, %g1
     andcc %g1, TSTATE_PRIV_BIT, %g0     ! if we are not returning to userspace...,
-    bnz 1f                  ! ...skip restoring userspace windows
+    bnz %xcc, 1f                ! ...skip restoring userspace windows
     nop
 .endif
 ,9 → 748,8
      * Fill all windows stored in the buffer.
      */
     clr %g4
-    set PAGE_SIZE - 1, %g5
-:  andcc %g7, %g5, %g0         ! PAGE_SIZE alignment check
-    bz 0f                   ! %g7 is page-aligned, no more windows to refill
+:  andcc %g7, UWB_ALIGNMENT - 1, %g0   ! alignment check
+    bz %xcc, 0f             ! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill
     nop
     add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7
 ,7 → 774,7
     and %g3, NWINDOWS - 1, %g3
     wrpr %g3, 0, %cwp           ! switch to the preceeding window
-    ba 0b
+    ba %xcc, 0b
     inc %g4
 :
 ,7 → 785,7
     wrpr %g1, 0, %cwp
     add %g4, %g2, %g2
     cmp %g2, NWINDOWS - 2
-    bg 2f                   ! fix the CANRESTORE=NWINDOWS-1 anomaly
+    bg %xcc, 2f             ! fix the CANRESTORE=NWINDOWS-1 anomaly
     mov NWINDOWS - 2, %g1           ! use dealy slot for both cases
     sub %g1, %g2, %g1

 /branches/arm/kernel/arch/sparc64/src/trap/exception.c
 ,62 → 40,67
 #include <arch/asm.h>
 #include <arch/register.h>
 #include <debug.h>
+#include <print.h>
 #include <symtab.h>
-#include <print.h>
 void dump_istate(istate_t *istate)
 {
+    char *tpcs, *tnpcs;
+    tpcs = symtab_fmt_name_lookup(istate->tpc);
+    tnpcs = symtab_fmt_name_lookup(istate->tnpc);
     printf("TSTATE=%#" PRIx64 "\n", istate->tstate);
-    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, get_symtab_entry(istate->tpc));
-    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, get_symtab_entry(istate->tnpc));
+    printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, tpcs);
+    printf("TNPC=%#" PRIx64 " (%s)\n", istate->tnpc, tnpcs);
 }
 /** Handle instruction_access_exception. (0x8) */
 void instruction_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle instruction_access_error. (0xa) */
 void instruction_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle illegal_instruction. (0x10) */
 void illegal_instruction(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle privileged_opcode. (0x11) */
 void privileged_opcode(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle unimplemented_LDD. (0x12) */
 void unimplemented_LDD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle unimplemented_STD. (0x13) */
 void unimplemented_STD(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle fp_disabled. (0x20) */
 ,9 → 118,9
 #ifdef CONFIG_FPU_LAZY
     scheduler_fpu_lazy_request();
 #else
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 #endif
 }
 ,98 → 127,98
 /** Handle fp_exception_ieee_754. (0x21) */
 void fp_exception_ieee_754(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle fp_exception_other. (0x22) */
 void fp_exception_other(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle tag_overflow. (0x23) */
 void tag_overflow(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle division_by_zero. (0x28) */
 void division_by_zero(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle data_access_exception. (0x30) */
 void data_access_exception(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
     dump_sfsr_and_sfar();
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle data_access_error. (0x32) */
 void data_access_error(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle mem_address_not_aligned. (0x34) */
 void mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle LDDF_mem_address_not_aligned. (0x35) */
 void LDDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle STDF_mem_address_not_aligned. (0x36) */
 void STDF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle privileged_action. (0x37) */
 void privileged_action(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle LDQF_mem_address_not_aligned. (0x38) */
 void LDQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** Handle STQF_mem_address_not_aligned. (0x39) */
 void STQF_mem_address_not_aligned(int n, istate_t *istate)
 {
-    fault_if_from_uspace(istate, "%s\n", __func__);
+    fault_if_from_uspace(istate, "%s.", __func__);
     dump_istate(istate);
-    panic("%s\n", __func__);
+    panic("%s.", __func__);
 }
 /** @}

 /branches/arm/kernel/arch/sparc64/src/trap/interrupt.c
 ,11 → 67,19
  */
 void interrupt(int n, istate_t *istate)
 {
+    uint64_t status;
     uint64_t intrcv;
     uint64_t data0;
+    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
+    if (status & (!INTR_DISPATCH_STATUS_BUSY))
+        panic("Interrupt Dispatch Status busy bit not set.");
     intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
-    data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#if defined (US)
+    data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#elif defined (US3)
+    data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
+#endif
     irq_t *irq = irq_dispatch_and_lock(data0);
     if (irq) {
 ,7 → 86,13
         /*
          * The IRQ handler was found.
          */
-        irq->handler(irq, irq->arg);
+        irq->handler(irq);
+        /*
+         * See if there is a clear-interrupt-routine and call it.
+         */
+        if (irq->cir) {
+            irq->cir(irq->cir_arg, irq->inr);
+        }
         spinlock_unlock(&irq->lock);
     } else if (data0 > config.base) {
         /*
 ,7 → 112,7
          */
 #ifdef CONFIG_DEBUG
         printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64
-            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
+            ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0);
 #endif
     }

 /branches/arm/kernel/arch/sparc64/src/start.S
 ,6 → 27,7
 #
 #include <arch/arch.h>
+#include <arch/cpu.h>
 #include <arch/regdef.h>
 #include <arch/boot/boot.h>
 #include <arch/stack.h>
 ,6 → 48,16
 #define BSP_FLAG    1
 /*
+ * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
+ * a given processor.
+ */
+#if defined (US)
+    #define PHYSMEM_ADDR_SIZE   41
+#elif defined (US3)
+    #define PHYSMEM_ADDR_SIZE   43
+#endif
+/*
  * Here is where the kernel is passed control from the boot loader.
  *
  * The registers are expected to be in this state:
 ,11 → 78,13
     and %o0, %l0, %l7           ! l7 <= bootstrap processor?
     andn %o0, %l0, %l6          ! l6 <= start of physical memory
-    ! Get bits 40:13 of physmem_base.
+    ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
     srlx %l6, 13, %l5
-    sllx %l5, 13 + (63 - 40), %l5
-    srlx %l5, 63 - 40, %l5          ! l5 <= physmem_base[40:13]
+    ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
+    sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
+    srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
     /*
      * Setup basic runtime environment.
      */
 ,6 → 96,8
                         ! consistent
     wrpr %g0, NWINDOWS - 1, %cleanwin   ! prevent needless clean_window
                         ! traps for kernel
+    wrpr %g0, 0, %wstate            ! use default spill/fill trap
     wrpr %g0, 0, %tl            ! TL = 0, primary context
                         ! register is used
 ,7 → 259,8
     /*
      * Precompute kernel 8K TLB data template.
-     * %l5 contains starting physical address bits [40:13]
+     * %l5 contains starting physical address
+     * bits [(PHYSMEM_ADDR_SIZE - 1):13]
      */
     sethi %hi(kernel_8k_tlb_data_template), %l4
     ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
 ,19 → 294,36
     /* Not reached. */
 :
-    ba 0b
+    ba %xcc, 0b
     nop
+:
+#ifdef CONFIG_SMP
     /*
+     * Determine the width of the MID and save its mask to %g3. The width
+     * is
+     *  * 5 for US and US-IIIi,
+     *  * 10 for US3 except US-IIIi.
+     */
+#if defined(US)
+    mov 0x1f, %g3
+#elif defined(US3)
+    mov 0x3ff, %g3
+    rdpr %ver, %g2
+    sllx %g2, 16, %g2
+    srlx %g2, 48, %g2
+    cmp %g2, IMPL_ULTRASPARCIII_I
+    move %xcc, 0x1f, %g3
+#endif
+    /*
      * Read MID from the processor.
      */
-:
-    ldxa [%g0] ASI_UPA_CONFIG, %g1
-    srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
-    and %g1, UPA_CONFIG_MID_MASK, %g1
+    ldxa [%g0] ASI_ICBUS_CONFIG, %g1
+    srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
+    and %g1, %g3, %g1
-#ifdef CONFIG_SMP
     /*
      * Active loop for APs until the BSP picks them up. A processor cannot
      * leave the loop until the global variable 'waking_up_mid' equals its
 ,7 → 333,7
 :
     ldx [%g2], %g3
     cmp %g3, %g1
-    bne 2b
+    bne %xcc, 2b
     nop
     /*
 ,7 → 352,7
 #endif
 :
-    ba 0b
+    ba %xcc, 0b
     nop
 ,10 → 381,31
     .quad 0
 /*
- * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it
- * is further modified to reflect the starting address of physical memory.
+ * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and
+ * kernel_8k_tlb_data_template variables are meant to stay together,
+ * aligned on 16B boundary.
  */
+.global fast_data_access_mmu_miss_data_hi
+.global end_of_identity
 .global kernel_8k_tlb_data_template
+.align 16
+/*
+ * This label is used by the fast_data_access_MMU_miss trap handler.
+ */
+fast_data_access_mmu_miss_data_hi:
+/*
+ * This variable is used by the fast_data_access_MMU_miss trap handler.
+ * In runtime, it is modified to contain the address of the end of physical
+ * memory.
+ */
+end_of_identity:
+    .quad -1
+/*
+ * This variable is used by the fast_data_access_MMU_miss trap handler.
+ * In runtime, it is further modified to reflect the starting address of
+ * physical memory.
+ */
 kernel_8k_tlb_data_template:
 #ifdef CONFIG_VIRT_IDX_DCACHE
     .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \

 /branches/arm/kernel/arch/sparc64/src/console.c
 ,7 → 26,7
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-/** @addtogroup sparc64
+/** @addtogroup sparc64
  * @{
  */
 /** @file
 ,14 → 37,8
 #include <arch/drivers/scr.h>
 #include <arch/drivers/kbd.h>
-#ifdef CONFIG_Z8530
-#include <genarch/kbd/z8530.h>
-#endif
-#ifdef CONFIG_NS16550
-#include <genarch/kbd/ns16550.h>
-#endif
+#include <arch/drivers/sgcn.h>
+#include <genarch/srln/srln.h>
 #include <console/chardev.h>
 #include <console/console.h>
 #include <arch/asm.h>
 ,92 → 48,101
 #include <genarch/ofw/ofw_tree.h>
 #include <arch.h>
 #include <panic.h>
+#include <string.h>
 #include <print.h>
 #define KEYBOARD_POLL_PAUSE 50000   /* 50ms */
-/** Initialize kernel console to use framebuffer and keyboard directly. */
-void standalone_sparc64_console_init(void)
+/**
+ * Initialize kernel console to use framebuffer and keyboard directly.
+ * Called on UltraSPARC machines with standard keyboard and framebuffer.
+ *
+ * @param aliases   the "/aliases" OBP node
+ */
+static void standard_console_init(ofw_tree_node_t *aliases)
 {
-    stdin = NULL;
-    ofw_tree_node_t *aliases;
-    ofw_tree_property_t *prop;
-    ofw_tree_node_t *screen;
-    ofw_tree_node_t *keyboard;
+#ifdef CONFIG_FB
+    ofw_tree_property_t *prop_scr = ofw_tree_getprop(aliases, "screen");
+    if (!prop_scr)
+        panic("Cannot find property 'screen'.");
+    if (!prop_scr->value)
+        panic("Cannot find screen alias.");
+    ofw_tree_node_t *screen = ofw_tree_lookup(prop_scr->value);
+    if (!screen)
+        panic("Cannot find %s.", prop_scr->value);
-    aliases = ofw_tree_lookup("/aliases");
-    if (!aliases)
-        panic("Can't find /aliases.\n");
-    prop = ofw_tree_getprop(aliases, "screen");
-    if (!prop)
-        panic("Can't find property \"screen\".\n");
-    if (!prop->value)
-        panic("Can't find screen alias.\n");
-    screen = ofw_tree_lookup(prop->value);
-    if (!screen)
-        panic("Can't find %s\n", prop->value);
     scr_init(screen);
+#endif
-    prop = ofw_tree_getprop(aliases, "keyboard");
-    if (!prop)
-        panic("Can't find property \"keyboard\".\n");
-    if (!prop->value)
-        panic("Can't find keyboard alias.\n");
-    keyboard = ofw_tree_lookup(prop->value);
+#ifdef CONFIG_SUN_KBD
+    ofw_tree_property_t *prop_kbd = ofw_tree_getprop(aliases, "keyboard");
+    if (!prop_kbd)
+        panic("Cannot find property 'keyboard'.");
+    if (!prop_kbd->value)
+        panic("Cannot find keyboard alias.");
+    ofw_tree_node_t *keyboard = ofw_tree_lookup(prop_kbd->value);
     if (!keyboard)
-        panic("Can't find %s\n", prop->value);
+        panic("Cannot find %s.", prop_kbd->value);
     kbd_init(keyboard);
+#endif
 }
-/** Kernel thread for polling keyboard.
- *
- * @param arg Ignored.
- */
-void kkbdpoll(void *arg)
+/** Initilize I/O on the Serengeti machine. */
+static void serengeti_init(void)
 {
-    thread_detach(THREAD);
-#ifdef CONFIG_Z8530
-    if (kbd_type == KBD_Z8530) {
-        /*
-         * The z8530 driver is interrupt-driven.
-         */
-        return;
+#ifdef CONFIG_SGCN_KBD
+    sgcn_instance_t *sgcn_instance = sgcnin_init();
+    if (sgcn_instance) {
+        srln_instance_t *srln_instance = srln_init();
+        if (srln_instance) {
+            indev_t *sink = stdin_wire();
+            indev_t *srln = srln_wire(srln_instance, sink);
+            sgcnin_wire(sgcn_instance, srln);
+        }
     }
 #endif
+#ifdef CONFIG_SGCN_PRN
+    sgcnout_init();
+#endif
+}
-    while (1) {
-#ifdef CONFIG_NS16550
-        if (kbd_type == KBD_NS16550)
-            ns16550_poll();
-#endif
-        thread_usleep(KEYBOARD_POLL_PAUSE);
+/**
+ * Initialize input/output. Auto-detects the type of machine
+ * and calls the appropriate I/O init routine.
+ */
+void standalone_sparc64_console_init(void)
+{
+    ofw_tree_node_t *aliases;
+    ofw_tree_property_t *prop;
+    aliases = ofw_tree_lookup("/aliases");
+    if (!aliases)
+        panic("Cannot find '/aliases'.");
+    /* "def-cn" = "default console" */
+    prop = ofw_tree_getprop(aliases, "def-cn");
+    if ((!prop) || (!prop->value) || (str_cmp(prop->value, "/sgcn") != 0)) {
+        standard_console_init(aliases);
+    } else {
+        serengeti_init();
     }
 }
 /** Acquire console back for kernel
  *
  */
 void arch_grab_console(void)
 {
-    switch (kbd_type) {
-#ifdef CONFIG_Z8530
-    case KBD_Z8530:
-        z8530_grab();
-        break;
+#ifdef CONFIG_FB
+    scr_redraw();
 #endif
-#ifdef CONFIG_NS16550
-    case KBD_NS16550:
-        ns16550_grab();
-        break;
+#ifdef CONFIG_SGCN_KBD
+    sgcn_grab();
 #endif
-    default:
-        break;
-    }
 }
 /** Return console to userspace
 ,20 → 150,9
  */
 void arch_release_console(void)
 {
-    switch (kbd_type) {
-#ifdef CONFIG_Z8530
-    case KBD_Z8530:
-        z8530_release();
-        break;
+#ifdef CONFIG_SGCN_KBD
+    sgcn_release();
 #endif
-#ifdef CONFIG_NS16550
-    case KBD_NS16550:
-        ns16550_release();
-        break;
-#endif
-    default:
-        break;
-    }
 }
 /** @}

 /branches/arm/kernel/arch/sparc64/src/sparc64.c
 ,7 → 37,6
 #include <config.h>
 #include <arch/trap/trap.h>
 #include <arch/console.h>
-#include <proc/thread.h>
 #include <console/console.h>
 #include <arch/boot/boot.h>
 #include <arch/arch.h>
 ,10 → 46,11
 #include <genarch/ofw/ofw_tree.h>
 #include <userspace.h>
 #include <ddi/irq.h>
+#include <string.h>
 bootinfo_t bootinfo;
-/** Perform sparc64 specific initialization before main_bsp() is called. */
+/** Perform sparc64-specific initialization before main_bsp() is called. */
 void arch_pre_main(void)
 {
     /* Copy init task info. */
 ,6 → 61,8
     for (i = 0; i < bootinfo.taskmap.count; i++) {
         init.tasks[i].addr = (uintptr_t) bootinfo.taskmap.tasks[i].addr;
         init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
+        str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
+            bootinfo.taskmap.tasks[i].name);
     }
     /* Copy boot allocations info. */
 ,8 → 88,6
          * But we only create 128 buckets.
          */
         irq_init(1 << 11, 128);
-        standalone_sparc64_console_init();
     }
 }
 ,18 → 101,7
 void arch_post_smp_init(void)
 {
-    static thread_t *t = NULL;
-    if (!t) {
-        /*
-             * Create thread that polls keyboard.
-             */
-        t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
-        if (!t)
-            panic("cannot create kkbdpoll\n");
-        thread_ready(t);
-    }
+    standalone_sparc64_console_init();
 }
 /** Calibrate delay loop.
 ,5 → 150,19
     while (1);
 }
+/** Construct function pointer
+ *
+ * @param fptr   function pointer structure
+ * @param addr   function address
+ * @param caller calling function address
+ *
+ * @return address of the function pointer
+ *
+ */
+void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
+{
+    return addr;
+}
 /** @}
  */

 /branches/arm/kernel/arch/sparc64/src/ddi/ddi.c
 ,7 → 41,7
  * Interrupts are disabled and task is locked.
  *
  * @param task Task.
- * @param ioaddr Startign I/O space address.
+ * @param ioaddr Starting I/O space address.
  * @param size Size of the enabled I/O range.
  *
  * @return 0 on success or an error code from errno.h.

 /branches/arm/kernel/arch/sparc64/src/cpu/cpu.c
 ,12 → 32,46
 /** @file
  */
+#include <arch/cpu_family.h>
 #include <cpu.h>
 #include <arch.h>
 #include <genarch/ofw/ofw_tree.h>
 #include <arch/drivers/tick.h>
 #include <print.h>
+#include <arch/cpu_node.h>
+/**
+ * Finds out the clock frequency of the current CPU.
+ *
+ * @param node  node representing the current CPU in the OFW tree
+ * @return  clock frequency if "node" is the current CPU and no error
+ *      occurs, -1 if "node" is not the current CPU or on error
+ */
+static int find_cpu_frequency(ofw_tree_node_t *node)
+{
+    ofw_tree_property_t *prop;
+    uint32_t mid;
+    /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */
+    prop = ofw_tree_getprop(node, "upa-portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "portid");
+    if ((!prop) || (!prop->value))
+        prop = ofw_tree_getprop(node, "cpuid");
+    if (prop && prop->value) {
+        mid = *((uint32_t *) prop->value);
+        if (mid == CPU->arch.mid) {
+            prop = ofw_tree_getprop(node, "clock-frequency");
+            if (prop && prop->value) {
+                return *((uint32_t *) prop->value);
+            }
+        }
+    }
+    return -1;
+}
 /** Perform sparc64 specific initialization of the processor structure for the
  * current processor.
  */
 ,34 → 78,37
 void cpu_arch_init(void)
 {
     ofw_tree_node_t *node;
-    uint32_t mid;
     uint32_t clock_frequency = 0;
-    upa_config_t upa_config;
-    upa_config.value = upa_config_read();
-    CPU->arch.mid = upa_config.mid;
+    CPU->arch.mid = read_mid();
     /*
      * Detect processor frequency.
      */
-    node = ofw_tree_find_child_by_device_type(ofw_tree_lookup("/"), "cpu");
-    while (node) {
-        ofw_tree_property_t *prop;
-        prop = ofw_tree_getprop(node, "upa-portid");
-        if (prop && prop->value) {
-            mid = *((uint32_t *) prop->value);
-            if (mid == CPU->arch.mid) {
-                prop = ofw_tree_getprop(node,
-                    "clock-frequency");
-                if (prop && prop->value)
-                    clock_frequency = *((uint32_t *)
-                        prop->value);
-            }
+    if (is_us() || is_us_iii()) {
+        node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
+        while (node) {
+            int f = find_cpu_frequency(node);
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            node = ofw_tree_find_peer_by_device_type(node, "cpu");
         }
-        node = ofw_tree_find_peer_by_device_type(node, "cpu");
+    } else if (is_us_iv()) {
+        node = ofw_tree_find_child(cpus_parent(), "cmp");
+        while (node) {
+            int f;
+            f = find_cpu_frequency(
+                ofw_tree_find_child(node, "cpu@0"));
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            f = find_cpu_frequency(
+                ofw_tree_find_child(node, "cpu@1"));
+            if (f != -1)
+                clock_frequency = (uint32_t) f;
+            node = ofw_tree_find_peer_by_name(node, "cmp");
+        }
     }
     CPU->arch.clock_frequency = clock_frequency;
     tick_init();
 }
 ,6 → 161,15
     case IMPL_ULTRASPARCIII:
         impl = "UltraSPARC III";
         break;
+    case IMPL_ULTRASPARCIII_PLUS:
+        impl = "UltraSPARC III+";
+        break;
+    case IMPL_ULTRASPARCIII_I:
+        impl = "UltraSPARC IIIi";
+        break;
+    case IMPL_ULTRASPARCIV:
+        impl = "UltraSPARC IV";
+        break;
     case IMPL_ULTRASPARCIV_PLUS:
         impl = "UltraSPARC IV+";
         break;

 /branches/arm/kernel/arch/sparc64/src/proc/thread.c
 ,9 → 34,8
 #include <proc/thread.h>
 #include <arch/proc/thread.h>
-#include <mm/frame.h>
-#include <mm/page.h>
-#include <arch/mm/page.h>
+#include <mm/slab.h>
+#include <arch/trap/regwin.h>
 #include <align.h>
 void thr_constructor_arch(thread_t *t)
 ,12 → 49,12
 void thr_destructor_arch(thread_t *t)
 {
     if (t->arch.uspace_window_buffer) {
+        uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
         /*
          * Mind the possible alignment of the userspace window buffer
          * belonging to a killed thread.
          */
-        frame_free(KA2PA(ALIGN_DOWN((uintptr_t)
-            t->arch.uspace_window_buffer, PAGE_SIZE)));
+        free((uint8_t *) ALIGN_DOWN(uw_buf, UWB_ALIGNMENT));
     }
 }
 ,7 → 66,7
          * The thread needs userspace window buffer and the object
          * returned from the slab allocator doesn't have any.
          */
-        t->arch.uspace_window_buffer = frame_alloc(ONE_FRAME, FRAME_KA);
+        t->arch.uspace_window_buffer = malloc(UWB_ASIZE, 0);
     } else {
         uintptr_t uw_buf = (uintptr_t) t->arch.uspace_window_buffer;
 ,7 → 75,7
          * belonging to a killed thread.
          */
         t->arch.uspace_window_buffer = (uint8_t *) ALIGN_DOWN(uw_buf,
-            PAGE_SIZE);
+            UWB_ASIZE);
     }
 }

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