/branches/arm/kernel/arch/arm32/src/mm/tlb.c |
---|
45,6 → 45,7 |
asm volatile ( |
"eor r1, r1\n" |
"MCR p15, 0, r1, c8, c7, 0\n" // see ARM Architecture reference relE 3.7.7 p.528 |
::: "r1" |
); |
} |
64,10 → 65,11 |
static inline void invlpg(uintptr_t page) |
{ |
asm volatile ( |
"MCR p15, 0, %0, c8, c7, 1" |
: /* no output */ |
: "r"(page) /* input */ |
); |
"MCR p15, 0, %0, c8, c7, 1" |
: /* no output */ |
: "r"(page) /* input */ |
); |
} |
/** Invalidate TLB entries for specified page range belonging to specified address space. |