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Ignore whitespace Rev 4633 → Rev 4634

/branches/arm/kernel/arch/arm32/src/drivers/qemu.c
43,6 → 43,8
#include <print.h>
#include <ddi/device.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <arch/mm/frame.h>
#include <arch/machine.h>
#include <arch/debug/print.h>
#include <genarch/fb/fb.h>
49,12 → 51,11
#include <genarch/fb/visuals.h>
 
/* Addresses of devices. */
#define QEMU_ICP_VIDEORAM 0x16000000
#define QEMU_ICP_UART 0x16000000
#define QEMU_ICP_KBD 0x18000000
#define ICP_KBD_STAT 0x04
#define ICP_KBD_DATA 0x08
#define ICP_KBD_INTR_STAT 0x10
#define QEMU_ICP_HALT_OFFSET 0x10
#define QEMU_ICP_RTC 0x13000000
#define QEMU_ICP_RTC1_LOAD_OFFSET 0x100
#define QEMU_ICP_RTC1_READ_OFFSET 0x104
65,22 → 66,35
#define QEMU_ICP_IRQC 0x14000000
#define QEMU_ICP_IRQC_MASK_OFFSET 0xC
#define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8
#define QEMU_ICP_MP 0x11000000
#define QEMU_ICP_MP_MEMSIZE_OFFSET 0x0090
#define QEMU_ICP_FB 0x01000000
 
#define QEMU_ICP_FB 0x00800000
#define QEMU_ICP_FB_FRAME (QEMU_ICP_FB >> 12)
#define QEMU_ICP_FB_NUM_FRAME 300
#define ICP_VGA 0xC0000000
#define ICP_CMCR 0x10000000
#define QEMU_ICP_SDRAM_MASK 0x1C
#define QEMU_ICP_SDRAMCR_OFFSET 0x20
 
/* IRQs */
#define QEMU_ICP_KBD_IRQ 3
#define QEMU_ICP_TIMER_IRQ 6
 
#define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+QEMU_ICP_SDRAMCR_OFFSET) & QEMU_ICP_SDRAM_MASK) >> 2)])
 
static qemu_icp_hw_map_t qemu_icp_hw_map;
static irq_t qemu_icp_timer_irq;
 
static bool hw_map_init_called = false;
static bool vga_init = false;
uint32_t sdram[8] = {
16777216, /* 16mb */
33554432, /* 32mb */
67108864, /* 64mb */
134217728, /* 128mb */
268435456, /* 256mb */
0, /* Reserverd */
0, /* Reserverd */
0 /* Reserverd */
};
 
void icp_vga_init(void);
 
135,7 → 149,7
/** Initializes #qemu_icp_hw_map. */
void qemu_icp_hw_map_init(void)
{
qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
qemu_icp_hw_map.uart = hw_map(QEMU_ICP_UART, PAGE_SIZE);
qemu_icp_hw_map.kbd_ctrl = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
qemu_icp_hw_map.kbd_stat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_STAT;
qemu_icp_hw_map.kbd_data = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_DATA;
149,13 → 163,11
 
qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
QEMU_ICP_IRQC_UNMASK_OFFSET;
qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_UNMASK_OFFSET;
qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
qemu_icp_hw_map.sdramcr = qemu_icp_hw_map.cmcr + QEMU_ICP_SDRAMCR_OFFSET;
qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
 
//icp_vga_init();
 
hw_map_init_called = true;
}
 
251,8 → 263,12
*/
size_t qemu_icp_get_memory_size(void)
{
//return *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET));
return 0x2000000;
if (hw_map_init_called) {
return (sdram[((*(uint32_t *)qemu_icp_hw_map.sdramcr & QEMU_ICP_SDRAM_MASK) >> 2)]);
} else {
return SDRAM_SIZE;
}
}
 
/** Prints a character.
265,7 → 281,7
if (!hw_map_init_called) {
addr = (char *) QEMU_ICP_KBD;
} else {
addr = (char *) qemu_icp_hw_map.videoram;
addr = (char *) qemu_icp_hw_map.uart;
}
if (ch == '\n')
279,7 → 295,7
while (1);
}
 
/** Gxemul specific interrupt exception handler.
/** interrupt exception handler.
*
* Determines sources of the interrupt from interrupt controller and
* calls high-level handlers for them.
321,6 → 337,15
return (uintptr_t) QEMU_ICP_FB;
}
 
/*
* Integrator specific frame initialization
*/
void
qemu_icp_frame_init(void)
{
frame_mark_unavailable(QEMU_ICP_FB_FRAME, QEMU_ICP_FB_NUM_FRAME);
}
 
 
/** @}
*/