55,8 → 55,8 |
#define QEMU_ICP_RTC_FREQ_OFFSET 0x100 |
#define QEMU_ICP_RTC_ACK_OFFSET 0x110 |
#define QEMU_ICP_IRQC 0x14000000 |
#define QEMU_ICP_IRQC_MASK_OFFSET 0x8 |
#define QEMU_ICP_IRQC_UNMASK_OFFSET 0xC |
#define QEMU_ICP_IRQC_MASK_OFFSET 0xC |
#define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8 |
#define QEMU_ICP_MP 0x11000000 |
#define QEMU_ICP_MP_MEMSIZE_OFFSET 0x0090 |
#define QEMU_ICP_FB 0x94000 |
65,8 → 65,8 |
#define ICP_CMCR 0x10000000 |
|
/* IRQs */ |
#define QEMU_ICP_KBD_IRQ 3 |
#define QEMU_ICP_TIMER_IRQ 5 |
#define QEMU_ICP_KBD_IRQ 0x03 |
#define QEMU_ICP_TIMER_IRQ 0x05 |
|
static qemu_icp_hw_map_t qemu_icp_hw_map; |
static chardev_t console; |
128,7 → 128,7 |
*/ |
static inline void qemu_icp_irqc_unmask(uint32_t irq) |
{ |
*((uint32_t *) qemu_icp_hw_map.irqc_unmask) = irq; |
*((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq; |
} |
|
/** Initializes the icp frame buffer */ |