Subversion Repositories HelenOS

Compare Revisions

Ignore whitespace Rev 2420 → Rev 2464

/branches/arm/kernel/arch/arm32/include/asm/boot.h
36,7 → 36,6
#ifndef KERN_arm32_ASM_BOOT_H_
#define KERN_arm32_ASM_BOOT_H_
 
 
/** Size of a temporary stack used for initial kernel start. */
#define TEMP_STACK_SIZE 0x100
 
52,9 → 51,9
* @param boot_bootinfo Struct holding information about loaded tasks.
* @param bootinfo_size Size of the bootinfo structure.
*/
void kernel_image_start(void *entry, void *boot_bootinfo, unsigned int bootinfo_size);
extern void kernel_image_start(void *entry, void *boot_bootinfo,
unsigned int bootinfo_size);
 
 
#endif
 
#endif
/branches/arm/kernel/arch/arm32/include/regutils.h
37,7 → 37,6
#ifndef KERN_arm32_REGUTILS_H_
#define KERN_arm32_REGUTILS_H_
 
 
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
#define STATUS_REG_MODE_MASK 0x1f
 
53,21 → 52,20
#define UNDEFINED_MODE 0x1b
#define SYSTEM_MODE 0x1f
 
 
/* [CS]PRS manipulation macros */
#define GEN_STATUS_READ(nm,reg) \
static inline uint32_t nm## _status_reg_read(void) \
{ \
uint32_t retval; \
asm volatile("mrs %0, " #reg : "=r"(retval)); \
return retval; \
}
static inline uint32_t nm## _status_reg_read(void) \
{ \
uint32_t retval; \
asm volatile("mrs %0, " #reg : "=r" (retval)); \
return retval; \
}
 
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
{ \
asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \
}
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
{ \
asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \
}
 
 
/** Returns the value of CPSR (Current Program Status Register). */
/branches/arm/kernel/arch/arm32/include/cycle.h
36,7 → 36,6
#ifndef KERN_arm32_CYCLE_H_
#define KERN_arm32_CYCLE_H_
 
 
/** Returns count of CPU cycles.
*
* No such instruction on ARM to get count of cycles.
48,7 → 47,6
return 0;
}
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/debug/print.h
52,6 → 52,5
 
#endif
 
 
/** @}
*/
/branches/arm/kernel/arch/arm32/include/machine.h
103,19 → 103,19
 
 
#ifdef MACHINE_GXEMUL_TESTARM
# define machine_console_init(devno) gxemul_console_init(devno)
# define machine_grab_console gxemul_grab_console
# define machine_release_console gxemul_release_console
# define machine_hw_map_init gxemul_hw_map_init
# define machine_timer_irq_start gxemul_timer_irq_start
# define machine_cpu_halt gxemul_cpu_halt
# define machine_get_memory_size gxemul_get_memory_size
# define machine_debug_putc(ch) gxemul_debug_putc(ch)
# define machine_irq_exception(exc_no, istate) gxemul_irq_exception(exc_no, istate)
# define machine_get_fb_address gxemul_get_fb_address
#define machine_console_init(devno) gxemul_console_init(devno)
#define machine_grab_console gxemul_grab_console
#define machine_release_console gxemul_release_console
#define machine_hw_map_init gxemul_hw_map_init
#define machine_timer_irq_start gxemul_timer_irq_start
#define machine_cpu_halt gxemul_cpu_halt
#define machine_get_memory_size gxemul_get_memory_size
#define machine_debug_putc(ch) gxemul_debug_putc(ch)
#define machine_irq_exception(exc_no, istate) \
gxemul_irq_exception(exc_no, istate)
#define machine_get_fb_address gxemul_get_fb_address
#endif
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/types.h
85,7 → 85,6
unsigned dummy : 32;
} pte_t;
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/stack.h
38,7 → 38,9
 
#define STACK_ITEM_SIZE 4
 
/** see <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for details */
/** See <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for
* details
*/
#define STACK_ALIGNMENT 8
 
#endif
/branches/arm/kernel/arch/arm32/include/atomic.h
46,10 → 46,10
static inline long atomic_add(atomic_t *val, int i)
{
int ret;
volatile long * mem = &(val->count);
volatile long *mem = &(val->count);
 
asm volatile (
"1: \n"
"1:\n"
"ldr r2, [%1] \n"
"add r3, r2, %2 \n"
"str r3, %0 \n"
65,53 → 65,63
return ret;
}
 
 
/** Atomic increment.
*
* @param val Variable to be incremented.
*/
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
static inline void atomic_inc(atomic_t *val)
{
atomic_add(val, 1);
}
 
 
/** Atomic decrement.
*
* @param val Variable to be decremented.
*/
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
static inline void atomic_dec(atomic_t *val) {
atomic_add(val, -1);
}
 
 
/** Atomic pre-increment.
*
* @param val Variable to be incremented.
* @return Value after incrementation.
*/
static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); }
static inline long atomic_preinc(atomic_t *val)
{
return atomic_add(val, 1);
}
 
 
/** Atomic pre-decrement.
*
* @param val Variable to be decremented.
* @return Value after decrementation.
*/
static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); }
static inline long atomic_predec(atomic_t *val)
{
return atomic_add(val, -1);
}
 
 
/** Atomic post-increment.
*
* @param val Variable to be incremented.
* @return Value before incrementation.
*/
static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; }
static inline long atomic_postinc(atomic_t *val)
{
return atomic_add(val, 1) - 1;
}
 
 
/** Atomic post-decrement.
*
* @param val Variable to be decremented.
* @return Value before decrementation.
*/
static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; }
static inline long atomic_postdec(atomic_t *val)
{
return atomic_add(val, -1) + 1;
}
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/proc/thread.h
47,4 → 47,3
 
/** @}
*/
 
/branches/arm/kernel/arch/arm32/include/asm.h
46,7 → 46,6
{
}
 
 
/** Return base address of current stack.
*
* Return the base address of the current stack.
59,17 → 58,16
asm volatile (
"and %0, sp, %1\n"
: "=r" (v)
: "r" (~(STACK_SIZE-1))
: "r" (~(STACK_SIZE - 1))
);
return v;
}
 
 
extern void cpu_halt(void);
extern void asm_delay_loop(uint32_t t);
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, uintptr_t entry);
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg,
uintptr_t entry);
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/mm/page.h
40,7 → 40,6
#include <mm/mm.h>
#include <arch/exception.h>
 
 
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
 
56,12 → 55,12
 
#ifdef KERNEL
 
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
 
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH (2<<8) // 256
/* coarse page tables used (256 * 4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */
 
#define PTL0_SIZE_ARCH FOUR_FRAMES
#define PTL1_SIZE_ARCH 0
73,59 → 72,75
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
(ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
(ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL0_ADDRESS_ARCH(ptl0) \
(set_ptl0_addr((pte_level0_t *) (ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
(((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
(((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
 
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
#define PTE_VALID_ARCH(pte) \
(*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) \
(((pte_level0_t *) (pte))->descriptor_type != 0)
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
#define PTE_GET_FRAME_ARCH(pte) \
(((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
 
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
#define PTE_WRITABLE_ARCH(pte) \
(((pte_level1_t *) (pte))->access_permission_0 == \
PTE_AP_USER_RW_KERNEL_RW)
 
#define PTE_EXECUTABLE_ARCH(pte) 1
#define PTE_EXECUTABLE_ARCH(pte) \
1
 
 
#ifndef __ASM__
 
/** Level 0 page table entry. */
typedef struct {
 
/* 01b for coarse tables, see below for details */
/* 0b01 for coarse tables, see below for details */
unsigned descriptor_type : 2;
unsigned impl_specific : 3;
unsigned domain : 4;
unsigned should_be_zero : 1;
 
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
* or large (64KB) pages. ARM also supports fine 2nd level page tables that
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
* with 1KB per the coarse table)
*/
/* Pointer to the coarse 2nd level page table (holding entries for small
* (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
* tables that may hold even tiny pages (1KB) but they are bigger (4KB
* per table in comparison with 1KB per the coarse table)
*/
unsigned coarse_table_addr : 22;
} ATTRIBUTE_PACKED pte_level0_t;
 
 
/** Level 1 page table entry (small (4KB) pages used). */
typedef struct {
 
147,28 → 162,28
/* Level 1 page tables access permissions */
 
/** User mode: no access, privileged mode: no access. */
#define PTE_AP_USER_NO_KERNEL_NO 0
#define PTE_AP_USER_NO_KERNEL_NO 0
 
/** User mode: no access, privileged mode: read/write. */
#define PTE_AP_USER_NO_KERNEL_RW 1
#define PTE_AP_USER_NO_KERNEL_RW 1
 
/** User mode: read only, privileged mode: read/write. */
#define PTE_AP_USER_RO_KERNEL_RW 2
#define PTE_AP_USER_RO_KERNEL_RW 2
 
/** User mode: read/write, privileged mode: read/write. */
#define PTE_AP_USER_RW_KERNEL_RW 3
#define PTE_AP_USER_RW_KERNEL_RW 3
 
 
/* pte_level0_t and pte_level1_t descriptor_type flags */
 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
#define PTE_DESCRIPTOR_NOT_PRESENT 0
#define PTE_DESCRIPTOR_NOT_PRESENT 0
 
/** pte_level0_t coarse page table flag (used in descriptor_type). */
#define PTE_DESCRIPTOR_COARSE_TABLE 1
#define PTE_DESCRIPTOR_COARSE_TABLE 1
 
/** pte_level1_t small page table flag (used in descriptor type). */
#define PTE_DESCRIPTOR_SMALL_PAGE 2
#define PTE_DESCRIPTOR_SMALL_PAGE 2
 
 
/** Sets the address of level 0 page table.
175,7 → 190,7
*
* @param pt Pointer to the page table to set.
*/
static inline void set_ptl0_addr( pte_level0_t* pt)
static inline void set_ptl0_addr( pte_level0_t *pt)
{
asm volatile (
"mcr p15, 0, %0, c2, c0, 0 \n"
193,18 → 208,13
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
pte_level0_t *p = &pt[i];
int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
 
return
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
( 1 << PAGE_USER_SHIFT ) |
( 1 << PAGE_READ_SHIFT ) |
( 1 << PAGE_WRITE_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE_SHIFT )
;
return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
(1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
(1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
}
 
 
/** Returns level 1 page table entry flags.
*
* @param pt Level 1 page table.
214,17 → 224,18
{
pte_level1_t *p = &pt[i];
 
return
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( p->bufferable << PAGE_CACHEABLE )
;
int dt = p->descriptor_type;
int ap = p->access_permission_0;
 
return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
(1 << PAGE_EXEC_SHIFT) |
(p->bufferable << PAGE_CACHEABLE);
}
 
 
240,11 → 251,14
 
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
// ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied
p->should_be_zero = 1;
/*
* Ensures that the entry will be recognized as valid when
* PTE_VALID_ARCH applied.
*/
p->should_be_zero = 1;
} else {
p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
p->should_be_zero = 0;
p->should_be_zero = 0;
}
}
 
264,11 → 278,11
pte_level1_t *p = &pt[i];
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
p->access_permission_3 = 1;
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
p->access_permission_3 = 1;
} else {
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
p->access_permission_3 = p->access_permission_0;
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
p->access_permission_3 = p->access_permission_0;
}
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
275,18 → 289,19
 
/* default access permission */
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
p->access_permission_2 = p->access_permission_3 =
PTE_AP_USER_NO_KERNEL_RW;
 
if (flags & PAGE_USER) {
if (flags & PAGE_READ) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
PTE_AP_USER_RO_KERNEL_RW;
p->access_permission_2 = p->access_permission_3 =
PTE_AP_USER_RO_KERNEL_RW;
}
if (flags & PAGE_WRITE) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
PTE_AP_USER_RW_KERNEL_RW;
p->access_permission_2 = p->access_permission_3 =
PTE_AP_USER_RW_KERNEL_RW;
}
}
}
303,4 → 318,3
 
/** @}
*/
 
/branches/arm/kernel/arch/arm32/include/mm/asid.h
44,12 → 44,12
 
typedef uint8_t asid_t;
 
/*
* This works due to fact that this file is never included alone but only
* through "generic/include/mm/asid.h" where ASID_START is defined.
*/
#define asid_get() (ASID_START + 1)
 
/* this works due to fact that this file is never included alone but only
through "generic/include/mm/asid.h" where ASID_START is defined
*/
#define asid_get() ( ASID_START + 1 )
 
#define asid_put(asid)
 
#endif
/branches/arm/kernel/arch/arm32/include/mm/page_fault.h
1,92 → 1,89
/*
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup arm32mm
* @{
*/
/** @file
* @brief Page fault related declarations.
*/
 
#ifndef KERN_arm32_PAGE_FAULT_H_
#define KERN_arm32_PAGE_FAULT_H_
 
#include <arch/types.h>
 
 
/** Decribes CP15 "fault status register" (FSR). */
typedef struct {
unsigned status : 3;
unsigned domain : 4;
unsigned zero : 1;
unsigned should_be_zero : 24;
} ATTRIBUTE_PACKED fault_status_t;
 
 
/** Help union used for casting integer value into #fault_status_t. */
typedef union {
fault_status_t fs;
uint32_t dummy;
} fault_status_union_t;
 
 
/** Simplified description of instruction code.
*
* @note Used for recognizing memory access instructions.
* @see ARM architecture reference (chapter 3.1)
*/
typedef struct {
unsigned dummy1 : 4;
unsigned bit4 : 1;
unsigned bits567 : 3;
unsigned dummy : 12;
unsigned access : 1;
unsigned opcode : 4;
unsigned type : 3;
unsigned condition : 4;
} ATTRIBUTE_PACKED instruction_t;
 
 
/** Help union used for casting pc register (uint_32_t) value into
* #instruction_t pointer.
*/
typedef union {
instruction_t *instr;
uint32_t pc;
} instruction_union_t;
 
 
extern void prefetch_abort(int n, istate_t *istate);
extern void data_abort(int n, istate_t *istate);
 
 
#endif
 
/** @}
*/
 
/*
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup arm32mm
* @{
*/
/** @file
* @brief Page fault related declarations.
*/
 
#ifndef KERN_arm32_PAGE_FAULT_H_
#define KERN_arm32_PAGE_FAULT_H_
 
#include <arch/types.h>
 
 
/** Decribes CP15 "fault status register" (FSR). */
typedef struct {
unsigned status : 3;
unsigned domain : 4;
unsigned zero : 1;
unsigned should_be_zero : 24;
} ATTRIBUTE_PACKED fault_status_t;
 
 
/** Help union used for casting integer value into #fault_status_t. */
typedef union {
fault_status_t fs;
uint32_t dummy;
} fault_status_union_t;
 
 
/** Simplified description of instruction code.
*
* @note Used for recognizing memory access instructions.
* @see ARM architecture reference (chapter 3.1)
*/
typedef struct {
unsigned dummy1 : 4;
unsigned bit4 : 1;
unsigned bits567 : 3;
unsigned dummy : 12;
unsigned access : 1;
unsigned opcode : 4;
unsigned type : 3;
unsigned condition : 4;
} ATTRIBUTE_PACKED instruction_t;
 
 
/** Help union used for casting pc register (uint_32_t) value into
* #instruction_t pointer.
*/
typedef union {
instruction_t *instr;
uint32_t pc;
} instruction_union_t;
 
extern void prefetch_abort(int n, istate_t *istate);
extern void data_abort(int n, istate_t *istate);
 
#endif
 
/** @}
*/
/branches/arm/kernel/arch/arm32/include/context.h
46,7 → 46,9
 
#include <arch/types.h>
 
/** Thread context containing registers that must be preserved across function calls. */
/** Thread context containing registers that must be preserved across function
* calls.
*/
typedef struct {
uint32_t cpu_mode;
uintptr_t sp;
/branches/arm/kernel/arch/arm32/include/cpu.h
42,24 → 42,22
 
/** Struct representing ARM CPU identifiaction. */
typedef struct {
 
/** Implementator (vendor) number. */
uint32_t imp_num;
uint32_t imp_num;
 
/** Variant number. */
uint32_t variant_num;
uint32_t variant_num;
 
/** Architecture number. */
uint32_t arch_num;
uint32_t arch_num;
 
/** Primary part number. */
uint32_t prim_part_num;
uint32_t prim_part_num;
 
/** Revision number. */
uint32_t rev_num;
uint32_t rev_num;
} cpu_arch_t;
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/drivers/gxemul.h
48,7 → 48,6
/** Timer frequency */
#define GXEMUL_TIMER_FREQ 100
 
 
/** Struct containing mappings of gxemul HW devices into kernel part
* of virtual address space.
*/
63,7 → 62,6
uintptr_t irqc_unmask;
} gxemul_hw_map_t;
 
 
extern void gxemul_hw_map_init(void);
extern void gxemul_console_init(devno_t devno);
extern void gxemul_release_console(void);
75,7 → 73,6
extern size_t gxemul_get_memory_size(void);
extern uintptr_t gxemul_get_fb_address(void);
 
 
#endif
 
/** @}