| 37,8 → 37,9 |
|---|
| #ifndef KERN_arm32_REGUTILS_H_ |
| #define KERN_arm32_REGUTILS_H_ |
| |
| |
| #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
| #define STATUS_REG_MODE_MASK 0x1F |
| #define STATUS_REG_MODE_MASK 0x1f |
| |
| #define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
| |
| 53,13 → 54,12 |
|---|
| #define SYSTEM_MODE 0x1f |
| |
| |
| |
| /* [CS]PRS manipulation macros */ |
| #define GEN_STATUS_READ(nm,reg) \ |
| static inline uint32_t nm## _status_reg_read(void) \ |
| { \ |
| uint32_t retval; \ |
| asm("mrs %0, " #reg : "=r"(retval)); \ |
| asm volatile("mrs %0, " #reg : "=r"(retval)); \ |
| return retval; \ |
| } |
| |
| 66,26 → 66,22 |
|---|
| #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
| static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
| { \ |
| asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
| asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
| } |
| |
| |
| /** Returns the value of CPSR (Current Program Status Register). |
| */ |
| /** Returns the value of CPSR (Current Program Status Register). */ |
| GEN_STATUS_READ(current, cpsr) |
| |
| |
| /** Sets control bits of CPSR |
| */ |
| /** Sets control bits of CPSR. */ |
| GEN_STATUS_WRITE(current, cpsr, control, c); |
| |
| |
| /** Returns the value of SPSR (Saved Program Status Register). |
| */ |
| /** Returns the value of SPSR (Saved Program Status Register). */ |
| GEN_STATUS_READ(saved, spsr) |
| |
| |
| |
| #endif |
| |
| /** @} |