37,29 → 37,29 |
#ifndef KERN_arm32_REGUTILS_H_ |
#define KERN_arm32_REGUTILS_H_ |
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#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1F |
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#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1f |
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#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
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/* ARM Processor Operation Modes */ |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
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/* [CS]PRS manipulation macros */ |
#define GEN_STATUS_READ(nm,reg) \ |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm("mrs %0, " #reg : "=r"(retval)); \ |
asm volatile("mrs %0, " #reg : "=r"(retval)); \ |
return retval; \ |
} |
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66,26 → 66,22 |
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
} |
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/** Returns the value of CPSR (Current Program Status Register). |
*/ |
/** Returns the value of CPSR (Current Program Status Register). */ |
GEN_STATUS_READ(current, cpsr) |
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/** Sets control bits of CPSR |
*/ |
/** Sets control bits of CPSR. */ |
GEN_STATUS_WRITE(current, cpsr, control, c); |
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/** Returns the value of SPSR (Saved Program Status Register). |
*/ |
/** Returns the value of SPSR (Saved Program Status Register). */ |
GEN_STATUS_READ(saved, spsr) |
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#endif |
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/** @} |