WebSVN – HelenOS – Path Comparison – / – /branches/arm/kernel/arch/arm32/include/mm Rev 2417 and /branches/arm/kernel/arch/arm32/include/mm Rev 2721

Ignore whitespace Rev 2417 → Rev 2721

 /branches/arm/kernel/arch/arm32/include/mm/page.h
 ,7 → 40,6
 #include <mm/mm.h>
 #include <arch/exception.h>
 #define PAGE_WIDTH  FRAME_WIDTH
 #define PAGE_SIZE   FRAME_SIZE
 ,12 → 55,12
 #ifdef KERNEL
-#define PTL0_ENTRIES_ARCH   (2<<12)    // 4096
+#define PTL0_ENTRIES_ARCH   (2 << 12)   /* 4096 */
 #define PTL1_ENTRIES_ARCH   0
 #define PTL2_ENTRIES_ARCH   0
-/* coarse page tables used (256*4 = 1KB per page) */
-#define PTL3_ENTRIES_ARCH   (2<<8)     // 256
+/* coarse page tables used (256 * 4 = 1KB per page) */
+#define PTL3_ENTRIES_ARCH   (2 << 8)    /* 256 */
 #define PTL0_SIZE_ARCH      FOUR_FRAMES
 #define PTL1_SIZE_ARCH      0
 ,59 → 72,75
 #define PTL2_INDEX_ARCH(vaddr)  0
 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
-#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
-#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
+    ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
+#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
+    (ptl1)
+#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
+    (ptl2)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
+    ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
-#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
+#define SET_PTL0_ADDRESS_ARCH(ptl0) \
+    (set_ptl0_addr((pte_level0_t *) (ptl0)))
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
+    (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
+    (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
-#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
-#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
-#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
-#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
+#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
+    get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i))
+#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
+    PAGE_PRESENT
+#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
+    PAGE_PRESENT
+#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
+    get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i))
-#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
+#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
+    set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x))
 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
-#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
+#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
+    set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x))
-#define PTE_VALID_ARCH(pte)             (*((uint32_t *) (pte)) != 0)
-#define PTE_PRESENT_ARCH(pte)           ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
+#define PTE_VALID_ARCH(pte) \
+    (*((uint32_t *) (pte)) != 0)
+#define PTE_PRESENT_ARCH(pte) \
+    (((pte_level0_t *) (pte))->descriptor_type != 0)
 /* pte should point into ptl3 */
-#define PTE_GET_FRAME_ARCH(pte)         ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
+#define PTE_GET_FRAME_ARCH(pte) \
+    (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
 /* pte should point into ptl3 */
-#define PTE_WRITABLE_ARCH(pte)          ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
+#define PTE_WRITABLE_ARCH(pte) \
+    (((pte_level1_t *) (pte))->access_permission_0 == \
+        PTE_AP_USER_RW_KERNEL_RW)
-#define PTE_EXECUTABLE_ARCH(pte)        1
+#define PTE_EXECUTABLE_ARCH(pte) \
 #ifndef __ASM__
 /** Level 0 page table entry. */
 typedef struct {
-    /* 01b for coarse tables, see below for details */
+    /* 0b01 for coarse tables, see below for details */
     unsigned descriptor_type     : 2;
     unsigned impl_specific       : 3;
     unsigned domain              : 4;
     unsigned should_be_zero      : 1;
-    /* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
-     * or large (64KB) pages. ARM also supports fine 2nd level page tables that
-     * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
-     * with 1KB per the coarse table)
-    */
+    /* Pointer to the coarse 2nd level page table (holding entries for small
+     * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
+     * tables that may hold even tiny pages (1KB) but they are bigger (4KB
+     * per table in comparison with 1KB per the coarse table)
+     */
     unsigned coarse_table_addr   : 22;
 } ATTRIBUTE_PACKED pte_level0_t;
 /** Level 1 page table entry (small (4KB) pages used). */
 typedef struct {
 ,28 → 162,28
 /* Level 1 page tables access permissions */
 /** User mode: no access, privileged mode: no access. */
-#define PTE_AP_USER_NO_KERNEL_NO 0
+#define PTE_AP_USER_NO_KERNEL_NO    0
 /** User mode: no access, privileged mode: read/write. */
-#define PTE_AP_USER_NO_KERNEL_RW 1
+#define PTE_AP_USER_NO_KERNEL_RW    1
 /** User mode: read only, privileged mode: read/write. */
-#define PTE_AP_USER_RO_KERNEL_RW 2
+#define PTE_AP_USER_RO_KERNEL_RW    2
 /** User mode: read/write, privileged mode: read/write. */
-#define PTE_AP_USER_RW_KERNEL_RW 3
+#define PTE_AP_USER_RW_KERNEL_RW    3
 /* pte_level0_t and pte_level1_t descriptor_type flags */
 /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_NOT_PRESENT  0
+#define PTE_DESCRIPTOR_NOT_PRESENT  0
 /** pte_level0_t coarse page table flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_COARSE_TABLE 1
+#define PTE_DESCRIPTOR_COARSE_TABLE 1
 /** pte_level1_t small page table flag (used in descriptor type). */
-#define PTE_DESCRIPTOR_SMALL_PAGE   2
+#define PTE_DESCRIPTOR_SMALL_PAGE   2
 /** Sets the address of level 0 page table.
 ,7 → 190,7
  *
  * @param pt    Pointer to the page table to set.
  */
-static inline void set_ptl0_addr( pte_level0_t* pt)
+static inline void set_ptl0_addr( pte_level0_t *pt)
 {
     asm volatile (
         "mcr p15, 0, %0, c2, c0, 0 \n"
 ,18 → 208,13
 static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
 {
     pte_level0_t *p = &pt[i];
+    int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
-    return
-        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
-        ( 1 << PAGE_USER_SHIFT )  |
-        ( 1 << PAGE_READ_SHIFT )  |
-        ( 1 << PAGE_WRITE_SHIFT ) |
-        ( 1 << PAGE_EXEC_SHIFT )  |
-        ( 1 << PAGE_CACHEABLE_SHIFT  )
-    ;
+    return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
+        (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
+        (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
 }
 /** Returns level 1 page table entry flags.
  *
  *  @param pt     Level 1 page table.
 ,17 → 224,18
 {
     pte_level1_t *p = &pt[i];
-    return
-        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT)   << PAGE_PRESENT_SHIFT) |
-        ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT )  |
-        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT )  |
-        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
-        ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT )  |
-        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT )  |
-        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
-        ( 1 << PAGE_EXEC_SHIFT ) |
-        ( p->bufferable << PAGE_CACHEABLE )
-    ;
+    int dt = p->descriptor_type;
+    int ap = p->access_permission_0;
+    return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
+        ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
+        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
+        ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+        ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
+        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
+        ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+        (1 << PAGE_EXEC_SHIFT) |
+        (p->bufferable << PAGE_CACHEABLE);
 }
 ,11 → 251,14
     if (flags & PAGE_NOT_PRESENT) {
         p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-        // ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied
-        p->should_be_zero  = 1;
+        /*
+         * Ensures that the entry will be recognized as valid when
+         * PTE_VALID_ARCH applied.
+         */
+        p->should_be_zero = 1;
     } else {
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-        p->should_be_zero  = 0;
+        p->should_be_zero = 0;
     }
 }
 ,11 → 278,11
     pte_level1_t *p = &pt[i];
     if (flags & PAGE_NOT_PRESENT) {
-        p->descriptor_type      = PTE_DESCRIPTOR_NOT_PRESENT;
-        p->access_permission_3  = 1;
+        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
+        p->access_permission_3 = 1;
     } else {
-        p->descriptor_type      = PTE_DESCRIPTOR_SMALL_PAGE;
-        p->access_permission_3  = p->access_permission_0;
+        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+        p->access_permission_3 = p->access_permission_0;
     }
     p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 ,18 → 289,19
     /* default access permission */
     p->access_permission_0 = p->access_permission_1 =
-        p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
+        p->access_permission_2 = p->access_permission_3 =
+        PTE_AP_USER_NO_KERNEL_RW;
     if (flags & PAGE_USER)  {
         if (flags & PAGE_READ) {
             p->access_permission_0 = p->access_permission_1 =
-                p->access_permission_2 = p->access_permission_3 =
-                PTE_AP_USER_RO_KERNEL_RW;
+                p->access_permission_2 = p->access_permission_3 =
+                PTE_AP_USER_RO_KERNEL_RW;
         }
         if (flags & PAGE_WRITE) {
             p->access_permission_0 = p->access_permission_1 =
-                p->access_permission_2 = p->access_permission_3 =
-                PTE_AP_USER_RW_KERNEL_RW;
+                p->access_permission_2 = p->access_permission_3 =
+                PTE_AP_USER_RW_KERNEL_RW;
         }
     }
 }
 ,4 → 318,3
 /** @}
  */

 /branches/arm/kernel/arch/arm32/include/mm/asid.h
 ,12 → 44,12
 typedef uint8_t asid_t;
+/*
+ * This works due to fact that this file is never included alone but only
+ * through "generic/include/mm/asid.h" where ASID_START is defined.
+ */
+#define asid_get()      (ASID_START + 1)
-/* this works due to fact that this file is never included alone but only
-   through "generic/include/mm/asid.h" where ASID_START is defined
-*/
-#define asid_get()      ( ASID_START + 1 )
 #define asid_put(asid)
 #endif

 /branches/arm/kernel/arch/arm32/include/mm/page_fault.h
 ,92 → 1,89
-/*
- * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup arm32mm
- * @{
- */
-/** @file
- *  @brief Page fault related declarations.
- */
-#ifndef KERN_arm32_PAGE_FAULT_H_
-#define KERN_arm32_PAGE_FAULT_H_
-#include <arch/types.h>
-/** Decribes CP15 "fault status register" (FSR). */
-typedef struct {
-    unsigned status           : 3;
-    unsigned domain           : 4;
-    unsigned zero             : 1;
-    unsigned should_be_zero   : 24;
-} ATTRIBUTE_PACKED fault_status_t;
-/** Help union used for casting integer value into #fault_status_t. */
-typedef union {
-    fault_status_t    fs;
-    uint32_t          dummy;
-} fault_status_union_t;
-/** Simplified description of instruction code.
- *
- * @note Used for recognizing memory access instructions.
- * @see ARM architecture reference (chapter 3.1)
- */
-typedef struct {
-    unsigned dummy1        : 4;
-    unsigned bit4          : 1;
-    unsigned bits567       : 3;
-    unsigned dummy         : 12;
-    unsigned access        : 1;
-    unsigned opcode        : 4;
-    unsigned type          : 3;
-    unsigned condition     : 4;
-} ATTRIBUTE_PACKED instruction_t;
-/** Help union used for casting pc register (uint_32_t) value into
- *  #instruction_t pointer.
- */
-typedef union {
-    instruction_t   *instr;
-    uint32_t         pc;
-} instruction_union_t;
-extern void prefetch_abort(int n, istate_t *istate);
-extern void data_abort(int n, istate_t *istate);
-#endif
-/** @}
- */
+/*
+ * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup arm32mm
+ * @{
+ */
+/** @file
+ *  @brief Page fault related declarations.
+ */
+#ifndef KERN_arm32_PAGE_FAULT_H_
+#define KERN_arm32_PAGE_FAULT_H_
+#include <arch/types.h>
+/** Decribes CP15 "fault status register" (FSR). */
+typedef struct {
+    unsigned status           : 3;
+    unsigned domain           : 4;
+    unsigned zero             : 1;
+    unsigned should_be_zero   : 24;
+} ATTRIBUTE_PACKED fault_status_t;
+/** Help union used for casting integer value into #fault_status_t. */
+typedef union {
+    fault_status_t fs;
+    uint32_t dummy;
+} fault_status_union_t;
+/** Simplified description of instruction code.
+ *
+ * @note Used for recognizing memory access instructions.
+ * @see ARM architecture reference (chapter 3.1)
+ */
+typedef struct {
+    unsigned dummy1        : 4;
+    unsigned bit4          : 1;
+    unsigned bits567       : 3;
+    unsigned dummy         : 12;
+    unsigned access        : 1;
+    unsigned opcode        : 4;
+    unsigned type          : 3;
+    unsigned condition     : 4;
+} ATTRIBUTE_PACKED instruction_t;
+/** Help union used for casting pc register (uint_32_t) value into
+ *  #instruction_t pointer.
+ */
+typedef union {
+    instruction_t *instr;
+    uint32_t pc;
+} instruction_union_t;
+extern void prefetch_abort(int n, istate_t *istate);
+extern void data_abort(int n, istate_t *istate);
+#endif
+/** @}
+ */

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Ignore whitespace Rev 2417 → Rev 2721