| 101,6 → 101,7 |
|---|
| #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
| #define PTE_EXECUTABLE_ARCH(pte) 1 |
| |
| |
| #ifndef __ASM__ |
| |
| /** Level 0 page table entry. */ |
| 118,7 → 119,8 |
|---|
| unsigned coarse_table_addr : 22; |
| } __attribute__ ((packed)) pte_level0_t; |
| |
| /** Level 1 page table entry (small (4KB) pages used) */ |
| |
| /** Level 1 page table entry (small (4KB) pages used). */ |
| typedef struct { |
| /* 0b10 for small pages */ |
| unsigned descriptor_type : 2; |
| 136,30 → 138,29 |
|---|
| |
| /* Level 1 page tables access permissions */ |
| |
| /** User mode: no access, privileged mode: no access */ |
| /** User mode: no access, privileged mode: no access. */ |
| #define PTE_AP_USER_NO_KERNEL_NO 0 |
| /** User mode: no access, privileged mode: read/write */ |
| /** User mode: no access, privileged mode: read/write. */ |
| #define PTE_AP_USER_NO_KERNEL_RW 1 |
| /** User mode: read only, privileged mode: read/write */ |
| /** User mode: read only, privileged mode: read/write. */ |
| #define PTE_AP_USER_RO_KERNEL_RW 2 |
| /** User mode: read/write, privileged mode: read/write */ |
| /** User mode: read/write, privileged mode: read/write. */ |
| #define PTE_AP_USER_RW_KERNEL_RW 3 |
| |
| |
| /* pte_level0_t and pte_level1_t descriptor_type flags */ |
| |
| /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */ |
| /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
| #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
| /** pte_level0_t coarse page table flag (used in descriptor_type) */ |
| /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
| #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
| /** pte_level1_t small page table flag (used in descriptor type) */ |
| /** pte_level1_t small page table flag (used in descriptor type). */ |
| #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
| |
| |
| /** |
| * Sets the address of level 0 page table. |
| /** Sets the address of level 0 page table. |
| * |
| * \param pt pointer to the page table to set |
| * @param pt Pointer to the page table to set. |
| */ |
| static inline void set_ptl0_addr( pte_level0_t* pt) |
| { |
| 170,10 → 171,11 |
|---|
| ); |
| } |
| |
| |
| /** Returns level 0 page table entry flags. |
| * |
| * \param pt level 0 page table |
| * \param i index of the entry to return |
| * @param pt Level 0 page table. |
| * @param i Index of the entry to return. |
| */ |
| static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
| { |
| 189,10 → 191,11 |
|---|
| ; |
| } |
| |
| |
| /** Returns level 1 page table entry flags. |
| * |
| * \param pt level 1 page table |
| * \param i index of the entry to return |
| * @param pt Level 1 page table. |
| * @param i Index of the entry to return. |
| */ |
| static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
| { |
| 211,11 → 214,12 |
|---|
| ; |
| } |
| |
| |
| /** Sets flags of level 0 page table entry. |
| * |
| * \param pt level 0 page table |
| * \param i index of the entry to be changed |
| * \param flags new flags |
| * @param pt level 0 page table |
| * @param i index of the entry to be changed |
| * @param flags new flags |
| */ |
| static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
| { |
| 231,6 → 235,7 |
|---|
| } |
| } |
| |
| |
| /** Sets flags of level 1 page table entry. |
| * |
| * We use same access rights for the whole page. When page is not preset we |
| 237,9 → 242,9 |
|---|
| * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
| * page entry, see #PAGE_VALID_ARCH). |
| * |
| * \param pt level 1 page table |
| * \param i index of the entry to be changed |
| * \param flags new flags |
| * @param pt Level 1 page table. |
| * @param i Index of the entry to be changed. |
| * @param flags New flags. |
| */ |
| static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
| { |