/branches/arm/kernel/arch/arm32/include/exception.h |
---|
125,6 → 125,7 |
return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; |
} |
/** Returns Program Counter member of given istate structure. */ |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
/branches/arm/kernel/arch/arm32/include/boot.h |
---|
46,8 → 46,10 |
/** Struct holding information about single loaded uspace task. */ |
typedef struct { |
/** Address where the task was placed. */ |
uintptr_t addr; |
/** Size of the task's binary. */ |
uint32_t size; |
} utask_t; |
55,8 → 57,10 |
/** Struct holding information about loaded uspace tasks. */ |
typedef struct { |
/** Number of loaded tasks. */ |
uint32_t cnt; |
/** Array of loaded tasks. */ |
utask_t tasks[TASKMAP_MAX_RECORDS]; |
} bootinfo_t; |
/branches/arm/kernel/arch/arm32/include/atomic.h |
---|
72,6 → 72,7 |
*/ |
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } |
/** Atomic decrement. |
* |
* @param val Variable to be decremented. |
78,6 → 79,7 |
*/ |
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } |
/** Atomic pre-increment. |
* |
* @param val Variable to be incremented. |
85,6 → 87,7 |
*/ |
static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); } |
/** Atomic pre-decrement. |
* |
* @param val Variable to be decremented. |
92,6 → 95,7 |
*/ |
static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); } |
/** Atomic post-increment. |
* |
* @param val Variable to be incremented. |
99,6 → 103,7 |
*/ |
static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; } |
/** Atomic post-decrement. |
* |
* @param val Variable to be decremented. |
/branches/arm/kernel/arch/arm32/include/asm.h |
---|
47,7 → 47,7 |
} |
/** Return base address of current stack |
/** Return base address of current stack. |
* |
* Return the base address of the current stack. |
* The stack is assumed to be STACK_SIZE bytes long. |
/branches/arm/kernel/arch/arm32/include/mm/page.h |
---|
107,11 → 107,13 |
/** Level 0 page table entry. */ |
typedef struct { |
/* 01b for coarse tables, see below for details */ |
unsigned descriptor_type : 2; |
unsigned impl_specific : 3; |
unsigned domain : 4; |
unsigned should_be_zero : 1; |
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB) |
* or large (64KB) pages. ARM also supports fine 2nd level page tables that |
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
123,10 → 125,12 |
/** Level 1 page table entry (small (4KB) pages used). */ |
typedef struct { |
/* 0b10 for small pages */ |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
/* access permissions for each of 4 subparts of a page |
* (for each 1KB when small pages used */ |
unsigned access_permission_0 : 2; |
141,10 → 145,13 |
/** User mode: no access, privileged mode: no access. */ |
#define PTE_AP_USER_NO_KERNEL_NO 0 |
/** User mode: no access, privileged mode: read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
/** User mode: read only, privileged mode: read/write. */ |
#define PTE_AP_USER_RO_KERNEL_RW 2 |
/** User mode: read/write, privileged mode: read/write. */ |
#define PTE_AP_USER_RW_KERNEL_RW 3 |
153,8 → 160,10 |
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_NOT_PRESENT 0 |
/** pte_level0_t coarse page table flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_COARSE_TABLE 1 |
/** pte_level1_t small page table flag (used in descriptor type). */ |
#define PTE_DESCRIPTOR_SMALL_PAGE 2 |
/branches/arm/kernel/arch/arm32/include/cpu.h |
---|
42,14 → 42,19 |
/** Struct representing ARM CPU identifiaction. */ |
typedef struct { |
/** Implementator (vendor) number. */ |
uint32_t imp_num; |
/** Variant number. */ |
uint32_t variant_num; |
/** Architecture number. */ |
uint32_t arch_num; |
/** Primary part number. */ |
uint32_t prim_part_num; |
/** Revision number. */ |
uint32_t rev_num; |
} cpu_arch_t; |