/branches/arm/kernel/arch/arm32/include/machine_func.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mainpage.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mach/testarm/testarm.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mach/integratorcp/integratorcp.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/interrupt.h |
---|
37,7 → 37,6 |
#define KERN_arm32_INTERRUPT_H_ |
#include <arch/types.h> |
#include <arch/exception.h> |
/** Initial size of exception dispatch table. */ |
#define IVT_ITEMS 6 |
/branches/arm/kernel/arch/arm32/include/exception.h |
---|
40,7 → 40,7 |
#include <arch/types.h> |
#include <arch/regutils.h> |
/** If defined, forces using of high exception vectors. */ |
/** If defined, macro forces using of high exception vectors. */ |
#define HIGH_EXCEPTION_VECTORS |
#ifdef HIGH_EXCEPTION_VECTORS |
84,7 → 84,7 |
extern uintptr_t exc_stack; |
/** Struct representing CPU state saved when an exception occurs. */ |
/** Structure representing CPU state saved when an exception occurs. */ |
typedef struct { |
uint32_t spsr; |
uint32_t sp; |
125,7 → 125,6 |
return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; |
} |
/** Returns Program Counter member of given istate structure. */ |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
133,16 → 132,10 |
} |
extern void setup_exception_stacks(void); |
extern void install_exception_handlers(void); |
extern void exception_init(void); |
extern void print_istate(istate_t *istate); |
extern void reset_exception_entry(void); |
extern void irq_exception_entry(void); |
extern void fiq_exception_entry(void); |
extern void undef_instr_exception_entry(void); |
extern void prefetch_abort_exception_entry(void); |
extern void data_abort_exception_entry(void); |
extern void swi_exception_entry(void); |
#endif |
/branches/arm/kernel/arch/arm32/include/fpu_context.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* Copyright (c) 2005 Jakub Vana |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,9 → 30,7 |
* @{ |
*/ |
/** @file |
* @brief FPU context (not implemented). |
* |
* GXemul doesn't support FPU on its ARM CPU. |
* @brief FPU context. |
*/ |
#ifndef KERN_arm32_FPU_CONTEXT_H_ |
40,7 → 38,7 |
#include <arch/types.h> |
#define FPU_CONTEXT_ALIGN 0 |
#define FPU_CONTEXT_ALIGN 0 /* TODO */ |
typedef struct { |
} fpu_context_t; |
/branches/arm/kernel/arch/arm32/include/regutils.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** |
37,6 → 37,7 |
#ifndef KERN_arm32_REGUTILS_H_ |
#define KERN_arm32_REGUTILS_H_ |
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1f |
52,26 → 53,21 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
/* [CS]PRS manipulation macros */ |
#define GEN_STATUS_READ(nm,reg) \ |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm volatile( \ |
"mrs %[retval], " #reg \ |
: [retval] "=r" (retval) \ |
); \ |
return retval; \ |
} |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm volatile("mrs %0, " #reg : "=r"(retval)); \ |
return retval; \ |
} |
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm volatile( \ |
"msr " #reg "_" #field ", %[value]" \ |
:: [value] "r" (value) \ |
); \ |
} |
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
} |
/** Returns the value of CPSR (Current Program Status Register). */ |
/branches/arm/kernel/arch/arm32/include/types.h |
---|
36,11 → 36,9 |
#ifndef KERN_arm32_TYPES_H_ |
#define KERN_arm32_TYPES_H_ |
#ifndef DOXYGEN |
# define ATTRIBUTE_PACKED __attribute__ ((packed)) |
#else |
# define ATTRIBUTE_PACKED |
#endif |
#define NULL 0 |
#define false 0 |
#define true 1 |
typedef signed char int8_t; |
typedef signed short int16_t; |
53,6 → 51,8 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
62,30 → 62,14 |
typedef uint32_t unative_t; |
typedef int32_t native_t; |
typedef struct { |
} fncptr_t; |
typedef uint8_t bool; |
typedef uint64_t task_id_t; |
typedef uint32_t context_id_t; |
#define PRIp "x" /**< Format for uintptr_t. */ |
#define PRIs "u" /**< Format for size_t. */ |
typedef int32_t inr_t; |
typedef int32_t devno_t; |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
#define PRId32 "d" /**< Format for int32_t. */ |
#define PRId64 "lld" /**< Format for int64_t. */ |
#define PRIdn "d" /**< Format for native_t. */ |
#define PRIu8 "u" /**< Format for uint8_t. */ |
#define PRIu16 "u" /**< Format for uint16_t. */ |
#define PRIu32 "u" /**< Format for uint32_t. */ |
#define PRIu64 "llu" /**< Format for uint64_t. */ |
#define PRIun "u" /**< Format for unative_t. */ |
#define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */ |
#define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */ |
#define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */ |
#define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */ |
#define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ |
/** Page table entry. |
* |
* We have different structs for level 0 and level 1 page table entries. |
95,6 → 79,7 |
unsigned dummy : 32; |
} pte_t; |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/memstr.h |
---|
38,10 → 38,10 |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
extern void memsetw(void *dst, size_t cnt, uint16_t x); |
extern void memsetb(void *dst, size_t cnt, uint8_t x); |
extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); |
extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); |
extern int memcmp(const void *a, const void *b, size_t cnt); |
extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); |
#endif |
/branches/arm/kernel/arch/arm32/include/proc/thread.h |
---|
47,3 → 47,4 |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/frame.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
36,8 → 36,8 |
#ifndef KERN_arm32_FRAME_H_ |
#define KERN_arm32_FRAME_H_ |
#define FRAME_WIDTH 12 /* 4KB frames */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#define FRAME_WIDTH 12 /* 4KB frames */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
44,8 → 44,8 |
#include <arch/types.h> |
#define BOOT_PAGE_TABLE_SIZE 0x4000 |
#define BOOT_PAGE_TABLE_ADDRESS 0x4000 |
#define BOOT_PAGE_TABLE_SIZE 0x4000 |
#define BOOT_PAGE_TABLE_ADDRESS 0x4000 |
#define BOOT_PAGE_TABLE_START_FRAME (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH) |
#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH) |
54,7 → 54,6 |
extern void frame_arch_init(void); |
extern void boot_page_table_free(void); |
#define physmem_print() |
#endif /* __ASM__ */ |
#endif /* KERNEL */ |
/branches/arm/kernel/arch/arm32/include/mm/memory_init.h |
---|
0,0 → 1,46 |
/* |
* Copyright (c) 2007 Pavel Jancik |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
* @brief Memory information functions declarations. |
*/ |
#ifndef KERN_arm32_MEMORY_INIT_H_ |
#define KERN_arm32_MEMORY_INIT_H_ |
#include <config.h> |
size_t get_memory_size(void); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/page.h |
---|
40,9 → 40,12 |
#include <mm/mm.h> |
#include <arch/exception.h> |
#define PAGE_WIDTH FRAME_WIDTH |
#define PAGE_SIZE FRAME_SIZE |
#define PAGE_COLOR_BITS 0 /* dummy */ |
#ifndef __ASM__ |
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
53,102 → 56,77 |
#ifdef KERNEL |
/* Number of entries in each level. */ |
#define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
#define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
/* coarse page tables used (256 * 4 = 1KB per page) */ |
#define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
/* coarse page tables used (256*4 = 1KB per page) */ |
#define PTL3_ENTRIES_ARCH (2<<8) // 256 |
/* Page table sizes for each level. */ |
#define PTL0_SIZE_ARCH FOUR_FRAMES |
#define PTL1_SIZE_ARCH 0 |
#define PTL2_SIZE_ARCH 0 |
#define PTL3_SIZE_ARCH ONE_FRAME |
/* Macros calculating indices into page tables for each level. */ |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
/* Get PTE address accessors for each level. */ |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
(ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
(ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
/* Set PTE address accessors for each level. */ |
#define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
(set_ptl0_addr((pte_level0_t *) (ptl0))) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
(((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0))) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
(((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i)) |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
/* Macros for querying the last-level PTE entries. */ |
#define PTE_VALID_ARCH(pte) \ |
(*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) \ |
(((pte_level0_t *) (pte))->descriptor_type != 0) |
#define PTE_GET_FRAME_ARCH(pte) \ |
(((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
#define PTE_WRITABLE_ARCH(pte) \ |
(((pte_level1_t *) (pte))->access_permission_0 == \ |
PTE_AP_USER_RW_KERNEL_RW) |
#define PTE_EXECUTABLE_ARCH(pte) \ |
1 |
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
/* pte should point into ptl3 */ |
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
/* pte should point into ptl3 */ |
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
#define PTE_EXECUTABLE_ARCH(pte) 1 |
#ifndef __ASM__ |
/** Level 0 page table entry. */ |
typedef struct { |
/* 0b01 for coarse tables, see below for details */ |
unsigned descriptor_type : 2; |
unsigned impl_specific : 3; |
unsigned domain : 4; |
unsigned should_be_zero : 1; |
/* 01b for coarse tables, see below for details */ |
unsigned descriptor_type : 2; |
unsigned impl_specific : 3; |
unsigned domain : 4; |
unsigned should_be_zero : 1; |
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB) |
* or large (64KB) pages. ARM also supports fine 2nd level page tables that |
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
* with 1KB per the coarse table) |
*/ |
unsigned coarse_table_addr : 22; |
} __attribute__ ((packed)) pte_level0_t; |
/* Pointer to the coarse 2nd level page table (holding entries for small |
* (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
* tables that may hold even tiny pages (1KB) but they are bigger (4KB |
* per table in comparison with 1KB per the coarse table) |
*/ |
unsigned coarse_table_addr : 22; |
} ATTRIBUTE_PACKED pte_level0_t; |
/** Level 1 page table entry (small (4KB) pages used). */ |
typedef struct { |
/* 0b10 for small pages */ |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
/* access permissions for each of 4 subparts of a page |
* (for each 1KB when small pages used */ |
unsigned access_permission_0 : 2; |
155,35 → 133,30 |
unsigned access_permission_1 : 2; |
unsigned access_permission_2 : 2; |
unsigned access_permission_3 : 2; |
unsigned frame_base_addr : 20; |
} ATTRIBUTE_PACKED pte_level1_t; |
unsigned frame_base_addr : 20; |
} __attribute__ ((packed)) pte_level1_t; |
/* Level 1 page tables access permissions */ |
/** User mode: no access, privileged mode: no access. */ |
#define PTE_AP_USER_NO_KERNEL_NO 0 |
#define PTE_AP_USER_NO_KERNEL_NO 0 |
/** User mode: no access, privileged mode: read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
/** User mode: read only, privileged mode: read/write. */ |
#define PTE_AP_USER_RO_KERNEL_RW 2 |
#define PTE_AP_USER_RO_KERNEL_RW 2 |
/** User mode: read/write, privileged mode: read/write. */ |
#define PTE_AP_USER_RW_KERNEL_RW 3 |
#define PTE_AP_USER_RW_KERNEL_RW 3 |
/* pte_level0_t and pte_level1_t descriptor_type flags */ |
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_NOT_PRESENT 0 |
#define PTE_DESCRIPTOR_NOT_PRESENT 0 |
/** pte_level0_t coarse page table flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_COARSE_TABLE 1 |
#define PTE_DESCRIPTOR_COARSE_TABLE 1 |
/** pte_level1_t small page table flag (used in descriptor type). */ |
#define PTE_DESCRIPTOR_SMALL_PAGE 2 |
#define PTE_DESCRIPTOR_SMALL_PAGE 2 |
/** Sets the address of level 0 page table. |
190,11 → 163,12 |
* |
* @param pt Pointer to the page table to set. |
*/ |
static inline void set_ptl0_addr(pte_level0_t *pt) |
static inline void set_ptl0_addr( pte_level0_t* pt) |
{ |
asm volatile ( |
"mcr p15, 0, %[pt], c2, c0, 0\n" |
:: [pt] "r" (pt) |
"mcr p15, 0, %0, c2, c0, 0 \n" |
: |
: "r"(pt) |
); |
} |
204,37 → 178,41 |
* @param pt Level 0 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i) |
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
{ |
pte_level0_t *p = &pt[i]; |
int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
(1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
(1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
return |
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) | |
( 1 << PAGE_USER_SHIFT ) | |
( 1 << PAGE_READ_SHIFT ) | |
( 1 << PAGE_WRITE_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( 1 << PAGE_CACHEABLE_SHIFT ) |
; |
} |
/** Returns level 1 page table entry flags. |
* |
* @param pt Level 1 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i) |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
{ |
pte_level1_t *p = &pt[i]; |
int dt = p->descriptor_type; |
int ap = p->access_permission_0; |
return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
(1 << PAGE_EXEC_SHIFT) | |
(p->bufferable << PAGE_CACHEABLE); |
return |
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( p->bufferable << PAGE_CACHEABLE ) |
; |
} |
244,20 → 222,17 |
* @param i index of the entry to be changed |
* @param flags new flags |
*/ |
static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags) |
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
{ |
pte_level0_t *p = &pt[i]; |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
/* |
* Ensures that the entry will be recognized as valid when |
* PTE_VALID_ARCH applied. |
*/ |
p->should_be_zero = 1; |
// ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied |
p->should_be_zero = 1; |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
p->should_be_zero = 0; |
p->should_be_zero = 0; |
} |
} |
272,16 → 247,16 |
* @param i Index of the entry to be changed. |
* @param flags New flags. |
*/ |
static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags) |
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
{ |
pte_level1_t *p = &pt[i]; |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
p->access_permission_3 = 1; |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
p->access_permission_3 = 1; |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
p->access_permission_3 = p->access_permission_0; |
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
p->access_permission_3 = p->access_permission_0; |
} |
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
288,19 → 263,18 |
/* default access permission */ |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_NO_KERNEL_RW; |
p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; |
if (flags & PAGE_USER) { |
if (flags & PAGE_READ) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RO_KERNEL_RW; |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RO_KERNEL_RW; |
} |
if (flags & PAGE_WRITE) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RW_KERNEL_RW; |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RW_KERNEL_RW; |
} |
} |
} |
317,3 → 291,4 |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/asid.h |
---|
31,8 → 31,6 |
*/ |
/** @file |
* @brief ASIDs related declarations. |
* |
* ARM CPUs doesn't support ASIDs. |
*/ |
#ifndef KERN_arm32_ASID_H_ |
44,12 → 42,11 |
typedef uint8_t asid_t; |
/* |
* This works due to fact that this file is never included alone but only |
* through "generic/include/mm/asid.h" where ASID_START is defined. |
*/ |
#define asid_get() (ASID_START + 1) |
#define asid_get() ( ASID_START + 1 ) |
/* this works due to fact that this file is never included alone but only |
throught "generic/include/mm/asid.h" where ASID_START is defined |
*/ |
#define asid_put(asid) |
#endif |
/branches/arm/kernel/arch/arm32/include/mm/tlb.h |
---|
36,6 → 36,9 |
#ifndef KERN_arm32_TLB_H_ |
#define KERN_arm32_TLB_H_ |
#define tlb_arch_init() |
#define tlb_print() |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/mm/page_fault.h |
---|
1,89 → 1,91 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
* @brief Page fault related declarations. |
*/ |
#ifndef KERN_arm32_PAGE_FAULT_H_ |
#define KERN_arm32_PAGE_FAULT_H_ |
#include <arch/types.h> |
/** Decribes CP15 "fault status register" (FSR). */ |
typedef struct { |
unsigned status : 3; |
unsigned domain : 4; |
unsigned zero : 1; |
unsigned should_be_zero : 24; |
} ATTRIBUTE_PACKED fault_status_t; |
/** Help union used for casting integer value into #fault_status_t. */ |
typedef union { |
fault_status_t fs; |
uint32_t dummy; |
} fault_status_union_t; |
/** Simplified description of instruction code. |
* |
* @note Used for recognizing memory access instructions. |
* @see ARM architecture reference (chapter 3.1) |
*/ |
typedef struct { |
unsigned dummy1 : 4; |
unsigned bit4 : 1; |
unsigned bits567 : 3; |
unsigned dummy : 12; |
unsigned access : 1; |
unsigned opcode : 4; |
unsigned type : 3; |
unsigned condition : 4; |
} ATTRIBUTE_PACKED instruction_t; |
/** Help union used for casting pc register (uint_32_t) value into |
* #instruction_t pointer. |
*/ |
typedef union { |
instruction_t *instr; |
uint32_t pc; |
} instruction_union_t; |
extern void prefetch_abort(int n, istate_t *istate); |
extern void data_abort(int n, istate_t *istate); |
#endif |
/** @} |
*/ |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
* @brief Page fault related declarations. |
*/ |
#ifndef KERN_arm32_PAGE_FAULT_H_ |
#define KERN_arm32_PAGE_FAULT_H |
#include <arch/types.h> |
/** Decribes CP15 "fault status register" (FSR). */ |
typedef struct { |
unsigned status : 3; |
unsigned domain : 4; |
unsigned zero : 1; |
unsigned should_be_zero : 24; |
} __attribute__ ((packed)) fault_status_t; |
/** Help union used for casting integer value into #fault_status_t. */ |
typedef union { |
fault_status_t fs; |
uint32_t dummy; |
} fault_status_union_t; |
/** Simplified description of instruction code. |
* |
* @note Used for recognizing memory access instructions. |
* @see ARM architecture reference (chapter 3.1) |
*/ |
typedef struct { |
unsigned dummy1 : 4; |
unsigned bit4 : 1; |
unsigned bits567 : 3; |
unsigned dummy : 12; |
unsigned access : 1; |
unsigned opcode : 4; |
unsigned type : 3; |
unsigned condition : 4; |
} __attribute__ ((packed)) instruction_t; |
/** Help union used for casting pc register (uint_32_t) value into |
* #instruction_t pointer. |
*/ |
typedef union { |
instruction_t* instr; |
uint32_t pc; |
} instruction_union_t; |
extern void prefetch_abort(int n, istate_t *istate); |
extern void data_abort(int n, istate_t *istate); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/drivers/gxemul.h |
---|
0,0 → 1,80 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief GXemul peripheries drivers declarations. |
*/ |
#ifndef KERN_arm32_GXEMUL_H_ |
#define KERN_arm32_GXEMUL_H_ |
#include <console/chardev.h> |
/** Last interrupt number (beginning from 0) whose status is probed |
* from interrupt controller |
*/ |
#define GXEMUL_IRQC_MAX_IRQ 8 |
/** Timer frequency */ |
#define GXEMUL_TIMER_FREQ 100 |
/** Struct containing mappings of gxemul HW devices into kernel part |
* of virtual address space. |
*/ |
typedef struct { |
uintptr_t videoram; |
uintptr_t kbd; |
uintptr_t rtc; |
uintptr_t rtc_freq; |
uintptr_t rtc_ack; |
uintptr_t irqc; |
uintptr_t irqc_mask; |
uintptr_t irqc_unmask; |
} gxemul_hw_map_t; |
extern void gxemul_hw_map_init(void); |
extern void gxemul_console_init(devno_t devno); |
extern void gxemul_release_console(void); |
extern void gxemul_grab_console(void); |
extern void gxemul_timer_irq_start(void); |
extern void gxemul_debug_putc(char ch); |
extern void gxemul_cpu_halt(void); |
extern void gxemul_irq_exception(int exc_no, istate_t *istate); |
extern size_t gxemul_get_memory_size(void); |
extern uintptr_t gxemul_get_fb_address(void); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/machine.h |
---|
0,0 → 1,109 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Declarations of machine specific functions. |
*/ |
#ifndef KERN_arm32_MACHINE_H_ |
#define KERN_arm32_MACHINE_H_ |
#include <console/console.h> |
#include <arch/types.h> |
#include <arch/exception.h> |
#include <arch/drivers/gxemul.h> |
/** Initializes console. |
* |
* @param devno Console device number. |
*/ |
extern void machine_console_init(devno_t devno); |
/** Acquire console back for kernel. */ |
extern void machine_grab_console(void); |
/** Return console to userspace. */ |
extern void machine_release_console(void); |
/** Maps HW devices to the kernel address space using #hw_map. */ |
extern void machine_hw_map_init(void); |
/** Starts timer. */ |
extern void machine_timer_irq_start(void); |
/** Halts CPU. */ |
extern void machine_cpu_halt(void); |
/** Returns size of available memory. |
* |
* @return Size of available memory. |
*/ |
extern size_t machine_get_memory_size(void); |
/** Prints a character. |
* |
* @param ch Character to be printed. |
*/ |
extern void machine_debug_putc(char ch); |
/** Interrupt exception handler. |
* |
* @param exc_no Interrupt exception number. |
* @param istate Saved processor state. |
*/ |
extern void machine_irq_exception(int exc_no, istate_t *istate); |
extern uintptr_t machine_get_fb_address(void); |
#ifdef MACHINE_GXEMUL_TESTARM |
# define machine_console_init(devno) gxemul_console_init(devno) |
# define machine_grab_console gxemul_grab_console |
# define machine_release_console gxemul_release_console |
# define machine_hw_map_init gxemul_hw_map_init |
# define machine_timer_irq_start gxemul_timer_irq_start |
# define machine_cpu_halt gxemul_cpu_halt |
# define machine_get_memory_size gxemul_get_memory_size |
# define machine_debug_putc(ch) gxemul_debug_putc(ch) |
# define machine_irq_exception(exc_no, istate) gxemul_irq_exception(exc_no, istate) |
# define machine_get_fb_address gxemul_get_fb_address |
#endif |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/asm/boot.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
36,10 → 36,28 |
#ifndef KERN_arm32_ASM_BOOT_H_ |
#define KERN_arm32_ASM_BOOT_H_ |
/** Size of a temporary stack used for initial kernel start. */ |
#define TEMP_STACK_SIZE 0x100 |
#define TEMP_STACK_SIZE 0x100 |
#ifndef __ASM__ |
/** Kernel entry point. |
* |
* Implemented in assembly. Copies boot_bootinfo (declared as bootinfo in |
* boot/arch/arm32/loader/main.c) to #bootinfo struct. Then jumps to |
* #arch_pre_main and #main_bsp. |
* |
* @param entry Entry point address (not used). |
* @param boot_bootinfo Struct holding information about loaded tasks. |
* @param bootinfo_size Size of the bootinfo structure. |
*/ |
void kernel_image_start(void *entry, void *boot_bootinfo, unsigned int bootinfo_size); |
#endif |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/byteorder.h |
---|
0,0 → 1,62 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Endianness definitions. |
*/ |
#ifndef KERN_arm32_BYTEORDER_H_ |
#define KERN_arm32_BYTEORDER_H_ |
#include <byteorder.h> |
#ifdef BIG_ENDIAN |
#define uint32_t_le2host(n) uint32_t_byteorder_swap(n) |
#define uint64_t_le2host(n) uint64_t_byteorder_swap(n) |
#define uint32_t_be2host(n) (n) |
#define uint64_t_be2host(n) (n) |
#else |
#define uint32_t_le2host(n) (n) |
#define uint64_t_le2host(n) (n) |
#define uint32_t_be2host(n) uint32_t_byteorder_swap(n) |
#define uint64_t_be2host(n) uint64_t_byteorder_swap(n) |
#endif |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/debug/print.h |
---|
0,0 → 1,57 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Debug printing functions. |
*/ |
#ifndef KERN_arm32_DEBUG_PRINT_H_ |
#define KERN_arm32_DEBUG_PRINT_H_ |
#include <stdarg.h> |
#include <arch/types.h> |
extern void debug_puts(const char *str); |
extern void debug_printf(const char *fmt, ...); |
#ifdef CONFIG_DEBUG |
# define dprintf(arg1...) debug_printf(arg1) |
# define dputs(arg1) debug_puts(arg1) |
#else |
# define dprintf(arg1...) |
# define dputs(arg1) |
#endif |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/console.h |
---|
0,0 → 1,49 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Console. |
*/ |
#ifndef KERN_arm32_CONSOLE_H_ |
#define KERN_arm32_CONSOLE_H_ |
/** Initializes console. |
* |
* @param devno Console device number. |
*/ |
extern void console_init(devno_t devno); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/boot.h |
---|
0,0 → 1,72 |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Bootinfo declarations. |
* |
* Reflects boot/arch/arm32/loader/main.h. |
*/ |
#ifndef KERN_arm32_BOOT_H_ |
#define KERN_arm32_BOOT_H_ |
#include <arch/types.h> |
/** Maximum number of tasks in the #bootinfo_t struct. */ |
#define TASKMAP_MAX_RECORDS 32 |
/** Struct holding information about single loaded uspace task. */ |
typedef struct { |
/** Address where the task was placed. */ |
uintptr_t addr; |
/** Size of the task's binary. */ |
uint32_t size; |
} utask_t; |
/** Struct holding information about loaded uspace tasks. */ |
typedef struct { |
/** Number of loaded tasks. */ |
uint32_t cnt; |
/** Array of loaded tasks. */ |
utask_t tasks[TASKMAP_MAX_RECORDS]; |
} bootinfo_t; |
/** Bootinfo that is filled in #kernel_image_start. */ |
extern bootinfo_t bootinfo; |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/faddr.h |
---|
40,7 → 40,7 |
/** Calculate absolute address of function referenced by fptr pointer. |
* |
* @param fptr Function pointer. |
* @param f Function pointer. |
*/ |
#define FADDR(fptr) ((uintptr_t) (fptr)) |
/branches/arm/kernel/arch/arm32/include/context.h |
---|
46,9 → 46,7 |
#include <arch/types.h> |
/** Thread context containing registers that must be preserved across function |
* calls. |
*/ |
/** Thread context containing registers that must be preserved across function calls. */ |
typedef struct { |
uint32_t cpu_mode; |
uintptr_t sp; |
/branches/arm/kernel/arch/arm32/include/cycle.h |
---|
36,17 → 36,14 |
#ifndef KERN_arm32_CYCLE_H_ |
#define KERN_arm32_CYCLE_H_ |
/** Returns count of CPU cycles. |
* |
* No such instruction on ARM to get count of cycles. |
* |
* @return Count of CPU cycles. |
*/ |
/** No such instruction on ARM to get count of cycles. */ |
static inline uint64_t get_cycle(void) |
{ |
return 0; |
} |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/stack.h |
---|
38,9 → 38,7 |
#define STACK_ITEM_SIZE 4 |
/** See <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for |
* details |
*/ |
/** see <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for details */ |
#define STACK_ALIGNMENT 8 |
#endif |
/branches/arm/kernel/arch/arm32/include/atomic.h |
---|
26,10 → 26,10 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
/** @file |
* @brief Atomic operations. |
*/ |
42,45 → 42,41 |
* @param i Value to be added. |
* |
* @return Value after addition. |
* |
*/ |
static inline long atomic_add(atomic_t *val, int i) |
{ |
int ret; |
volatile long *mem = &(val->count); |
volatile long * mem = &(val->count); |
asm volatile ( |
"1:\n" |
"ldr r2, [%[mem]]\n" |
"add r3, r2, %[i]\n" |
"str r3, %[ret]\n" |
"swp r3, r3, [%[mem]]\n" |
"cmp r3, r2\n" |
"bne 1b\n" |
: [ret] "=m" (ret) |
: [mem] "r" (mem), [i] "r" (i) |
"1: \n" |
"ldr r2, [%1] \n" |
"add r3, r2, %2 \n" |
"str r3, %0 \n" |
"swp r3, r3, [%1] \n" |
"cmp r3, r2 \n" |
"bne 1b \n" |
: "=m" (ret) |
: "r" (mem), "r" (i) |
: "r3", "r2" |
); |
return ret; |
} |
/** Atomic increment. |
* |
* @param val Variable to be incremented. |
*/ |
static inline void atomic_inc(atomic_t *val) |
{ |
atomic_add(val, 1); |
} |
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } |
/** Atomic decrement. |
* |
* @param val Variable to be decremented. |
*/ |
static inline void atomic_dec(atomic_t *val) { |
atomic_add(val, -1); |
} |
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } |
/** Atomic pre-increment. |
* |
87,10 → 83,7 |
* @param val Variable to be incremented. |
* @return Value after incrementation. |
*/ |
static inline long atomic_preinc(atomic_t *val) |
{ |
return atomic_add(val, 1); |
} |
static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); } |
/** Atomic pre-decrement. |
* |
97,10 → 90,7 |
* @param val Variable to be decremented. |
* @return Value after decrementation. |
*/ |
static inline long atomic_predec(atomic_t *val) |
{ |
return atomic_add(val, -1); |
} |
static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); } |
/** Atomic post-increment. |
* |
107,10 → 97,7 |
* @param val Variable to be incremented. |
* @return Value before incrementation. |
*/ |
static inline long atomic_postinc(atomic_t *val) |
{ |
return atomic_add(val, 1) - 1; |
} |
static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; } |
/** Atomic post-decrement. |
* |
117,11 → 104,9 |
* @param val Variable to be decremented. |
* @return Value before decrementation. |
*/ |
static inline long atomic_postdec(atomic_t *val) |
{ |
return atomic_add(val, -1) + 1; |
} |
static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; } |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/arch.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
36,26 → 36,6 |
#ifndef KERN_arm32_ARCH_H_ |
#define KERN_arm32_ARCH_H_ |
#define TASKMAP_MAX_RECORDS 32 |
#define CPUMAP_MAX_RECORDS 32 |
#define BOOTINFO_TASK_NAME_BUFLEN 32 |
#include <typedefs.h> |
typedef struct { |
uintptr_t addr; |
uint32_t size; |
char name[BOOTINFO_TASK_NAME_BUFLEN]; |
} utask_t; |
typedef struct { |
uint32_t cnt; |
utask_t tasks[TASKMAP_MAX_RECORDS]; |
} bootinfo_t; |
extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/asm.h |
---|
26,10 → 26,10 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
/** @file |
* @brief Declarations of functions implemented in assembly. |
*/ |
36,7 → 36,6 |
#ifndef KERN_arm32_ASM_H_ |
#define KERN_arm32_ASM_H_ |
#include <typedefs.h> |
#include <arch/types.h> |
#include <arch/stack.h> |
#include <config.h> |
47,59 → 46,30 |
{ |
} |
static inline void pio_write_8(ioport8_t *port, uint8_t v) |
{ |
*port = v; |
} |
static inline void pio_write_16(ioport16_t *port, uint16_t v) |
{ |
*port = v; |
} |
static inline void pio_write_32(ioport32_t *port, uint32_t v) |
{ |
*port = v; |
} |
static inline uint8_t pio_read_8(ioport8_t *port) |
{ |
return *port; |
} |
static inline uint16_t pio_read_16(ioport16_t *port) |
{ |
return *port; |
} |
static inline uint32_t pio_read_32(ioport32_t *port) |
{ |
return *port; |
} |
/** Return base address of current stack. |
* |
/** Return base address of current stack |
* |
* Return the base address of the current stack. |
* The stack is assumed to be STACK_SIZE bytes long. |
* The stack must start on page boundary. |
* |
*/ |
static inline uintptr_t get_stack_base(void) |
{ |
uintptr_t v; |
asm volatile ( |
"and %[v], sp, %[size]\n" |
: [v] "=r" (v) |
: [size] "r" (~(STACK_SIZE - 1)) |
"and %0, sp, %1\n" |
: "=r" (v) |
: "r" (~(STACK_SIZE-1)) |
); |
return v; |
} |
extern void cpu_halt(void); |
extern void asm_delay_loop(uint32_t t); |
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
uintptr_t entry); |
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, uintptr_t entry); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/barrier.h |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
39,16 → 39,13 |
/* |
* TODO: implement true ARM memory barriers for macros below. |
*/ |
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
#define memory_barrier() asm volatile ("" ::: "memory") |
#define read_barrier() asm volatile ("" ::: "memory") |
#define write_barrier() asm volatile ("" ::: "memory") |
#define memory_barrier() asm volatile ("" ::: "memory") |
#define read_barrier() asm volatile ("" ::: "memory") |
#define write_barrier() asm volatile ("" ::: "memory") |
#define smc_coherence(a) |
#define smc_coherence_block(a, l) |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/cpu.h |
---|
43,21 → 43,18 |
/** Struct representing ARM CPU identifiaction. */ |
typedef struct { |
/** Implementator (vendor) number. */ |
uint32_t imp_num; |
uint32_t imp_num; |
/** Variant number. */ |
uint32_t variant_num; |
uint32_t variant_num; |
/** Architecture number. */ |
uint32_t arch_num; |
uint32_t arch_num; |
/** Primary part number. */ |
uint32_t prim_part_num; |
uint32_t prim_part_num; |
/** Revision number. */ |
uint32_t rev_num; |
uint32_t rev_num; |
} cpu_arch_t; |
#endif |
/** @} |