/branches/arm/kernel/arch/arm32/include/machine_func.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mainpage.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mach/testarm/testarm.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mach/integratorcp/integratorcp.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/interrupt.h |
---|
27,32 → 27,20 |
*/ |
/** @addtogroup arm32interrupt |
* @ingroup interrupt |
* @{ |
*/ |
/** @file |
* @brief Declarations of interrupt controlling routines. |
*/ |
#ifndef KERN_arm32_INTERRUPT_H_ |
#define KERN_arm32_INTERRUPT_H_ |
#include <arch/types.h> |
#include <arch/exception.h> |
/** Initial size of exception dispatch table. */ |
#define IVT_ITEMS 6 |
/** Index of the first item in exception dispatch table. */ |
#define IVT_FIRST 0 |
void interrupt_init(void); |
extern void interrupt_init(void); |
extern ipl_t interrupts_disable(void); |
extern ipl_t interrupts_enable(void); |
extern void interrupts_restore(ipl_t ipl); |
extern ipl_t interrupts_read(void); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/exception.h |
---|
1,5 → 1,6 |
/* |
* Copyright (c) 2007 Michal Kebrt, Petr Stepan |
* Copyright (c) 2007 Michal Kebrt |
* Copyright (c) 2007 Petr Stepan |
* |
* All rights reserved. |
* |
31,7 → 32,6 |
* @{ |
*/ |
/** @file |
* @brief Exception declarations. |
*/ |
#ifndef KERN_arm32_EXCEPTION_H_ |
38,58 → 38,28 |
#define KERN_arm32_EXCEPTION_H_ |
#include <arch/types.h> |
#include <arch/regutils.h> |
/** If defined, forces using of high exception vectors. */ |
#define HIGH_EXCEPTION_VECTORS |
#ifdef HIGH_EXCEPTION_VECTORS |
#define EXC_BASE_ADDRESS 0xffff0000 |
#else |
#define EXC_BASE_ADDRESS 0x0 |
#endif |
/* Exception Vectors */ |
#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) |
#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) |
#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) |
#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) |
#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) |
#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) |
#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) |
#define EXC_RESET_VEC 0x0 |
#define EXC_UNDEF_INSTR_VEC 0x4 |
#define EXC_SWI_VEC 0x8 |
#define EXC_PREFETCH_ABORT_VEC 0xc |
#define EXC_DATA_ABORT_VEC 0x10 |
#define EXC_IRQ_VEC 0x18 |
#define EXC_FIQ_VEC 0x1c |
/* Exception numbers */ |
#define EXC_RESET 0 |
#define EXC_UNDEF_INSTR 1 |
#define EXC_SWI 2 |
#define EXC_PREFETCH_ABORT 3 |
#define EXC_DATA_ABORT 4 |
#define EXC_IRQ 5 |
#define EXC_FIQ 6 |
#define EXC_RESET 0 |
#define EXC_UNDEF_INSTR 1 |
#define EXC_SWI 2 |
#define EXC_PREFETCH_ABORT 3 |
#define EXC_DATA_ABORT 4 |
#define EXC_IRQ 5 |
#define EXC_FIQ 6 |
/** Kernel stack pointer. |
* |
* It is set when thread switches to user mode, |
* and then used for exception handling. |
*/ |
extern uintptr_t supervisor_sp; |
/** Temporary exception stack pointer. |
* |
* Temporary stack is used in exceptions handling routines |
* before switching to thread's kernel stack. |
*/ |
extern uintptr_t exc_stack; |
/** Struct representing CPU state saved when an exception occurs. */ |
typedef struct { |
uint32_t spsr; |
uint32_t sp; |
uint32_t lr; |
uint32_t r0; |
uint32_t r1; |
uint32_t r2; |
99,52 → 69,35 |
uint32_t r6; |
uint32_t r7; |
uint32_t r8; |
uint32_t r9; |
uint32_t r10; |
uint32_t r11; |
uint32_t r12; |
uint32_t sp; |
uint32_t lr; |
uint32_t pc; |
uint32_t spsr; |
} istate_t; |
/** Sets Program Counter member of given istate structure. |
* |
* @param istate istate structure |
* @param retaddr new value of istate's PC member |
*/ |
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
{ |
istate->pc = retaddr; |
istate->lr = retaddr; |
} |
/** Returns true if exception happened while in userspace. */ |
/** Return true if exception happened while in userspace */ |
static inline int istate_from_uspace(istate_t *istate) |
{ |
return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; |
return !(istate->lr & 0x80000000); |
return 0; |
} |
/** Returns Program Counter member of given istate structure. */ |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
return istate->pc; |
return istate->lr; |
} |
extern void setup_exception_stacks(void); |
extern void install_exception_handlers(void); |
extern void exception_init(void); |
extern void print_istate(istate_t *istate); |
extern void reset_exception_entry(void); |
extern void irq_exception_entry(void); |
extern void fiq_exception_entry(void); |
extern void undef_instr_exception_entry(void); |
extern void prefetch_abort_exception_entry(void); |
extern void data_abort_exception_entry(void); |
extern void swi_exception_entry(void); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/drivers/gxemul.h |
---|
0,0 → 1,47 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_MSIM_GXEMUL_H_ |
#define KERN_arm32_MSIM_GXEMUL_H_ |
#include <console/chardev.h> |
void gxemul_console(devno_t devno); |
void gxemul_kbd_release(void); |
void gxemul_kbd_grab(void); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/page_fault.h |
---|
File deleted |
/branches/arm/kernel/arch/arm32/include/mm/page.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* Copyright (c) 2003-2007 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Paging related declarations. |
*/ |
#ifndef KERN_arm32_PAGE_H_ |
40,9 → 39,12 |
#include <mm/mm.h> |
#include <arch/exception.h> |
#define PAGE_WIDTH FRAME_WIDTH |
#define PAGE_SIZE FRAME_SIZE |
#define PAGE_COLOR_BITS 0 /* dummy */ |
#ifndef __ASM__ |
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
52,263 → 54,136 |
#endif |
#ifdef KERNEL |
// Using small pages <==> 4kb |
#define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
#define PTL3_ENTRIES_ARCH (2<<8) // 256 |
/* Number of entries in each level. */ |
#define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
#define PTL1_ENTRIES_ARCH 0 |
#define PTL2_ENTRIES_ARCH 0 |
/* coarse page tables used (256 * 4 = 1KB per page) */ |
#define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
/* Page table sizes for each level. */ |
#define PTL0_SIZE_ARCH FOUR_FRAMES |
#define PTL1_SIZE_ARCH 0 |
#define PTL2_SIZE_ARCH 0 |
#define PTL3_SIZE_ARCH ONE_FRAME |
/* Macros calculating indices into page tables for each level. */ |
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
#define PTL1_INDEX_ARCH(vaddr) 0 |
#define PTL2_INDEX_ARCH(vaddr) 0 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
/* Get PTE address accessors for each level. */ |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
(ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
(ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
/* Set PTE address accessors for each level. */ |
#define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
(set_ptl0_addr((pte_level0_t *) (ptl0))) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
(((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
#define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_t *)(ptl0)) ) |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
(((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
/* Get PTE flags accessors for each level. */ |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i)) |
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
/* Set PTE flags accessors for each level. */ |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x)) |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
/* Macros for querying the last-level PTE entries. */ |
#define PTE_VALID_ARCH(pte) \ |
(*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) \ |
(((pte_level0_t *) (pte))->descriptor_type != 0) |
#define PTE_GET_FRAME_ARCH(pte) \ |
(((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
#define PTE_WRITABLE_ARCH(pte) \ |
(((pte_level1_t *) (pte))->access_permission_0 == \ |
PTE_AP_USER_RW_KERNEL_RW) |
#define PTE_EXECUTABLE_ARCH(pte) \ |
1 |
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3 |
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3 |
#define PTE_EXECUTABLE_ARCH(pte) 1 |
#ifndef __ASM__ |
/** Level 0 page table entry. */ |
typedef struct { |
/* 0b01 for coarse tables, see below for details */ |
unsigned descriptor_type : 2; |
unsigned impl_specific : 3; |
unsigned domain : 4; |
unsigned should_be_zero : 1; |
/* Pointer to the coarse 2nd level page table (holding entries for small |
* (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
* tables that may hold even tiny pages (1KB) but they are bigger (4KB |
* per table in comparison with 1KB per the coarse table) |
*/ |
unsigned coarse_table_addr : 22; |
} ATTRIBUTE_PACKED pte_level0_t; |
/** Level 1 page table entry (small (4KB) pages used). */ |
typedef struct { |
/* 0b10 for small pages */ |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
/* access permissions for each of 4 subparts of a page |
* (for each 1KB when small pages used */ |
unsigned access_permission_0 : 2; |
unsigned access_permission_1 : 2; |
unsigned access_permission_2 : 2; |
unsigned access_permission_3 : 2; |
unsigned frame_base_addr : 20; |
} ATTRIBUTE_PACKED pte_level1_t; |
/* Level 1 page tables access permissions */ |
/** User mode: no access, privileged mode: no access. */ |
#define PTE_AP_USER_NO_KERNEL_NO 0 |
/** User mode: no access, privileged mode: read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
/** User mode: read only, privileged mode: read/write. */ |
#define PTE_AP_USER_RO_KERNEL_RW 2 |
/** User mode: read/write, privileged mode: read/write. */ |
#define PTE_AP_USER_RW_KERNEL_RW 3 |
/* pte_level0_t and pte_level1_t descriptor_type flags */ |
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_NOT_PRESENT 0 |
/** pte_level0_t coarse page table flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_COARSE_TABLE 1 |
/** pte_level1_t small page table flag (used in descriptor type). */ |
#define PTE_DESCRIPTOR_SMALL_PAGE 2 |
/** Sets the address of level 0 page table. |
* |
* @param pt Pointer to the page table to set. |
/** Set adress of paging level 0 table |
* \param pt pointer to page table to set |
*/ |
static inline void set_ptl0_addr(pte_level0_t *pt) |
{ |
asm volatile ( |
"mcr p15, 0, %[pt], c2, c0, 0\n" |
:: [pt] "r" (pt) |
); |
static inline void set_ptl0_addr( pte_level0_t* pt){ |
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
: |
: "r"(pt) |
); |
} |
/** Returns level 0 page table entry flags. |
* |
* @param pt Level 0 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i) |
//TODO Comment: Page table structure as in other architectures |
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
{ |
pte_level0_t *p = &pt[i]; |
int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
pte_level0_t *p = &pt[i]; |
return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
(1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
(1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
return ( |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( 1 << PAGE_READ_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( 1 << PAGE_CACHEABLE ) |
); |
} |
/** Returns level 1 page table entry flags. |
* |
* @param pt Level 1 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i) |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
{ |
pte_level1_t *p = &pt[i]; |
pte_level1_t *p = &pt[i]; |
int dt = p->descriptor_type; |
int ap = p->access_permission_0; |
return ( |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( p->bufferable << PAGE_CACHEABLE ) |
); |
return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
(1 << PAGE_EXEC_SHIFT) | |
(p->bufferable << PAGE_CACHEABLE); |
} |
/** Sets flags of level 0 page table entry. |
* |
* @param pt level 0 page table |
* @param i index of the entry to be changed |
* @param flags new flags |
*/ |
static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags) |
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
{ |
pte_level0_t *p = &pt[i]; |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
/* |
* Ensures that the entry will be recognized as valid when |
* PTE_VALID_ARCH applied. |
*/ |
p->should_be_zero = 1; |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
p->should_be_zero = 0; |
if ( flags & PAGE_NOT_PRESENT ) { |
p->descriptor_type = pte_descriptor_not_preset; |
p->should_be_zero = 1; |
} else |
{ |
p->descriptor_type = pte_descriptor_coarse_table; |
p->should_be_zero = 0; |
} |
return; |
} |
/** Sets flags of level 1 page table entry. |
* |
* We use same access rights for the whole page. When page is not preset we |
* store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
* page entry, see #PAGE_VALID_ARCH). |
* |
* @param pt Level 1 page table. |
* @param i Index of the entry to be changed. |
* @param flags New flags. |
/* We use same acess rights for whole page, so if page is set as not preset then |
* in acess_rigts_3 set value 1 |
*/ |
static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags) |
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
{ |
pte_level1_t *p = &pt[i]; |
if (flags & PAGE_NOT_PRESENT) { |
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
p->access_permission_3 = 1; |
} else { |
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
p->access_permission_3 = p->access_permission_0; |
} |
if ( flags & PAGE_NOT_PRESENT ) { |
p->descriptor_type = pte_descriptor_not_preset; |
p->access_permission_3 = 1; |
} else |
{ |
p->descriptor_type = pte_descriptor_coarse_table; |
p->access_permission_3 = p->access_permission_0; |
} |
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
/* default access permission */ |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_NO_KERNEL_RW; |
if (flags & PAGE_USER) { |
if (flags & PAGE_READ) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RO_KERNEL_RW; |
} |
if (flags & PAGE_WRITE) { |
p->access_permission_0 = p->access_permission_1 = |
p->access_permission_2 = p->access_permission_3 = |
PTE_AP_USER_RW_KERNEL_RW; |
} |
} |
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
// default kernel rw, user none |
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw; |
if ( flags & PAGE_USER ) { |
if ( flags & PAGE_READ ) |
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw; |
if ( flags & PAGE_WRITE ) |
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw; |
} |
return; return; |
} |
extern void page_arch_init(void); |
#endif /* __ASM__ */ |
#endif /* KERNEL */ |
317,3 → 192,4 |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/memory_init.h |
---|
0,0 → 1,45 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_MEMORY_INIT_H_ |
#define KERN_arm32_MEMORY_INIT_H_ |
#include <config.h> |
size_t get_memory_size(void); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/mm/frame.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
26,35 → 26,22 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32mm |
/** @addtogroup arm32mm |
* @{ |
*/ |
/** @file |
* @brief Frame related declarations. |
*/ |
#ifndef KERN_arm32_FRAME_H_ |
#define KERN_arm32_FRAME_H_ |
#define FRAME_WIDTH 12 /* 4KB frames */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#define FRAME_WIDTH 12 /* 4KB frames */ |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
#include <arch/types.h> |
#define BOOT_PAGE_TABLE_SIZE 0x4000 |
#define BOOT_PAGE_TABLE_ADDRESS 0x4000 |
#define BOOT_PAGE_TABLE_START_FRAME (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH) |
#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH) |
extern uintptr_t last_frame; |
extern void frame_arch_init(void); |
extern void boot_page_table_free(void); |
#define physmem_print() |
#endif /* __ASM__ */ |
#endif /* KERNEL */ |
/branches/arm/kernel/arch/arm32/include/mm/asid.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* Copyright (c) 2005 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,9 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief ASIDs related declarations. |
* |
* ARM CPUs doesn't support ASIDs. |
*/ |
#ifndef KERN_arm32_ASID_H_ |
44,12 → 41,11 |
typedef uint8_t asid_t; |
/* |
* This works due to fact that this file is never included alone but only |
* through "generic/include/mm/asid.h" where ASID_START is defined. |
*/ |
#define asid_get() (ASID_START + 1) |
#define asid_get() ( ASID_START + 1 ) |
/* this works due to that this file is never included alone but only throught |
"generic/include/mm/asid.h" where ASID_START is defined |
*/ |
#define asid_put(asid) |
#endif |
/branches/arm/kernel/arch/arm32/include/mm/as.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Address space manipulating functions declarations. |
*/ |
#ifndef KERN_arm32_AS_H_ |
38,10 → 37,10 |
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 |
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 |
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff |
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 |
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff |
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 |
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff |
#define USTACK_ADDRESS_ARCH (0x80000000 - PAGE_SIZE) |
/branches/arm/kernel/arch/arm32/include/mm/tlb.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,12 → 30,14 |
* @{ |
*/ |
/** @file |
* @brief TLB related declarations. |
*/ |
#ifndef KERN_arm32_TLB_H_ |
#define KERN_arm32_TLB_H_ |
#define tlb_arch_init() |
#define tlb_print() |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/stack.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Stack constants. |
*/ |
#ifndef KERN_arm32_STACK_H_ |
38,9 → 37,7 |
#define STACK_ITEM_SIZE 4 |
/** See <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for |
* details |
*/ |
/** see <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for details */ |
#define STACK_ALIGNMENT 8 |
#endif |
/branches/arm/kernel/arch/arm32/include/atomic.h |
---|
26,102 → 26,53 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Atomic operations. |
*/ |
#ifndef KERN_arm32_ATOMIC_H_ |
#define KERN_arm32_ATOMIC_H_ |
/** Atomic addition. |
#define atomic_inc(x) ((void) atomic_add(x, 1)) |
#define atomic_dec(x) ((void) atomic_add(x, -1)) |
#define atomic_postinc(x) (atomic_add(x, 1) - 1) |
#define atomic_postdec(x) (atomic_add(x, -1) + 1) |
#define atomic_preinc(x) atomic_add(x, 1) |
#define atomic_predec(x) atomic_add(x, -1) |
/* Atomic addition of immediate value. |
* |
* @param val Where to add. |
* @param i Value to be added. |
* @param val Memory location to which will be the immediate value added. |
* @param i Signed immediate that will be added to *val. |
* |
* @return Value after addition. |
* |
*/ |
static inline long atomic_add(atomic_t *val, int i) |
{ |
int ret; |
volatile long *mem = &(val->count); |
volatile long * mem = &(val->count); |
asm volatile ( |
"1:\n" |
"ldr r2, [%[mem]]\n" |
"add r3, r2, %[i]\n" |
"str r3, %[ret]\n" |
"swp r3, r3, [%[mem]]\n" |
"cmp r3, r2\n" |
"bne 1b\n" |
: [ret] "=m" (ret) |
: [mem] "r" (mem), [i] "r" (i) |
"1: \n" |
"ldr r2, [%1] \n" |
"add r3, r2, %2 \n" |
"str r3, %0 \n" |
"swp r3, r3, [%1] \n" |
"cmp r3, r2 \n" |
"bne 1b \n" |
: "=m" (ret) |
: "r" (mem), "r" (i) |
: "r3", "r2" |
); |
return ret; |
} |
} |
/** Atomic increment. |
* |
* @param val Variable to be incremented. |
*/ |
static inline void atomic_inc(atomic_t *val) |
{ |
atomic_add(val, 1); |
} |
/** Atomic decrement. |
* |
* @param val Variable to be decremented. |
*/ |
static inline void atomic_dec(atomic_t *val) { |
atomic_add(val, -1); |
} |
/** Atomic pre-increment. |
* |
* @param val Variable to be incremented. |
* @return Value after incrementation. |
*/ |
static inline long atomic_preinc(atomic_t *val) |
{ |
return atomic_add(val, 1); |
} |
/** Atomic pre-decrement. |
* |
* @param val Variable to be decremented. |
* @return Value after decrementation. |
*/ |
static inline long atomic_predec(atomic_t *val) |
{ |
return atomic_add(val, -1); |
} |
/** Atomic post-increment. |
* |
* @param val Variable to be incremented. |
* @return Value before incrementation. |
*/ |
static inline long atomic_postinc(atomic_t *val) |
{ |
return atomic_add(val, 1) - 1; |
} |
/** Atomic post-decrement. |
* |
* @param val Variable to be decremented. |
* @return Value before decrementation. |
*/ |
static inline long atomic_postdec(atomic_t *val) |
{ |
return atomic_add(val, -1) + 1; |
} |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/asm.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* Copyright (c) 2003-2004 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
26,72 → 26,34 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Declarations of functions implemented in assembly. |
*/ |
#ifndef KERN_arm32_ASM_H_ |
#define KERN_arm32_ASM_H_ |
#include <typedefs.h> |
#include <arch/types.h> |
#include <arch/stack.h> |
#include <config.h> |
#include <arch/interrupt.h> |
/** No such instruction on ARM to sleep CPU. */ |
static inline void cpu_sleep(void) |
{ |
// not implemented on gxemul |
} |
static inline void pio_write_8(ioport8_t *port, uint8_t v) |
{ |
*port = v; |
} |
static inline void pio_write_16(ioport16_t *port, uint16_t v) |
{ |
*port = v; |
} |
static inline void pio_write_32(ioport32_t *port, uint32_t v) |
{ |
*port = v; |
} |
static inline uint8_t pio_read_8(ioport8_t *port) |
{ |
return *port; |
} |
static inline uint16_t pio_read_16(ioport16_t *port) |
{ |
return *port; |
} |
static inline uint32_t pio_read_32(ioport32_t *port) |
{ |
return *port; |
} |
/** Return base address of current stack. |
* |
/** Return base address of current stack |
* |
* Return the base address of the current stack. |
* The stack is assumed to be STACK_SIZE bytes long. |
* The stack must start on page boundary. |
* |
*/ |
static inline uintptr_t get_stack_base(void) |
{ |
uintptr_t v; |
asm volatile ( |
"and %[v], sp, %[size]\n" |
: [v] "=r" (v) |
: [size] "r" (~(STACK_SIZE - 1)) |
); |
asm volatile ("and %0, sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
return v; |
} |
100,6 → 62,12 |
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
uintptr_t entry); |
extern ipl_t interrupts_disable(void); |
extern ipl_t interrupts_enable(void); |
extern void interrupts_restore(ipl_t ipl); |
extern ipl_t interrupts_read(void); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/context.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Thread context. |
*/ |
#ifndef KERN_arm32_CONTEXT_H_ |
39,18 → 38,22 |
#include <align.h> |
#include <arch/stack.h> |
/* Put one item onto the stack to support get_stack_base() and align it up. */ |
/* |
* Put one item onto the stack to support get_stack_base() and align it up. |
*/ |
#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) |
#ifndef __ASM__ |
#include <arch/types.h> |
/** Thread context containing registers that must be preserved across function |
* calls. |
/* |
* Only save registers that must be preserved across |
* function calls. |
*/ |
typedef struct { |
uint32_t cpu_mode; |
uintptr_t sp; |
uintptr_t pc; |
59,14 → 62,12 |
uint32_t r6; |
uint32_t r7; |
uint32_t r8; |
uint32_t r9; |
uint32_t r10; |
uint32_t r11; |
ipl_t ipl; |
} context_t; |
#endif /* __ASM__ */ |
#endif |
/branches/arm/kernel/arch/arm32/include/cpu.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief CPU identification. |
*/ |
#ifndef KERN_arm32_CPU_H_ |
39,25 → 38,20 |
#include <arch/types.h> |
#include <arch/asm.h> |
/** Struct representing ARM CPU identifiaction. */ |
typedef struct { |
/** Implementator (vendor) number. */ |
uint32_t imp_num; |
/** Variant number. */ |
uint32_t variant_num; |
/** Architecture number. */ |
uint32_t arch_num; |
/** Primary part number. */ |
uint32_t prim_part_num; |
/** Revision number. */ |
uint32_t rev_num; |
/** Implementator (vendor) number */ |
uint32_t imp_num; |
/** Variant number */ |
uint32_t variant_num; |
/** Architecture number */ |
uint32_t arch_num; |
/** Primary part number */ |
uint32_t prim_part_num; |
/** Revision number */ |
uint32_t rev_num; |
} cpu_arch_t; |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/regutils.h |
---|
26,66 → 26,64 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** |
* @file |
* @brief Utilities for convenient manipulation with ARM registers. |
* @brief Utilities for convenient manipulation with ARM registries. |
*/ |
#ifndef KERN_arm32_REGUTILS_H_ |
#define KERN_arm32_REGUTILS_H_ |
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1f |
#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
#define STATUS_REG_IE_ENABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1F |
/* ARM Processor Operation Modes */ |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
/* [CS]PRS manipulation macros */ |
#define GEN_STATUS_READ(nm,reg) \ |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm volatile( \ |
"mrs %[retval], " #reg \ |
: [retval] "=r" (retval) \ |
); \ |
return retval; \ |
} |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm("mrs %0, " #reg : "=r"(retval)); \ |
return retval; \ |
} |
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm volatile( \ |
"msr " #reg "_" #field ", %[value]" \ |
:: [value] "r" (value) \ |
); \ |
} |
static void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
} |
/** Returns the value of CPSR (Current Program Status Register). */ |
/** Returns the value of CPSR (Current Program Status Register). |
*/ |
GEN_STATUS_READ(current, cpsr) |
/** Sets control bits of CPSR. */ |
/** Sets control bits of CPSR |
*/ |
GEN_STATUS_WRITE(current, cpsr, control, c); |
/** Returns the value of SPSR (Saved Program Status Register). */ |
/** Returns the value of SPSR (Saved Program Status Register). |
*/ |
GEN_STATUS_READ(saved, spsr) |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/console.h |
---|
0,0 → 1,43 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_CONSOLE_H_ |
#define KERN_arm32_CONSOLE_H_ |
extern void console_init(devno_t devno); |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/asm/boot.h |
---|
26,19 → 26,19 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Initial kernel start. |
*/ |
#ifndef KERN_arm32_ASM_BOOT_H_ |
#define KERN_arm32_ASM_BOOT_H_ |
/** Size of a temporary stack used for initial kernel start. */ |
#define TEMP_STACK_SIZE 0x100 |
/* Temporary stack size for boot process */ |
#define TEMP_STACK_SIZE 0x100 |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/boot.h |
---|
0,0 → 1,48 |
/* |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
#ifndef KERN_arm32_BOOT_H_ |
#define KERN_arm32_BOOT_H_ |
#define TASKMAP_MAX_RECORDS 32 |
#include <arch/types.h> |
typedef struct { |
uintptr_t addr; |
uint32_t size; |
} utask_t; |
typedef struct { |
uint32_t cnt; |
utask_t tasks[TASKMAP_MAX_RECORDS]; |
} bootinfo_t; |
extern bootinfo_t bootinfo; |
#endif |
/branches/arm/kernel/arch/arm32/include/types.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
* Copyright (c) 2003-2007 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,17 → 30,14 |
* @{ |
*/ |
/** @file |
* @brief Type definitions. |
*/ |
#ifndef KERN_arm32_TYPES_H_ |
#define KERN_arm32_TYPES_H_ |
#ifndef DOXYGEN |
# define ATTRIBUTE_PACKED __attribute__ ((packed)) |
#else |
# define ATTRIBUTE_PACKED |
#endif |
#define NULL 0 |
#define false 0 |
#define true 1 |
typedef signed char int8_t; |
typedef signed short int16_t; |
53,6 → 50,8 |
typedef unsigned long long uint64_t; |
typedef uint32_t size_t; |
typedef uint32_t count_t; |
typedef uint32_t index_t; |
typedef uint32_t uintptr_t; |
typedef uint32_t pfn_t; |
62,39 → 61,58 |
typedef uint32_t unative_t; |
typedef int32_t native_t; |
typedef uint8_t bool; |
typedef uint64_t task_id_t; |
typedef uint32_t context_id_t; |
typedef int32_t inr_t; |
typedef int32_t devno_t; |
/** Page Table Entry. */ |
typedef struct { |
} fncptr_t; |
/**PageTables are so different that we have different types |
* for level 0 and level1 page table entries |
*/ |
unsigned dummy : 32; |
} pte_t; |
#define PRIp "x" /**< Format for uintptr_t. */ |
#define PRIs "u" /**< Format for size_t. */ |
typedef struct { |
unsigned descriptor_type : 2; |
unsigned machine_depend : 3; // Alf: ???? v Architecture previev neni vyznam definovan |
unsigned domain : 4; |
unsigned should_be_zero : 1; |
unsigned coarse_table_addr : 22; |
} __attribute__ ((packed)) pte_level0_t; |
#define PRId8 "d" /**< Format for int8_t. */ |
#define PRId16 "d" /**< Format for int16_t. */ |
#define PRId32 "d" /**< Format for int32_t. */ |
#define PRId64 "lld" /**< Format for int64_t. */ |
#define PRIdn "d" /**< Format for native_t. */ |
//TODO Alf: Comments |
typedef struct { |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned access_permission_0 : 2; |
unsigned access_permission_1 : 2; |
unsigned access_permission_2 : 2; |
unsigned access_permission_3 : 2; |
unsigned frame_base_addr : 20; |
} __attribute__ ((packed)) pte_level1_t; |
#define PRIu8 "u" /**< Format for uint8_t. */ |
#define PRIu16 "u" /**< Format for uint16_t. */ |
#define PRIu32 "u" /**< Format for uint32_t. */ |
#define PRIu64 "llu" /**< Format for uint64_t. */ |
#define PRIun "u" /**< Format for unative_t. */ |
/// Page table level 1 access permission constants |
/// User no acess, kernel no access |
#define pte_ap_user_no_kernel_no 0 |
/// User no acess, kernel read/write |
#define pte_ap_user_no_kernel_rw 1 |
/// User read only, kernel read/write |
#define pte_ap_user_ro_kernel_rw 2 |
/// User read/write, kernel read/write |
#define pte_ap_user_rw_kernel_rw 2 |
#define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */ |
#define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */ |
#define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */ |
#define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */ |
#define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ |
/// Value of descriptor_type in pte_level0_t and pte_level1_t that signal not present flag |
#define pte_descriptor_not_preset 0 |
/// Value of descriptor_type in pte_level0_t that signal a coarse page table format |
#define pte_descriptor_coarse_table 1 |
/// Value of descriptor_type in pte_level1_t that signal a small page table entry format |
#define pte_descriptor_small_page 2 |
/** Page table entry. |
* |
* We have different structs for level 0 and level 1 page table entries. |
* See page.h for definition of pte_level*_t. |
*/ |
typedef struct { |
unsigned dummy : 32; |
} pte_t; |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/fpu_context.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* Copyright (c) 2005 Jakub Vana |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,9 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief FPU context (not implemented). |
* |
* GXemul doesn't support FPU on its ARM CPU. |
*/ |
#ifndef KERN_arm32_FPU_CONTEXT_H_ |
40,7 → 37,7 |
#include <arch/types.h> |
#define FPU_CONTEXT_ALIGN 0 |
#define FPU_CONTEXT_ALIGN 0 /* TODO */ |
typedef struct { |
} fpu_context_t; |
/branches/arm/kernel/arch/arm32/include/cycle.h |
---|
1,5 → 1,5 |
/* |
* Copyright (c) 2007 Michal Kebrt |
* Copyright (c) 2006 Martin Decky |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
30,20 → 30,14 |
* @{ |
*/ |
/** @file |
* @brief Count of CPU cycles. |
*/ |
#ifndef KERN_arm32_CYCLE_H_ |
#define KERN_arm32_CYCLE_H_ |
/** Returns count of CPU cycles. |
* |
* No such instruction on ARM to get count of cycles. |
* |
* @return Count of CPU cycles. |
*/ |
static inline uint64_t get_cycle(void) |
{ |
/* TODO */ |
return 0; |
} |
/branches/arm/kernel/arch/arm32/include/byteorder.h |
---|
0,0 → 1,61 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_BYTEORDER_H_ |
#define KERN_arm32_BYTEORDER_H_ |
#include <byteorder.h> |
#ifdef BIG_ENDIAN |
#define uint32_t_le2host(n) uint32_t_byteorder_swap(n) |
#define uint64_t_le2host(n) uint64_t_byteorder_swap(n) |
#define uint32_t_be2host(n) (n) |
#define uint64_t_be2host(n) (n) |
#else |
#define uint32_t_le2host(n) (n) |
#define uint64_t_le2host(n) (n) |
#define uint32_t_be2host(n) uint32_t_byteorder_swap(n) |
#define uint64_t_be2host(n) uint64_t_byteorder_swap(n) |
#endif |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/elf.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief ARM ELF constants. |
*/ |
#ifndef KERN_arm32_ELF_H_ |
/branches/arm/kernel/arch/arm32/include/memstr.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Memory manipulating functions declarations. |
*/ |
#ifndef KERN_arm32_MEMSTR_H_ |
38,10 → 37,10 |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
extern void memsetw(void *dst, size_t cnt, uint16_t x); |
extern void memsetb(void *dst, size_t cnt, uint8_t x); |
extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); |
extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); |
extern int memcmp(const void *a, const void *b, size_t cnt); |
extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); |
#endif |
/branches/arm/kernel/arch/arm32/include/arg.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Empty. |
*/ |
#ifndef KERN_arm32_ARG_H_ |
/branches/arm/kernel/arch/arm32/include/arch.h |
---|
26,36 → 26,15 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Empty. |
*/ |
#ifndef KERN_arm32_ARCH_H_ |
#define KERN_arm32_ARCH_H_ |
#define TASKMAP_MAX_RECORDS 32 |
#define CPUMAP_MAX_RECORDS 32 |
#define BOOTINFO_TASK_NAME_BUFLEN 32 |
#include <typedefs.h> |
typedef struct { |
uintptr_t addr; |
uint32_t size; |
char name[BOOTINFO_TASK_NAME_BUFLEN]; |
} utask_t; |
typedef struct { |
uint32_t cnt; |
utask_t tasks[TASKMAP_MAX_RECORDS]; |
} bootinfo_t; |
extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/proc/task.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Task related declarations. |
*/ |
#ifndef KERN_arm32_TASK_H_ |
/branches/arm/kernel/arch/arm32/include/proc/thread.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Thread related declarations. |
*/ |
#ifndef KERN_arm32_THREAD_H_ |
47,3 → 46,4 |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/faddr.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Function address conversion. |
*/ |
#ifndef KERN_arm32_FADDR_H_ |
38,10 → 37,6 |
#include <arch/types.h> |
/** Calculate absolute address of function referenced by fptr pointer. |
* |
* @param fptr Function pointer. |
*/ |
#define FADDR(fptr) ((uintptr_t) (fptr)) |
#endif |
/branches/arm/kernel/arch/arm32/include/debug.h |
---|
30,7 → 30,6 |
* @{ |
*/ |
/** @file |
* @brief Empty. |
*/ |
#ifndef KERN_arm32_DEBUG_H_ |
/branches/arm/kernel/arch/arm32/include/barrier.h |
---|
26,11 → 26,10 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
* @brief Memory barriers. |
*/ |
#ifndef KERN_arm32_BARRIER_H_ |
39,16 → 38,13 |
/* |
* TODO: implement true ARM memory barriers for macros below. |
*/ |
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") |
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") |
#define memory_barrier() asm volatile ("" ::: "memory") |
#define read_barrier() asm volatile ("" ::: "memory") |
#define write_barrier() asm volatile ("" ::: "memory") |
#define memory_barrier() asm volatile ("" ::: "memory") |
#define read_barrier() asm volatile ("" ::: "memory") |
#define write_barrier() asm volatile ("" ::: "memory") |
#define smc_coherence(a) |
#define smc_coherence_block(a, l) |
#endif |
/** @} |