63,10 → 63,10 |
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]) & 0xfffffc00 ) |
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]) & 0xfffff000 ) |
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
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#define SET_PTL0_ADDRESS_ARCH(ptl0) // TODO |
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
82,7 → 82,7 |
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1t *)(ptl3), (index_t)(i), (x)) |
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
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#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
102,7 → 102,7 |
pte_level0_t *p = &pt[i]; |
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return ( |
( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( 1 << PAGE_READ_SHIFT ) | |
( 1 << PAGE_EXEC_SHIFT ) | |
( 1 << PAGE_CACHEABLE ) |
111,12 → 111,12 |
); |
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} |
static inline int get_pt_level1_flags(pte_t *pt, index_t i) |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
{ |
pte_level1_t *p = &pt[i]; |
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return ( |
( p->destriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
136,11 → 136,11 |
pte_level0_t *p = &pt[i]; |
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if ( flags & PAGE_NOT_PRESENT ) { |
p->destriptor_type = pte_descriptor_not_preset; |
p->descriptor_type = pte_descriptor_not_preset; |
p->should_be_zero = 1; |
} else |
{ |
p->destriptor_type = pte_descriptor_coarse_table; |
p->descriptor_type = pte_descriptor_coarse_table; |
p->should_be_zero = 0; |
} |
return; |
154,11 → 154,11 |
pte_level1_t *p = &pt[i]; |
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if ( flags & PAGE_NOT_PRESENT ) { |
p->destriptor_type = pte_descriptor_not_preset; |
p->descriptor_type = pte_descriptor_not_preset; |
p->access_permission_3 = 1; // Ensure not all bits set to zero ... correct acess rights are stored in other 0-2 access permission entries |
} else |
{ |
p->destriptor_type = pte_descriptor_coarse_table; |
p->descriptor_type = pte_descriptor_coarse_table; |
p->access_permission_3 = p->access_permission_0; |
} |
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