42,9 → 42,9 |
*/ |
ipl_t interrupts_disable(void) |
{ |
ipl_t ipl = status_reg_read(); |
ipl_t ipl = current_status_reg_read(); |
|
status_reg_control_write(ipl & ~status_reg_ie_enabled_bit); |
current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
|
return ipl; |
} |
55,9 → 55,9 |
*/ |
ipl_t interrupts_enable(void) |
{ |
ipl_t ipl = status_reg_read(); |
ipl_t ipl = current_status_reg_read(); |
|
status_reg_control_write(ipl | status_reg_ie_enabled_bit); |
current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
|
return ipl; |
} |
68,7 → 68,8 |
*/ |
void interrupts_restore(ipl_t ipl) |
{ |
status_reg_control_write(status_reg_read() | (ipl & status_reg_ie_enabled_bit)); |
current_status_reg_control_write(current_status_reg_read() | |
(ipl & STATUS_REG_IE_ENABLED_BIT)); |
} |
|
/** Read interrupt priority level. |
77,7 → 78,7 |
*/ |
ipl_t interrupts_read(void) |
{ |
return status_reg_read(); |
return current_status_reg_read(); |
} |
|
/** @} |