/branches/arm/boot/arch/arm32/loader/mm.h |
---|
73,10 → 73,11 |
#ifndef __ASM__ |
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized |
* pages). Used only for booting the kernel. */ |
typedef struct { |
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION (0b10) |
unsigned descriptor_type : 2; |
unsigned bufferable : 1; |
unsigned cacheable : 1; |
unsigned impl_specific : 1; |
88,23 → 89,55 |
} __attribute__ ((packed)) pte_level0_section; |
/** Page table that holds 1:1 mapping for booting the kernel. */ |
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
/** Starts the MMU - initializes page table and enables paging. */ |
void mmu_start(void); |
/** Enables paging. */ |
static inline void enable_paging() |
{ |
/* c3 - each two bits controls access to the one of domains (16) |
* 0b01 - behave as a client (user) of a domain |
*/ |
asm volatile ( |
// behave as a client of domains |
"ldr r0, =0x55555555 \n" |
"mcr p15, 0, r0, c3, c0, 0 \n" |
// current settings |
"mrc p15, 0, r0, c1, c0, 0 \n" |
/* TODO: talk to Alf why needed |
// mask to disable aligment checks; system & rom bit set to 0 (has no |
// special effect) |
"ldr r1, =0xfffffe8f \n" |
"and r0, r0, r1 \n" |
*/ |
// mask to enable paging |
"ldr r1, =0x00000001 \n" |
"orr r0, r0, r1 \n" |
// store settings |
"mcr p15, 0, r0, c1, c0, 0 \n" |
: |
: |
: "r0", "r1" |
); |
} |
/** Sets the address of level 0 page table. |
* \param pt pointer to the page table to set |
*/ |
static inline void set_ptl0_address( pte_level0_section* pt) { |
static inline void set_ptl0_address(pte_level0_section* pt) |
{ |
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
: |
: "r"(pt) |
: |
: "r"(pt) |
); |
} |
/** Page table that holds 1:1 mapping for booting the kernel. */ |
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH]; |
/** Sets memory mapping for kernel */ |
void mm_kernel_mapping(void); |
#endif |
#endif |
/branches/arm/boot/arch/arm32/loader/main.c |
---|
33,7 → 33,7 |
#include "mm.h" |
#define KERNEL_PHY_ADDRESS 0x00100000 |
#define KERNEL_VIRTUAL_ADDRESS 0x80100000 |
char *release = RELEASE; |
56,8 → 56,10 |
release, revision, timestamp); |
} |
/** Copies all images to #KERNEL_VIRTUAL_ADDRESS and jumps there. */ |
void bootstrap(void) |
{ |
mmu_start(); |
version_print(); |
component_t components[COMPONENTS]; |
65,7 → 67,7 |
init_components(components); |
printf("\nMemory statistics\n"); |
printf(" kernel entry point at %L\n", KERNEL_PHY_ADDRESS); |
printf(" kernel entry point at %L\n", KERNEL_VIRTUAL_ADDRESS); |
printf(" %L: boot info structure\n", &bootinfo); |
unsigned int i, j; |
80,9 → 82,9 |
for (i = 0; i < COMPONENTS; i++) { |
printf(" %s...", components[i].name); |
top = ALIGN_UP(top, PAGE_SIZE); |
memcpy(((void *) KERNEL_PHY_ADDRESS) + top, components[i].start, components[i].size); |
memcpy(((void *) KERNEL_VIRTUAL_ADDRESS) + top, components[i].start, components[i].size); |
if (i > 0) { |
bootinfo.tasks[bootinfo.cnt].addr = ((void *) KERNEL_PHY_ADDRESS) + top; |
bootinfo.tasks[bootinfo.cnt].addr = ((void *) KERNEL_VIRTUAL_ADDRESS) + top; |
bootinfo.tasks[bootinfo.cnt].size = components[i].size; |
bootinfo.cnt++; |
} |
91,9 → 93,7 |
printf("done.\n"); |
} |
mm_kernel_mapping(); |
printf("\nBooting the kernel...\n"); |
jump_to_kernel((void *) PA2KA(KERNEL_PHY_ADDRESS), &bootinfo, sizeof(bootinfo)); |
jump_to_kernel((void *) KERNEL_VIRTUAL_ADDRESS, &bootinfo, sizeof(bootinfo)); |
} |
/branches/arm/boot/arch/arm32/loader/mm.c |
---|
34,6 → 34,7 |
#include "mm.h" |
/** Initializes section page table entry. |
* |
* Will be readable/writable by kernel with no access from user mode. |
43,9 → 44,10 |
* \param frame first frame in the section (frame number) |
* \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. |
*/ |
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){ |
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame) |
{ |
pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
pte->bufferable = 0; // disable |
pte->bufferable = 0; |
pte->cacheable = 0; |
pte->impl_specific = 0; |
pte->domain = 0; |
53,14 → 55,15 |
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; |
pte->should_be_zero_2 = 0; |
pte->section_base_addr = (frame << FRAME_WIDTH) >> 20; |
}; |
} |
void mm_kernel_mapping(void) { |
static void init_page_table(void) |
{ |
int i; |
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
// create 1:1 mapping (in lower 2GB) |
// create 1:1 mapping virtual-physical (in lower 2GB) |
for(i = 0; i < first_kernel_section; i++) { |
init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION); |
} |
69,24 → 72,14 |
for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) { |
init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION); |
} |
} |
void mmu_start() { |
init_page_table(); |
set_ptl0_address(page_table); |
// enable paging |
asm volatile ( |
"ldr r0, =0x55555555 \n" |
"mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables |
"mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system |
"ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled |
"and r0, r0, r1 \n" |
"ldr r1, =0x00000001 \n" // mask to enable paging |
"orr r0, r0, r1 \n" |
"mcr p15, 0, r0, c1, c0, 0 \n" // store settings |
: |
: |
: "r0", "r1" |
); |
}; |
enable_paging(); |
} |
/** @} |
*/ |