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Regard whitespace Rev 2253 → Rev 2254

/branches/arm/boot/arch/arm32/loader/mm.c
34,6 → 34,7
 
#include "mm.h"
 
 
/** Initializes section page table entry.
*
* Will be readable/writable by kernel with no access from user mode.
43,9 → 44,10
* \param frame first frame in the section (frame number)
* \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
*/
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){
static void init_pte_level0_section(pte_level0_section* pte, unsigned frame)
{
pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
pte->bufferable = 0; // disable
pte->bufferable = 0;
pte->cacheable = 0;
pte->impl_specific = 0;
pte->domain = 0;
53,14 → 55,15
pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
pte->should_be_zero_2 = 0;
pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
};
}
 
 
void mm_kernel_mapping(void) {
static void init_page_table(void)
{
int i;
 
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
// create 1:1 mapping (in lower 2GB)
// create 1:1 mapping virtual-physical (in lower 2GB)
for(i = 0; i < first_kernel_section; i++) {
init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION);
}
69,25 → 72,15
for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) {
init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION);
}
}
 
void mmu_start() {
init_page_table();
set_ptl0_address(page_table);
enable_paging();
}
// enable paging
asm volatile (
"ldr r0, =0x55555555 \n"
"mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables
"mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system
"ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled
"and r0, r0, r1 \n"
"ldr r1, =0x00000001 \n" // mask to enable paging
"orr r0, r0, r1 \n"
"mcr p15, 0, r0, c1, c0, 0 \n" // store settings
:
:
: "r0", "r1"
);
};
 
/** @}
*/