/branches/arm/kernel/arch/arm32/include/exception.h |
---|
136,6 → 136,13 |
extern void install_exception_handlers(void); |
extern void exception_init(void); |
extern void print_istate(istate_t *istate); |
extern void reset_exception_entry(void); |
extern void irq_exception_entry(void); |
extern void fiq_exception_entry(void); |
extern void undef_instr_exception_entry(void); |
extern void prefetch_abort_exception_entry(void); |
extern void data_abort_exception_entry(void); |
extern void swi_exception_entry(void); |
#endif |
/branches/arm/kernel/arch/arm32/Makefile.inc |
---|
45,6 → 45,7 |
ARCH_SOURCES = \ |
arch/$(KARCH)/src/start.S \ |
arch/$(KARCH)/src/asm.S \ |
arch/$(KARCH)/src/exc_handler.S \ |
arch/$(KARCH)/src/arm32.c \ |
arch/$(KARCH)/src/machine_func.c \ |
arch/$(KARCH)/src/context.S \ |
/branches/arm/kernel/arch/arm32/src/exception.c |
---|
58,159 → 58,6 |
/** Size of memory block occupied by exception vectors. */ |
#define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
/** Switches to kernel stack and saves all registers there. |
* |
* Temporary exception stack is used to save a few registers |
* before stack switch takes place. |
* |
* The stack fram created by the function looks like: |
* |
* |_________________| |
* | | |
* | SPSR | |
* | | |
* |_________________| |
* | Stack Pointer | |
* | of | |
* | Previous Mode | |
* |_________________| |
* | Return address | |
* | of | |
* | Previous Mode | |
* |_________________| |
* | R0 - R12 | |
* | of | |
* | Previous Mode | |
* |_________________| |
* | Return address | |
* | from | |
* |Exception Handler| |
* |_________________| |
* | | |
* |
*/ |
inline static void setup_stack_and_save_regs() |
{ |
asm volatile ( |
"ldr r13, =exc_stack\n" |
"stmfd r13!, {r0-r3}\n" |
"mrs r1, cpsr\n" |
"bic r1, r1, #0x1f\n" |
"mrs r2, spsr\n" |
"and r0, r2, #0x1f\n" |
"cmp r0, #0x10\n" |
"bne 1f\n" |
/* prev mode was usermode */ |
"mov r0, sp\n" |
"mov r3, lr\n" |
/* Switch to supervisor mode */ |
"orr r1, r1, #0x13\n" |
"msr cpsr_c, r1\n" |
/* Load sp with [supervisor_sp] */ |
"ldr r13, =supervisor_sp\n" |
"ldr r13, [r13]\n" |
/* Populate the stack frame */ |
"msr spsr, r2\n" |
"mov lr, r3\n" |
"stmfd r13!, {lr}\n" |
"stmfd r13!, {r4-r12}\n" |
"ldmfd r0!, {r4-r7}\n" |
"stmfd r13!, {r4-r7}\n" |
"stmfd r13!, {r13, lr}^\n" |
"stmfd r13!, {r2}\n" |
"b 2f\n" |
/* mode was not usermode */ |
"1:\n" |
/* Switch to previous mode which is undoubtedly the supervisor mode */ |
"orr r1, r1, r0\n" |
"mov r0, lr\n" |
"mov r3, sp\n" |
"msr cpsr_c, r1\n" |
/* Populate the stack frame */ |
"mov r1, sp\n" |
"stmfd r13!, {r0}\n" |
"stmfd r13!, {r4-r12}\n" |
/* Store r0-r3 in r4-r7 and then push it on to stack */ |
"ldmfd r3!, {r4-r7}\n" |
"stmfd r13!, {r4-r7}\n" |
/* Push return address and stack pointer on to stack */ |
"stmfd r13!, {lr}\n" |
"stmfd r13!, {r1}\n" |
"mov lr, r0\n" |
"msr spsr, r2\n" |
"stmfd r13!, {r2}\n" |
"2:\n" |
); |
} |
/** Returns from exception mode. |
* |
* Previously saved state of registers (including control register) |
* is restored from the stack. |
*/ |
inline static void load_regs() |
{ |
asm volatile( |
"ldmfd r13!, {r0} \n" |
"msr spsr, r0 \n" |
"and r0, r0, #0x1f \n" |
"cmp r0, #0x10 \n" |
"bne 1f \n" |
/* return to user mode */ |
"ldmfd r13!, {r13, lr}^ \n" |
"b 2f \n" |
/* return to non-user mode */ |
"1:\n" |
"ldmfd r13!, {r1, r2} \n" |
"mrs r3, cpsr \n" |
"bic r3, r3, #0x1f \n" |
"orr r3, r3, r0 \n" |
"mrs r0, cpsr \n" |
"msr cpsr_c, r3 \n" |
"mov lr, r2 \n" |
"msr cpsr_c, r0 \n" |
/* actual return */ |
"2:\n" |
"ldmfd r13!, {r0-r12, pc}^\n" |
); |
} |
/** Calls exception dispatch routine. */ |
#define CALL_EXC_DISPATCH(exception) \ |
asm volatile ( \ |
"mov r0, %[exc]\n" \ |
"mov r1, r13\n" \ |
"bl exc_dispatch\n" \ |
:: [exc] "i" (exception) \ |
);\ |
/** General exception handler. |
* |
* Stores registers, dispatches the exception, |
* and finally restores registers and returns from exception processing. |
* |
* @param exception Exception number. |
*/ |
#define PROCESS_EXCEPTION(exception) \ |
setup_stack_and_save_regs(); \ |
CALL_EXC_DISPATCH(exception) \ |
load_regs(); |
/** Updates specified exception vector to jump to given handler. |
* |
* Addresses of handlers are stored in memory following exception vectors. |
232,65 → 79,6 |
} |
/** Low-level Reset Exception handler. */ |
static void reset_exception_entry(void) |
{ |
PROCESS_EXCEPTION(EXC_RESET); |
} |
/** Low-level Software Interrupt Exception handler. */ |
static void swi_exception_entry(void) |
{ |
PROCESS_EXCEPTION(EXC_SWI); |
} |
/** Low-level Undefined Instruction Exception handler. */ |
static void undef_instr_exception_entry(void) |
{ |
PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
} |
/** Low-level Fast Interrupt Exception handler. */ |
static void fiq_exception_entry(void) |
{ |
PROCESS_EXCEPTION(EXC_FIQ); |
} |
/** Low-level Prefetch Abort Exception handler. */ |
static void prefetch_abort_exception_entry(void) |
{ |
asm volatile ( |
"sub lr, lr, #4" |
); |
PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
} |
/** Low-level Data Abort Exception handler. */ |
static void data_abort_exception_entry(void) |
{ |
asm volatile ( |
"sub lr, lr, #8" |
); |
PROCESS_EXCEPTION(EXC_DATA_ABORT); |
} |
/** Low-level Interrupt Exception handler. |
* |
* CPU is switched to Undefined mode before further interrupt processing |
* because of possible occurence of nested interrupt exception, which |
* would overwrite (and thus spoil) stack pointer. |
*/ |
static void irq_exception_entry(void) |
{ |
asm volatile ( |
"sub lr, lr, #4" |
); |
PROCESS_EXCEPTION(EXC_IRQ) |
} |
/** Software Interrupt handler. |
* |
* Dispatches the syscall. |
/branches/arm/kernel/arch/arm32/src/start.S |
---|
35,11 → 35,33 |
.global supervisor_sp |
kernel_image_start: |
# initialize Stack pointer for exception modes |
mrs r4, cpsr |
bic r4, r4, #0x1f |
#FIQ Mode |
orr r3, r4, #0x11 |
msr cpsr_c, r3 |
ldr sp, =exc_stack |
#IRQ Mode |
orr r3, r4, #0x12 |
msr cpsr_c, r3 |
ldr sp, =exc_stack |
#ABORT Mode |
orr r3, r4, #0x17 |
msr cpsr_c, r3 |
ldr sp, =exc_stack |
#UNDEFINED Mode |
orr r3, r4, #0x1b |
msr cpsr_c, r3 |
ldr sp, =exc_stack |
# switch to supervisor mode |
mrs r3, cpsr |
bic r3, r3, #0x1f |
orr r3, r3, #0x13 |
orr r3, r4, #0x13 |
msr cpsr_c, r3 |
ldr sp, =temp_stack |
/branches/arm/kernel/arch/arm32/src/exc_handler.S |
---|
0,0 → 1,199 |
# |
# Copyright (c) 2009 Vineeth Pillai |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions |
# are met: |
# |
# - Redistributions of source code must retain the above copyright |
# notice, this list of conditions and the following disclaimer. |
# - Redistributions in binary form must reproduce the above copyright |
# notice, this list of conditions and the following disclaimer in the |
# documentation and/or other materials provided with the distribution. |
# - The name of the author may not be used to endorse or promote products |
# derived from this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
.text |
.global irq_exception_entry |
.global fiq_exception_entry |
.global data_abort_exception_entry |
.global prefetch_abort_exception_entry |
.global undef_instr_exception_entry |
.global swi_exception_entry |
.global reset_exception_entry |
# Switches to kernel stack and saves all registers there. |
# |
# The stack frame created by the function looks like: |
# |
# |_________________| |
# | | |
# | SPSR | |
# | | |
# |_________________| |
# | Stack Pointer | |
# | of | |
# | Previous Mode | |
# |_________________| |
# | Return address | |
# | of | |
# | Previous Mode | |
# |_________________| |
# | R0 - R12 | |
# | of | |
# | Previous Mode | |
# |_________________| |
# | Return address | |
# | from | |
# |Exception Handler| |
# |_________________| |
# | | |
# |
# |
.macro SAVE_REGS_TO_STACK |
stmfd r13!, {r0-r3} |
mov r3, sp |
add sp, sp, #16 |
mrs r1, cpsr |
bic r1, r1, #0x1f |
mrs r2, spsr |
and r0, r2, #0x1f |
cmp r0, #0x10 |
bne 1f |
# prev mode was usermode |
mov r0, lr |
# Switch to supervisor mode |
orr r1, r1, #0x13 |
msr cpsr_c, r1 |
# Load sp with [supervisor_sp] |
ldr r13, =supervisor_sp |
ldr r13, [r13] |
# Populate the stack frame |
msr spsr, r2 |
mov lr, r0 |
stmfd r13!, {lr} |
stmfd r13!, {r4-r12} |
ldmfd r3!, {r4-r7} |
stmfd r13!, {r4-r7} |
stmfd r13!, {r13, lr}^ |
stmfd r13!, {r2} |
b 2f |
# mode was not usermode |
1: |
# Switch to previous mode which is undoubtedly the supervisor mode |
orr r1, r1, r0 |
mov r0, lr |
msr cpsr_c, r1 |
# Populate the stack frame |
mov r1, sp |
stmfd r13!, {r0} |
stmfd r13!, {r4-r12} |
# Store r0-r3 in r4-r7 and then push it on to stack |
ldmfd r3!, {r4-r7} |
stmfd r13!, {r4-r7} |
# Push return address and stack pointer on to stack |
stmfd r13!, {lr} |
stmfd r13!, {r1} |
mov lr, r0 |
msr spsr, r2 |
stmfd r13!, {r2} |
2: |
.endm |
.macro LOAD_REGS_FROM_STACK |
ldmfd r13!, {r0} |
msr spsr, r0 |
and r0, r0, #0x1f |
cmp r0, #0x10 |
bne 1f |
# return to user mode |
ldmfd r13!, {r13, lr}^ |
b 2f |
# return to non-user mode |
1: |
ldmfd r13!, {r1, lr} |
2: |
ldmfd r13!, {r0-r12, pc}^ |
.endm |
reset_exception_entry: |
SAVE_REGS_TO_STACK |
mov r0, #0 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
irq_exception_entry: |
sub lr, lr, #4 |
SAVE_REGS_TO_STACK |
mov r0, #5 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
fiq_exception_entry: |
sub lr, lr, #4 |
SAVE_REGS_TO_STACK |
mov r0, #6 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
undef_instr_exception_entry: |
SAVE_REGS_TO_STACK |
mov r0, #1 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
prefetch_abort_exception_entry: |
sub lr, lr, #4 |
SAVE_REGS_TO_STACK |
mov r0, #3 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
data_abort_exception_entry: |
sub lr, lr, #8 |
SAVE_REGS_TO_STACK |
mov r0, #4 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |
swi_exception_entry: |
ldr r13, =exc_stack |
SAVE_REGS_TO_STACK |
mov r0, #2 |
mov r1, r13 |
bl exc_dispatch |
LOAD_REGS_FROM_STACK |