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Ignore whitespace Rev 2275 → Rev 2276

/branches/arm/kernel/arch/arm32/include/types.h
68,68 → 68,15
typedef int32_t inr_t;
typedef int32_t devno_t;
 
 
/** Page table entry.
*
*
* We have different structs for level 0 and level 1 page table entries.
* Note: See page.h for pte_level*_t types of different levels of page table.
* */
typedef struct {
unsigned dummy : 32;
unsigned dummy : 32;
} pte_t;
 
/** Level 0 page table entry. */
typedef struct {
/* 01b for coarse tables, see below for details */
unsigned descriptor_type : 2;
unsigned impl_specific : 3;
unsigned domain : 4;
unsigned should_be_zero : 1;
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
* or large (64KB) pages. ARM also supports fine 2nd level page tables that
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
* with 1KB per the coarse table)
*/
unsigned coarse_table_addr : 22;
} __attribute__ ((packed)) pte_level0_t;
 
/** Level 1 page table entry (small (4KB) pages used) */
typedef struct {
/* 0b10 for small pages */
unsigned descriptor_type : 2;
unsigned bufferable : 1;
unsigned cacheable : 1;
/* access permissions for each of 4 subparts of a page
* (for each 1KB when small pages used */
unsigned access_permission_0 : 2;
unsigned access_permission_1 : 2;
unsigned access_permission_2 : 2;
unsigned access_permission_3 : 2;
unsigned frame_base_addr : 20;
} __attribute__ ((packed)) pte_level1_t;
 
 
/* Level 1 page tables access permissions */
 
/** User mode: no access, privileged mode: no access */
#define PTE_AP_USER_NO_KERNEL_NO 0
/** User mode: no access, privileged mode: read/write */
#define PTE_AP_USER_NO_KERNEL_RW 1
/** User mode: read only, privileged mode: read/write */
#define PTE_AP_USER_RO_KERNEL_RW 2
/// User mode: read/write, privileged mode: read/write
#define PTE_AP_USER_RW_KERNEL_RW 3
 
 
/* pte_level0_t and pte_level1_t descriptor_type flags */
 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_NOT_PRESENT 0
/** pte_level0_t coarse page table flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_COARSE_TABLE 1
/** pte_level1_t small page table flag (used in descriptor type) */
#define PTE_DESCRIPTOR_SMALL_PAGE 2
 
 
#endif
 
/** @}
/branches/arm/kernel/arch/arm32/include/mm/page.h
55,56 → 55,108
 
#ifdef KERNEL
 
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH (2<<8) // 256
#define PTL3_ENTRIES_ARCH (2<<8) // 256
 
#define PTL0_SIZE_ARCH FOUR_FRAMES
#define PTL1_SIZE_ARCH 0
#define PTL2_SIZE_ARCH 0
#define PTL3_SIZE_ARCH ONE_FRAME
#define PTL0_SIZE_ARCH FOUR_FRAMES
#define PTL1_SIZE_ARCH 0
#define PTL2_SIZE_ARCH 0
#define PTL3_SIZE_ARCH ONE_FRAME
 
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
#define PTE_EXECUTABLE_ARCH(pte) 1
 
#define PTE_EXECUTABLE_ARCH(pte) 1
 
#ifndef __ASM__
 
/**
/** Level 0 page table entry. */
typedef struct {
/* 01b for coarse tables, see below for details */
unsigned descriptor_type : 2;
unsigned impl_specific : 3;
unsigned domain : 4;
unsigned should_be_zero : 1;
/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
* or large (64KB) pages. ARM also supports fine 2nd level page tables that
* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
* with 1KB per the coarse table)
*/
unsigned coarse_table_addr : 22;
} __attribute__ ((packed)) pte_level0_t;
 
/** Level 1 page table entry (small (4KB) pages used) */
typedef struct {
/* 0b10 for small pages */
unsigned descriptor_type : 2;
unsigned bufferable : 1;
unsigned cacheable : 1;
/* access permissions for each of 4 subparts of a page
* (for each 1KB when small pages used */
unsigned access_permission_0 : 2;
unsigned access_permission_1 : 2;
unsigned access_permission_2 : 2;
unsigned access_permission_3 : 2;
unsigned frame_base_addr : 20;
} __attribute__ ((packed)) pte_level1_t;
 
 
/* Level 1 page tables access permissions */
 
/** User mode: no access, privileged mode: no access */
#define PTE_AP_USER_NO_KERNEL_NO 0
/** User mode: no access, privileged mode: read/write */
#define PTE_AP_USER_NO_KERNEL_RW 1
/** User mode: read only, privileged mode: read/write */
#define PTE_AP_USER_RO_KERNEL_RW 2
/** User mode: read/write, privileged mode: read/write */
#define PTE_AP_USER_RW_KERNEL_RW 3
 
 
/* pte_level0_t and pte_level1_t descriptor_type flags */
 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_NOT_PRESENT 0
/** pte_level0_t coarse page table flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_COARSE_TABLE 1
/** pte_level1_t small page table flag (used in descriptor type) */
#define PTE_DESCRIPTOR_SMALL_PAGE 2
 
 
/**
* Sets the address of level 0 page table.
*
* \param pt pointer to the page table to set
111,11 → 163,11
*/
static inline void set_ptl0_addr( pte_level0_t* pt)
{
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
);
asm volatile (
"mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
);
}
 
/** Returns level 0 page table entry flags.
/branches/arm/kernel/arch/arm32/src/mm/page.c
284,6 → 284,9
print_istate(istate);
dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->lr, page, fsr.status,fsr, access);
 
/* Alf: Will be commented until stack problem will be solved ...
as_page_fault make consequent page faults
 
int ret = as_page_fault(page, access, istate);
dprintf(" as_page_fault ret:%d\n", ret);
if (ret == AS_PF_FAULT) {
291,7 → 294,7
 
panic("page fault\n");
}
 
*/
// TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures
panic("page fault ... solved\n");
 
308,11 → 311,15
print_istate(istate);
dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->lr);
 
int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate);
/* Alf: Will be commented until stack problem will be solved ...
as_page_fault make consequent page faults
 
int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate);
dprintf(" as_page_fault ret:%d\n", ret);
if (ret == AS_PF_FAULT) {
panic("page fault - instruction fetch at addr:%X\n", istate->lr);
}
*/
 
panic("Prefetch abourt ... solved");
}