/branches/arm/kernel/arch/arm32/include/exception.h |
---|
39,6 → 39,7 |
#include <arch/types.h> |
#include <arch/regutils.h> |
#define HIGH_EXCEPTION_VECTORS |
#ifdef HIGH_EXCEPTION_VECTORS |
65,6 → 66,8 |
#define EXC_IRQ 5 |
#define EXC_FIQ 6 |
/** Structure representing CPU state saved when an exception occurs. */ |
typedef struct { |
uint32_t spsr; |
uint32_t sp; |
94,21 → 97,26 |
istate->pc = retaddr; |
} |
/** Return true if exception happened while in userspace */ |
/** Return true if exception happened while in userspace. */ |
static inline int istate_from_uspace(istate_t *istate) |
{ |
return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; |
} |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
return istate->pc; |
} |
extern void setup_exception_stacks(void); |
extern void install_exception_handlers(void); |
extern void exception_init(void); |
extern void print_istate(istate_t *istate); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/regutils.h |
---|
37,29 → 37,29 |
#ifndef KERN_arm32_REGUTILS_H_ |
#define KERN_arm32_REGUTILS_H_ |
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1F |
#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7) |
#define STATUS_REG_MODE_MASK 0x1f |
#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) |
/* ARM Processor Operation Modes */ |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
#define USER_MODE 0x10 |
#define FIQ_MODE 0x11 |
#define IRQ_MODE 0x12 |
#define SUPERVISOR_MODE 0x13 |
#define ABORT_MODE 0x17 |
#define UNDEFINED_MODE 0x1b |
#define SYSTEM_MODE 0x1f |
/* [CS]PRS manipulation macros */ |
#define GEN_STATUS_READ(nm,reg) \ |
static inline uint32_t nm## _status_reg_read(void) \ |
{ \ |
uint32_t retval; \ |
asm("mrs %0, " #reg : "=r"(retval)); \ |
asm volatile("mrs %0, " #reg : "=r"(retval)); \ |
return retval; \ |
} |
66,26 → 66,22 |
#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
{ \ |
asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
} |
/** Returns the value of CPSR (Current Program Status Register). |
*/ |
/** Returns the value of CPSR (Current Program Status Register). */ |
GEN_STATUS_READ(current, cpsr) |
/** Sets control bits of CPSR |
*/ |
/** Sets control bits of CPSR. */ |
GEN_STATUS_WRITE(current, cpsr, control, c); |
/** Returns the value of SPSR (Saved Program Status Register). |
*/ |
/** Returns the value of SPSR (Saved Program Status Register). */ |
GEN_STATUS_READ(saved, spsr) |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/boot.h |
---|
26,6 → 26,12 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_BOOT_H_ |
#define KERN_arm32_BOOT_H_ |
46,3 → 52,6 |
extern bootinfo_t bootinfo; |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/types.h |
---|
68,15 → 68,17 |
typedef int32_t inr_t; |
typedef int32_t devno_t; |
/** Page table entry. |
* |
* We have different structs for level 0 and level 1 page table entries. |
* Note: See page.h for pte_level*_t types of different levels of page table. |
* */ |
* See page.h for definition of pte_level*_t. |
*/ |
typedef struct { |
unsigned dummy : 32; |
} pte_t; |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/asm.h |
---|
39,11 → 39,13 |
#include <arch/stack.h> |
#include <config.h> |
static inline void cpu_sleep(void) |
{ |
// not implemented on gxemul |
} |
/** Return base address of current stack |
* |
* Return the base address of the current stack. |
57,10 → 59,10 |
return v; |
} |
extern void cpu_halt(void); |
extern void asm_delay_loop(uint32_t t); |
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, |
uintptr_t entry); |
extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, uintptr_t entry); |
extern ipl_t interrupts_disable(void); |
extern ipl_t interrupts_enable(void); |
/branches/arm/kernel/arch/arm32/include/mm/page.h |
---|
101,6 → 101,7 |
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
#define PTE_EXECUTABLE_ARCH(pte) 1 |
#ifndef __ASM__ |
/** Level 0 page table entry. */ |
118,7 → 119,8 |
unsigned coarse_table_addr : 22; |
} __attribute__ ((packed)) pte_level0_t; |
/** Level 1 page table entry (small (4KB) pages used) */ |
/** Level 1 page table entry (small (4KB) pages used). */ |
typedef struct { |
/* 0b10 for small pages */ |
unsigned descriptor_type : 2; |
136,30 → 138,29 |
/* Level 1 page tables access permissions */ |
/** User mode: no access, privileged mode: no access */ |
/** User mode: no access, privileged mode: no access. */ |
#define PTE_AP_USER_NO_KERNEL_NO 0 |
/** User mode: no access, privileged mode: read/write */ |
/** User mode: no access, privileged mode: read/write. */ |
#define PTE_AP_USER_NO_KERNEL_RW 1 |
/** User mode: read only, privileged mode: read/write */ |
/** User mode: read only, privileged mode: read/write. */ |
#define PTE_AP_USER_RO_KERNEL_RW 2 |
/** User mode: read/write, privileged mode: read/write */ |
/** User mode: read/write, privileged mode: read/write. */ |
#define PTE_AP_USER_RW_KERNEL_RW 3 |
/* pte_level0_t and pte_level1_t descriptor_type flags */ |
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */ |
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_NOT_PRESENT 0 |
/** pte_level0_t coarse page table flag (used in descriptor_type) */ |
/** pte_level0_t coarse page table flag (used in descriptor_type). */ |
#define PTE_DESCRIPTOR_COARSE_TABLE 1 |
/** pte_level1_t small page table flag (used in descriptor type) */ |
/** pte_level1_t small page table flag (used in descriptor type). */ |
#define PTE_DESCRIPTOR_SMALL_PAGE 2 |
/** |
* Sets the address of level 0 page table. |
/** Sets the address of level 0 page table. |
* |
* \param pt pointer to the page table to set |
* @param pt Pointer to the page table to set. |
*/ |
static inline void set_ptl0_addr( pte_level0_t* pt) |
{ |
170,10 → 171,11 |
); |
} |
/** Returns level 0 page table entry flags. |
* |
* \param pt level 0 page table |
* \param i index of the entry to return |
* @param pt Level 0 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
{ |
189,10 → 191,11 |
; |
} |
/** Returns level 1 page table entry flags. |
* |
* \param pt level 1 page table |
* \param i index of the entry to return |
* @param pt Level 1 page table. |
* @param i Index of the entry to return. |
*/ |
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
{ |
211,11 → 214,12 |
; |
} |
/** Sets flags of level 0 page table entry. |
* |
* \param pt level 0 page table |
* \param i index of the entry to be changed |
* \param flags new flags |
* @param pt level 0 page table |
* @param i index of the entry to be changed |
* @param flags new flags |
*/ |
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
{ |
231,6 → 235,7 |
} |
} |
/** Sets flags of level 1 page table entry. |
* |
* We use same access rights for the whole page. When page is not preset we |
237,9 → 242,9 |
* store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
* page entry, see #PAGE_VALID_ARCH). |
* |
* \param pt level 1 page table |
* \param i index of the entry to be changed |
* \param flags new flags |
* @param pt Level 1 page table. |
* @param i Index of the entry to be changed. |
* @param flags New flags. |
*/ |
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
{ |
/branches/arm/kernel/arch/arm32/include/mm/page_fault.h |
---|
37,8 → 37,7 |
#include <arch/types.h> |
/** Decribes CP15 "fault status register" (FSR). |
*/ |
/** Decribes CP15 "fault status register" (FSR). */ |
typedef struct { |
unsigned status : 3; |
unsigned domain : 4; |
47,8 → 46,7 |
} __attribute__ ((packed)) fault_status_t; |
/** Help union used for casting integer value into #fault_status_t. |
*/ |
/** Help union used for casting integer value into #fault_status_t. */ |
typedef union { |
fault_status_t fs; |
uint32_t dummy; |
56,9 → 54,9 |
/** Simplified description of instruction code. |
* |
* \note Used for recognizing memory access instructions. |
* \see ARM architecture reference (chapter 3.1) |
* |
* @note Used for recognizing memory access instructions. |
* @see ARM architecture reference (chapter 3.1) |
*/ |
typedef struct { |
unsigned dummy1 : 4; |
84,6 → 82,7 |
extern void prefetch_abort(int n, istate_t *istate); |
extern void data_abort(int n, istate_t *istate); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/include/context.h |
---|
39,9 → 39,7 |
#include <arch/stack.h> |
/* |
* Put one item onto the stack to support get_stack_base() and align it up. |
*/ |
/* Put one item onto the stack to support get_stack_base() and align it up. */ |
#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) |
49,10 → 47,8 |
#include <arch/types.h> |
/* |
* Only save registers that must be preserved across |
* function calls. |
*/ |
/* Structure containing registers that must be preserved across function calls. */ |
typedef struct { |
uintptr_t sp; |
uintptr_t pc; |
69,6 → 65,7 |
ipl_t ipl; |
} context_t; |
#endif /* __ASM__ */ |
#endif |
/branches/arm/kernel/arch/arm32/include/debug.h |
---|
0,0 → 1,41 |
/* |
* Copyright (c) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |
* modification, are permitted provided that the following conditions |
* are met: |
* |
* - Redistributions of source code must retain the above copyright |
* notice, this list of conditions and the following disclaimer. |
* - Redistributions in binary form must reproduce the above copyright |
* notice, this list of conditions and the following disclaimer in the |
* documentation and/or other materials provided with the distribution. |
* - The name of the author may not be used to endorse or promote products |
* derived from this software without specific prior written permission. |
* |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup arm32debug |
* @{ |
*/ |
/** @file |
*/ |
#ifndef KERN_arm32_DEBUG_H_ |
#define KERN_arm32_DEBUG_H_ |
#endif |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/include/cpu.h |
---|
38,16 → 38,18 |
#include <arch/types.h> |
#include <arch/asm.h> |
/** Structure representing ARM CPU identifiaction. */ |
typedef struct { |
/** Implementator (vendor) number */ |
/** Implementator (vendor) number. */ |
uint32_t imp_num; |
/** Variant number */ |
/** Variant number. */ |
uint32_t variant_num; |
/** Architecture number */ |
/** Architecture number. */ |
uint32_t arch_num; |
/** Primary part number */ |
/** Primary part number. */ |
uint32_t prim_part_num; |
/** Revision number */ |
/** Revision number. */ |
uint32_t rev_num; |
} cpu_arch_t; |
/branches/arm/kernel/arch/arm32/include/drivers/gxemul.h |
---|
35,7 → 35,6 |
#ifndef KERN_arm32_MSIM_GXEMUL_H_ |
#define KERN_arm32_MSIM_GXEMUL_H_ |
#include <console/chardev.h> |
#define GXEMUL_IRQC_MAX_IRQ 8 |
43,7 → 42,8 |
/** Struct containing mappings of gxemul HW devices into kernel part |
* * of virtual address space. */ |
* of virtual address space. |
*/ |
typedef struct { |
uintptr_t videoram; |
uintptr_t kbd; |
72,7 → 72,6 |
void gxemul_debug_putc(char ch); |
#endif |
/** @} |
/branches/arm/kernel/arch/arm32/src/exception.c |
---|
33,6 → 33,7 |
@brief Exception handlers and exception initialization routines. |
*/ |
#include <arch/exception.h> |
#include <arch/debug/print.h> |
#include <arch/memstr.h> |
43,6 → 44,7 |
#include <print.h> |
#include <syscall/syscall.h> |
#define PREFETCH_OFFSET 0x8 |
#define BRANCH_OPCODE 0xea000000 |
#define LDR_OPCODE 0xe59ff000 |
50,9 → 52,11 |
#define EXC_VECTORS_SIZE 0x20 |
#define EXC_VECTORS 0x8 |
extern uintptr_t supervisor_sp; |
extern uintptr_t exc_stack; |
inline static void setup_stack_and_save_regs() |
{ |
asm volatile( "ldr r13, =exc_stack \n\ |
164,8 → 168,9 |
/** General exception handler. |
* Stores registers, dispatches the exception, |
* and finally restores registers and returns from exception processing. |
* |
* @param exception Exception number. |
*/ |
#define PROCESS_EXCEPTION(exception) \ |
setup_stack_and_save_regs(); \ |
CALL_EXC_DISPATCH(exception) \ |
176,8 → 181,9 |
CALL_EXC_DISPATCH(exception) \ |
LOAD_REGS_FROM_STACK*/ |
/** Updates specified exception vector to jump to given handler. |
* Addresses of handlers are stored in memory following exception vectors. |
* Addresses of handlers are stored in memory following exception vectors. |
*/ |
static void install_handler (unsigned handler_addr, unsigned* vector) |
{ |
195,30 → 201,35 |
} |
/** Low-level Reset Exception handler. */ |
static void reset_exception_entry() |
{ |
PROCESS_EXCEPTION(EXC_RESET); |
} |
/** Low-level Software Interrupt Exception handler */ |
/** Low-level Software Interrupt Exception handler. */ |
static void swi_exception_entry() |
{ |
PROCESS_EXCEPTION(EXC_SWI); |
} |
/** Low-level Undefined Instruction Exception handler */ |
/** Low-level Undefined Instruction Exception handler. */ |
static void undef_instr_exception_entry() |
{ |
PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
} |
/** Low-level Fast Interrupt Exception handler */ |
/** Low-level Fast Interrupt Exception handler. */ |
static void fiq_exception_entry() |
{ |
PROCESS_EXCEPTION(EXC_FIQ); |
} |
/** Low-level Prefetch Abort Exception handler */ |
/** Low-level Prefetch Abort Exception handler. */ |
static void prefetch_abort_exception_entry() |
{ |
asm("sub lr, lr, #4"); |
225,7 → 236,8 |
PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
} |
/** Low-level Data Abort Exception handler */ |
/** Low-level Data Abort Exception handler. */ |
static void data_abort_exception_entry() |
{ |
asm("sub lr, lr, #8"); |
233,7 → 245,7 |
} |
/** Low-level Interrupt Exception handler */ |
/** Low-level Interrupt Exception handler. */ |
static void irq_exception_entry() |
{ |
asm("sub lr, lr, #4"); |
240,6 → 252,7 |
PROCESS_EXCEPTION(EXC_IRQ); |
} |
/** Software Interrupt handler. |
* |
* Dispatches the syscall. |
257,6 → 270,7 |
istate->r4); |
} |
/** Interrupt Exception handler. |
* |
* Determines the sources of interrupt, and calls their handlers. |
266,8 → 280,8 |
machine_irq_exception(exc_no, istate); |
} |
/** Fills exception vectors with appropriate exception handlers. |
*/ |
/** Fills exception vectors with appropriate exception handlers. */ |
void install_exception_handlers(void) |
{ |
install_handler((unsigned)reset_exception_entry, |
292,9 → 306,10 |
(unsigned*)EXC_FIQ_VEC); |
} |
#ifdef HIGH_EXCEPTION_VECTORS |
/** Activates using high exception vectors addresses. */ |
static void high_vectors() |
/** Activates use of high exception vectors addresses. */ |
static void high_vectors() |
{ |
uint32_t control_reg; |
328,8 → 343,7 |
} |
/** Sets stack pointers in all supported exception modes. |
*/ |
/** Sets stack pointers in all supported exception modes. */ |
void setup_exception_stacks() |
{ |
/* switch to particular mode and set "r13" there */ |
/branches/arm/kernel/arch/arm32/src/asm.S |
---|
46,51 → 46,51 |
bic r3, r3, #3 |
cmp r1, r3 |
stmdb sp!, {r4, lr} |
beq case_4 |
case_1: |
beq 4f |
1: |
cmp r2, #0 |
movne ip, #0 |
beq case_3 |
case_2: |
beq 3f |
2: |
ldrb r3, [ip, r1] |
strb r3, [ip, r0] |
add ip, ip, #1 |
cmp ip, r2 |
bne case_2 |
case_3: |
bne 2b |
3: |
mov r0, r1 |
ldmia sp!, {r4, pc} |
case_4: |
4: |
add r3, r0, #3 |
bic r3, r3, #3 |
cmp r0, r3 |
bne case_1 |
bne 1b |
movs r4, r2, lsr #2 |
moveq lr, r4 |
beq case_6 |
beq 6f |
mov lr, #0 |
mov ip, lr |
case_5: |
5: |
ldr r3, [ip, r1] |
add lr, lr, #1 |
cmp lr, r4 |
str r3, [ip, r0] |
add ip, ip, #4 |
bne case_5 |
case_6: |
bne 5b |
6: |
ands r4, r2, #3 |
beq case_3 |
beq 3b |
mov r3, lr, lsl #2 |
add r0, r3, r0 |
add ip, r3, r1 |
mov r2, #0 |
case_7: |
7: |
ldrb r3, [r2, ip] |
strb r3, [r2, r0] |
add r2, r2, #1 |
cmp r2, r4 |
bne case_7 |
b case_3 |
bne 7b |
b 3b |
memcpy_from_uspace_failover_address: |
memcpy_to_uspace_failover_address: |
/branches/arm/kernel/arch/arm32/src/console.c |
---|
32,30 → 32,31 |
/** @file |
*/ |
#include <console/console.h> |
#include <arch/console.h> |
#include <arch/machine.h> |
void console_init(devno_t devno) |
{ |
machine_console_init(devno); |
} |
/** Acquire console back for kernel |
* |
*/ |
/** Acquire console back for kernel. */ |
void arch_grab_console(void) |
{ |
machine_grab_console(); |
} |
/** Return console to userspace |
* |
*/ |
/** Return console to userspace. */ |
void arch_release_console(void) |
{ |
machine_release_console(); |
} |
/** @} |
*/ |
/branches/arm/kernel/arch/arm32/src/arm32.c |
---|
53,6 → 53,7 |
// // uintptr_t supervisor_sp /*__attribute__ ((section (".text")))*/; |
extern uintptr_t supervisor_sp; |
void arch_pre_main(void) |
{ |
int i; |
66,6 → 67,7 |
} |
void arch_pre_mm_init(void) |
{ |
/* It is not assumed by default */ |
72,10 → 74,8 |
interrupts_disable(); |
setup_exception_stacks(); |
} |
void prefetch_exception_generator(void); |
void arch_post_mm_init(void) |
{ |
88,34 → 88,34 |
console_init(device_assign_devno()); |
//fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8); |
interrupts_enable(); |
} |
void arch_post_cpu_init(void) |
{ |
/* TODO */ |
} |
void arch_pre_smp_init(void) |
{ |
/* TODO */ |
} |
void arch_post_smp_init(void) |
{ |
/* TODO */ |
} |
/** Perform arm32 specific tasks needed before the new task is run. */ |
void before_task_runs_arch(void) |
{ |
tlb_invalidate_all(); |
/* TODO */ |
tlb_invalidate_all(); |
} |
/** Perform arm32 specific tasks needed before the new thread is scheduled. */ |
void before_thread_runs_arch(void) |
{ |
122,11 → 122,12 |
supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
} |
void after_thread_ran_arch(void) |
{ |
/* TODO */ |
} |
/** Struct to hold general purpose register values */ |
typedef struct { |
uint32_t r0; |
150,7 → 151,7 |
/** Changes processor mode and jumps to the address specified in the first parameter. |
* |
* \param kernel_uarg userspace settings (entry point, stack, ...) |
* @param kernel_uarg Userspace settings (entry point, stack, ...). |
*/ |
void userspace(uspace_arg_t *kernel_uarg) |
{ |
/branches/arm/kernel/arch/arm32/src/debug/print.c |
---|
38,8 → 38,7 |
#include <arch/machine.h> |
/** |
* Prints a character to the console. |
/** Prints a character to the console. |
* |
* @param ch Character to be printed. |
*/ |
/branches/arm/kernel/arch/arm32/src/cpu/cpu.c |
---|
38,9 → 38,12 |
#include <print.h> |
/** Number of indexes left out in the #imp_data array */ |
#define IMP_DATA_START_OFFSET 0x40 |
/** Implementators (vendor) names */ |
static char * imp_data[] = { |
"?", |
"?", /* IMP_DATA_START_OFFSET */ |
"ARM Ltd", /* 0x41 */ |
"", /* 0x42 */ |
"", /* 0x43 */ |
51,7 → 54,7 |
"Intel Corporation" /* 0x69 */ |
}; |
/** Length of imp_data array */ |
/** Length of the #imp_data array */ |
static int imp_data_length = sizeof(imp_data)/sizeof(char *); |
/** Architecture names */ |
66,20 → 69,13 |
"6" /* 0x7 */ |
}; |
/** Length of arch_data array */ |
/** Length of the #arch_data array */ |
static int arch_data_length = sizeof(arch_data)/sizeof(char *); |
void cpu_arch_init(void) |
{ |
/* TODO */ |
} |
/** |
* Retrieves processor identification from CP15 register 0. |
/** Retrieves processor identification from CP15 register 0. |
* |
* @param cpu structure for storing identification |
* @param cpu Structure for storing CPU identification. |
*/ |
static void arch_cpu_identify(cpu_arch_t * cpu) |
{ |
97,6 → 93,11 |
} |
void cpu_arch_init(void) |
{ |
} |
void cpu_identify(void) |
{ |
arch_cpu_identify(&CPU->arch); |
109,8 → 110,8 |
char * architecture = arch_data[0]; |
cpu_arch_t * cpu_arch = &m->arch; |
if ( (cpu_arch->imp_num) > 0 && (cpu_arch->imp_num < (imp_data_length + 0x40)) ) { |
vendor = imp_data[cpu_arch->imp_num - 0x40]; |
if ( (cpu_arch->imp_num) > 0 && (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET)) ) { |
vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET]; |
} |
if ( (cpu_arch->arch_num) > 0 && (cpu_arch->arch_num < arch_data_length) ) { |
119,7 → 120,6 |
printf("vendor: %s, architecture: ARM %s, part number: %x, variant: %x, revision: %x\n", |
vendor, architecture, cpu_arch->prim_part_num, cpu_arch->variant_num, cpu_arch->rev_num); |
} |
/** @} |
/branches/arm/kernel/arch/arm32/src/dummy.S |
---|
41,22 → 41,22 |
.global sys_tls_set |
calibrate_delay_loop: |
mov pc, lr // return |
mov pc, lr |
asm_delay_loop: |
mov pc, lr // return |
mov pc, lr |
fpu_context_restore: |
mov pc, lr // return |
mov pc, lr |
fpu_context_save: |
mov pc, lr // return |
mov pc, lr |
fpu_enable: |
mov pc, lr // return |
mov pc, lr |
fpu_init: |
mov pc, lr // return |
mov pc, lr |
symbol_table: |
bkpt |
68,3 → 68,4 |
0: |
bkpt |
/branches/arm/kernel/arch/arm32/src/start.S |
---|
38,7 → 38,7 |
kernel_image_start: |
#switch to system mode |
# switch to system mode |
mrs r3, cpsr |
orr r3, r3, #0x1f |
msr cpsr_c, r3 |
67,20 → 67,12 |
bl main_bsp |
b halt |
.space TEMP_STACK_SIZE |
end_stack: |
.space 1024 |
exc_stack: |
.space 4 |
supervisor_sp: |
.space 4 |
.space 4 |
halt: |
ldr r0,=0x10000010 |
ldr r1, [r0] |
b halt |